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amd geode? sc3200 processor data book amd geode? sc3200 processor data book march 2004 publication id: revision 5.1
2 amd geode? sc3200 processor data book ? 2004 advanced micro devices, inc. all rights reserved. the contents of this document are pr ovided in connection with advanced micro devices, inc. (?amd?) products. amd make s no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to s pecifications and produ ct descriptions at any time without notice. no license, whet her express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of mer- chantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intend ed, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd?s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. contacts www.amd.com pcs.support@amd.com trademarks amd, the amd arrow logo, and combinations thereof , and geode, virtual system architecture, and webpad are trademarks of advanced micro devices, inc. microsoft and windows are registered trademarks of micr osoft corporation in the united states and other jurisdictions. mmx is trademark of intel corporation. other product names used in this publication are fo r identification purposes only and may be trademarks of their respective companies.
amd geode? sc3200 processor data book 3 contents revision 5.1 contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.0 amd geode? sc3200 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.0 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 gx1 module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 video processor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 core logic module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4 super i/o module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 clock, timers, and reset logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.0 signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 ball assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 strap options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.3 multiplexing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.0 general configuration bloc k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.1 configuration block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.2 multiplexing, interrupt selection, and base address registers . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.3 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.4 high-resolution timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.5 clock generators and plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.0 superi/o module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.2 module architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.3 configuration structure / access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.4 standard configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.5 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.6 system wakeup control (swc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 5.7 access.bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.8 legacy functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4 amd geode? sc3200 processor data book contents revision 5.1 6.0 core logic module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.2 module architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.4 chipset register space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 7.0 video processor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 7.1 module architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 7.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 7.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 8.0 debugging and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 8.1 testability (jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 9.0 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 9.1 general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 9.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 9.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 10.0 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 10.1 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 10.2 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 appendix a support documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 a.1 order information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 a.2 data book revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
amd geode? sc3200 processor data book 5 list of figures revision 5.1 list of figures figure 1-1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3-1. signal groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 3-2. 432-ebga ball assignment diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 3-3. 481-tepbga ball assign ment diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 figure 4-1. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 4-2. clock generation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 4-3. recommended oscillator external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 0 figure 5-1. sio block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 5-2. detailed sio block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 5-3. structure of the standard configuration register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 5-4. standard configuration registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 5-5. recommended oscillator external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1 figure 5-6. external oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 5-7. divider chain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 5-8. power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 5-9. typical battery configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 5-10. typical battery current: battery backed power mode @ t c = 25c . . . . . . . . . . . . . . . . . 124 figure 5-11. typical battery current: normal operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 5-12. interrupt/status timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 5-13. bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 5-14. start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 5-15. access.bus data transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 5-16. access.bus acknowledge cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 5-17. a complete access.bus data tr ansaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 5-18. uart mode register bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 47 figure 5-19. ircp/sp3 register bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 6-1. core logic module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 6-2. non-posted fast-pci to isa access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 6-3. pci to isa cycles with delayed transaction enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 6-4. isa dma read from pci memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 6-5. isa dma write to pci memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 6-6. pci change to sub-isa and back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 6-7. pit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 6-8. pic interrupt controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 6-9. pci and irq interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 6-10. smi generation for nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 6-11. general purpose timer and udef trap smi tree example . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 6-12. prd table example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 6-13. ac97 v2.0 codec signal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 6-14. audio smi tree example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 6-15. typical setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 7-1. video processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 figure 7-2. ntsc 525 lines, 60 hz, odd field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 figure 7-3. ntsc 525 lines, 60 hz, even field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 figure 7-4. vip block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
6 amd geode? sc3200 processor data book list of figures revision 5.1 figure 7-5. capture video mode bob example using one video frame buffer . . . . . . . . . . . . . . . . . . 333 figure 7-6. capture video mode weave example using two video frame buffers . . . . . . . . . . . . . . . 334 figure 7-7. video block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 figure 7-8. horizontal downscaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 figure 7-9. linear interpolation calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 figure 7-10. mixer/blender block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 figure 7-11. graphics/video frame with alpha windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 figure 7-12. color key and alpha blending logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 figure 7-13. tft power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 figure 7-14. pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 figure 9-1. differential input sensitivity for common mode range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 figure 9-2. drive level and measurement points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 figure 9-3. memory controller drive level and measurement points . . . . . . . . . . . . . . . . . . . . . . . . . . 381 figure 9-4. memory controller output valid timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 figure 9-5. read data in setup and hold timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 figure 9-6. video input port timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 figure 9-7. tft timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 figure 9-8. acb signals: rising time an d falling timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 figure 9-9. acb start and stop condition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 figure 9-10. acb start condition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 figure 9-11. acb data bit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 figure 9-12. testing setup for slew rate and minimum timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 figure 9-13. v/i curves for pci output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 figure 9-14. pciclk timing and measurement points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 figure 9-15. load circuits for maximum time measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 figure 9-16. output timing measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 93 figure 9-17. input timing measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 figure 9-18. pci reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 figure 9-19. sub-isa read operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 figure 9-20. sub-isa write operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 98 figure 9-21. lpc output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 figure 9-22. lpc input timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 figure 9-23. ide reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 figure 9-24. register transfer to/from device timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 figure 9-25. pio data transfer to/from device timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 figure 9-26. multiword dma data transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 figure 9-27. initiating an ultradma data in burst timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 figure 9-28. sustained ultradma data in burst timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 figure 9-29. host pausing an ultradma data in burst timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 410 figure 9-30. device terminating an ultradma data in burst timing diagram . . . . . . . . . . . . . . . . . . . . 411 figure 9-31. host terminating an ultradma data in burst timing diagram . . . . . . . . . . . . . . . . . . . . . . 412 figure 9-32. initiating an ultradma data out burst timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 figure 9-33. sustained ultradma data out burst timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 figure 9-34. device pausing an ultradma data out burst timing diagram . . . . . . . . . . . . . . . . . . . . . . 415 figure 9-35. host terminating an ultradma data out burst timing diagram . . . . . . . . . . . . . . . . . . . . . 416 figure 9-36. device terminating an ultradma data out burst timing diagram . . . . . . . . . . . . . . . . . . . 417 figure 9-37. data signal rise and fall timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 figure 9-38. source differential data jitter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 figure 9-39. eop width timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 figure 9-40. receiver jitter tolerance timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 figure 9-41. uart, sharp-ir, sir, and consumer remote control timing diagram . . . . . . . . . . . . . . . 422 figure 9-42. fast ir (mir and fir) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 figure 9-43. standard parallel port typical data exchange timing diagram . . . . . . . . . . . . . . . . . . . . . 424 figure 9-44. enhanced parallel port timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 figure 9-45. ecp forward mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
amd geode? sc3200 processor data book 7 list of figures revision 5.1 figure 9-46. ecp reverse mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 figure 9-47. ac97 reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 figure 9-48. ac97 sync timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 figure 9-49. ac97 clocks diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 figure 9-50. ac97 data timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 figure 9-51. ac97 rise and fall timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 figure 9-52. ac97 low power mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 figure 9-53. pwrbtn# trigger and onctl# timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 figure 9-54. gpwio and onctl# timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 figure 9-55. power-up sequencing with pwrbtn# timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 434 figure 9-56. power-up sequencing without pwrbtn# timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 435 figure 9-57. tck measurement points and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 figure 9-58. jtag test timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 figure 10-1. heatsink example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 figure 10-2. 432-terminal ebga package (body size: 40x40x1.72 mm; pitch: 1.27 mm) . . . . . . . . . . . 441 figure 10-3. 481-terminal tepbga pack age (body size: 40x40x2. 38 mm; pitch: 1.27 mm) . . . . . . . . 442
8 amd geode? sc3200 processor data book list of figures revision 5.1
amd geode? sc3200 processor data book 9 list of tables revision 5.1 list of tables table 2-1. sc3200 memory controller register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2-2. sc3200 memory controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 3-1. signal definitions legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 3-2. 432-ebga ball assignment - sorted by ball number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 3-3. 432-ebga ball assignment - sorted alphabetically by signal name . . . . . . . . . . . . . . . . . . 38 table 3-4. 481-tepbga ball assign ment - sorted by ball number . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 3-5. 481-tepbga ball assign ment - sorted alphabetically by signal name . . . . . . . . . . . . . . . 54 table 3-6. strap options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 3-7. two-signal/group multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 3-8. three-signal/group multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 3-9. four-signal/group multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 4-1. general configuration block register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 4-2. multiplexing, interrupt selection, and base address registers . . . . . . . . . . . . . . . . . . . . . . . 88 table 4-3. watchdog registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 4-4. high-resolution timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 4-5. crystal oscillator circuit compone nts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 4-6. core clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 4-7. strapped core clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 4-8. clock generator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 5-1. sio configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 5-2. ldn assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 5-3. standard configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 5-4. sio control and configuration register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 5-5. sio control and configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 5-6. relevant rtc configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 5-7. rtc configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 5-8. relevant swc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 5-9. relevant ircp/sp3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 5-10. ircp/sp3 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 5-11. relevant serial ports 1 and 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 5-12. serial ports 1 and 2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 5-13. relevant acb1 and acb2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 5-14. acb1 and acb2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 table 5-15. relevant parallel port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 5-16. parallel port configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 5-17. crystal oscillator cir cuit components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 5-18. system power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 5-19. rtc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 5-20. rtc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 5-21. divider chain control / test selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 5-22. periodic interrupt rate encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 5-23. bcd and binary formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 5-24. standard ram map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 5-25. extended ram map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 5-26. time range limits for ceir protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10 amd geode? sc3200 processor data book list of tables revision 5.1 table 5-27. banks 0 and 1 - common control and status register map . . . . . . . . . . . . . . . . . . . . . . . . 133 table 5-28. bank 1 - ceir wakeup configuration and control register map . . . . . . . . . . . . . . . . . . . . 133 table 5-29. banks 0 and 1 - common control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 5-30. bank 1 - ceir wakeup configuration and control registers . . . . . . . . . . . . . . . . . . . . . . . 135 table 5-31. acb register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 5-32. acb registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 5-33. parallel port register map for first level offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 5-34. parallel port register map for second level offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 5-35. parallel port bit map for first level offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 5-36. parallel port bit map for second level offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 5-37. bank 0 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 5-38. bank selection encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 5-39. bank 1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 5-40. bank 2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 5-41. bank 3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 5-42. bank 0 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 5-43. bank 1 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 5-44. bank 2 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 5-45. bank 3 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 5-46. bank 0 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 5-47. bank selection encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 5-48. bank 1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 5-49. bank 2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 5-50. bank 3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 5-51. bank 4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 5-52. bank 5 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 5-53. bank 6 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 5-54. bank 7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 5-55. bank 0 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 5-56. bank 1 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 5-57. bank 2 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 5-58. bank 3 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 5-59. bank 4 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 5-60. bank 5 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 5-61. bank 6 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 5-62. bank 7 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 6-1. physical region descriptor format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 6-2. ultradma/33 signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 6-3. cycle multiplexed pci / sub-isa balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 6-4. pic interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 6-5. wakeup events capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 6-6. power planes control signals vs. sleep states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 6-7. power planes vs. sleep/global states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 6-8. power management events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 6-9. device power management programming summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 6-10. bus masters that drive specific slots of the ac97 interface . . . . . . . . . . . . . . . . . . . . . . . 183 table 6-11. physical region descriptor format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 6-12. cycle types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 6-13. pci configuration address register (0cf8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 6-14. f0: pci header/bridge configuration registers for gpio and lpc support summary . . . 192 table 6-15. f0bar0: gpio support registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 6-16. f0bar1: lpc support registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 6-17. f1: pci header registers for smi status and acpi support summary . . . . . . . . . . . . . . . 196 table 6-18. f1bar0: smi status registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 6-19. f1bar1: acpi support registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
amd geode? sc3200 processor data book 11 list of tables revision 5.1 table 6-20. f2: pci header registers for ide controller support summary . . . . . . . . . . . . . . . . . . . . . 198 table 6-21. f2bar4: ide controller support registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 6-22. f3: pci header registers for audio support summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 6-23. f3bar0: audio support registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 6-24. f5: pci header registers for x-bus expansion support summary . . . . . . . . . . . . . . . . . . 201 table 6-25. f5bar0: i/o control support registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 6-26. pciusb: usb pci configuration register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 6-27. usb_bar: usb controller registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 6-28. isa legacy i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support . . . . . . . . . . . 206 table 6-30. f0bar0+i/o offset: gpio configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 6-31. f0bar1+i/o offset: lpc interface configuration registers . . . . . . . . . . . . . . . . . . . . . . . . 244 table 6-32. f1: pci header registers for smi status and acpi support . . . . . . . . . . . . . . . . . . . . . . . 252 table 6-33. f1bar0+i/o offset: smi status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 table 6-34. f1bar1+i/o offset: acpi support registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 table 6-35. f2: pci header/channels 0 and 1 registers for ide controller configuration . . . . . . . . . . 273 table 6-36. f2bar4+i/o offset: ide controller configuration registers . . . . . . . . . . . . . . . . . . . . . . . . 277 table 6-37. f3: pci header registers for audio configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 6-38. f3bar0+memory offset: audio configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . 280 table 6-39. f5: pci header registers for x-bus expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 table 6-40. f5bar0+i/o offset: x-bus expansion registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 table 6-41. pciusb: usb pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 table 6-42. usb_bar+memory offset: usb controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 table 6-43. dma channel control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 table 6-44. dma page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 table 6-45. programmable interval timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 table 6-46. programmable interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1 table 6-47. keyboard controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 table 6-48. real-time clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 table 6-49. miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 table 7-1. valid mixing/blending configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 table 7-2. truth table for alpha blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 table 7-3. f4: pci header registers for video processor support summary . . . . . . . . . . . . . . . . . . . 345 table 7-4. f4bar0: video processor configuration registers summary . . . . . . . . . . . . . . . . . . . . . . 345 table 7-5. f4bar2: vip support registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 table 7-6. f4: pci header registers for video processor support registers . . . . . . . . . . . . . . . . . . . 348 table 7-7. f4bar0+memory offset: video processor configuration registers . . . . . . . . . . . . . . . . . . 350 table 7-8. f4bar2+memory offset: vip configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 table 8-1. jtag mode instruction support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 table 9-1. electro static discharge (esd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 table 9-2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 table 9-3. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 table 9-4. power planes of external interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 71 table 9-5. system conditions used to measure sc3200 current during on state . . . . . . . . . . . . . . . 372 table 9-6. dc characteristics for on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 table 9-7. dc characteristics for active idle, sleep, and off states . . . . . . . . . . . . . . . . . . . . . . . . . . 373 table 9-8. ball capacitance and inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 table 9-9. balls with pu/pd resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 table 9-10. buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 table 9-11. default levels for measurement of switching parameters . . . . . . . . . . . . . . . . . . . . . . . . . 380 table 9-12. memory controller timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 table 9-13. video input port timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 table 9-14. tft timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 table 9-15. access.bus input timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6 table 9-16. access.bus output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
12 amd geode? sc3200 processor data book list of tables revision 5.1 table 9-17. pci ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 table 9-18. pci clock parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 table 9-19. pci timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 table 9-20. measurement condition parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 table 9-21. sub-isa timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 table 9-22. lpc and serirq timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 table 9-23. ide general timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 table 9-24. ide register transfer to/from device timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 401 table 9-25. ide pio data transfer to/from device timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . 403 table 9-26. ide multiword dma data transfer timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 table 9-27. ide ultradma data burst timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 table 9-28. usb timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 table 9-29. uart, sharp-ir, sir, and consumer remote control timing parameters . . . . . . . . . . . . 422 table 9-30. fast ir port timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 table 9-31. standard parallel port timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 24 table 9-33. ecp forward mode timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 table 9-34. ecp reverse mode timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 table 9-35. ac reset timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 table 9-36. ac97 sync timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 table 9-37. ac97 clocks parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 table 9-38. ac97 i/o timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 table 9-39. ac97 signal rise and fall timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 table 9-40. ac97 low power mode timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 table 9-41. pwrbtn# timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 table 9-42. power management event (gpwio) and onctl# timing parameters . . . . . . . . . . . . . . . 433 table 9-43. power-up sequence using the power button timing parameters . . . . . . . . . . . . . . . . . . . 434 table 9-44. power-up sequence not using the power button timing parameters . . . . . . . . . . . . . . . . 435 table 9-45. jtag timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 table 10-1. q jc (c/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 table 10-2. case-to-ambient thermal resistance example @ 85c . . . . . . . . . . . . . . . . . . . . . . . . . . 439 table a-1. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 table a-2. edits to current revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
amd geode? sc3200 processor data book 13 1 amd geode? sc3200 processor revision 5.1 1.0 amd geode? sc3200 processor 1.1 general description the amd geode? sc3200 processor is a member of the amd geode family of fully integrated x86 system chips. the sc3200 processor includes: the geode gx1 processor module combines advanced cpu performance with mmx? support, fully acceler- ated 2d graphics, a 64-bit synchronous dram (sdram) interface, a pci bus controller, and a display controller. a low-power tft video processor module with a video input port (vip), and a hard ware video accelerator for scaling, filtering, and color space conversion. the core logic module includes: pc/at functionality, a usb interface, an ide interface, a pci bus interface, an lpc bus interface, advanced configuration power inter- face (acpi) version 1.0 compliant power management, and an audio codec interface. the superi/o module has: three serial ports (uart1, uart2, and uart3 with fast infrared), a parallel port, two access.bus (acb) interfaces, and a real-time clock (rtc). these features, combined with the device?s low power con- sumption, enable a small form factor design making it ideal as the core for a webpad? system application. figure 1-1 shows the relationships between the modules. figure 1-1. block diagram cpu gx1 memory controller core display controller 2d graphics accelerator pci bus controller video scaling video processor tft i/f video mixer clock & reset logic config. fast-pci bus video input port (vip) ide i/f fast x-bus pit dmac pwr mgmnt configuration isa bus i/f pic usb gpio pci/sub-isa audio codec i/f lpc i/f isa bus block bus i/f pci bus i/f parallel port acb1 i/f acb2 i/f uart1 uart2 uart3 & ir bridge rtc core logic superi/o host interface x-bus
14 amd geode? sc3200 processor data book amd geode? sc3200 processor revision 5.1 1.2 features general features 32-bit x86 processor, up to 266 mhz, with mmx instruc- tion set support memory controller with 64-bit sdram interface 2d graphics accelerator ccir-656 video input port with direct video for full screen display pc/at functionality pci bus controller ide interface, two channels usb, three ports, ohci (open host controller interface) version 1.0 compliant audio, ac97/amc97 version 2.0 compliant virtual system architecture? (vsa) technology support power management, acpi (advanced configuration power interface) version 1.0 compliant package: ? 432-terminal ebga (enhanced ball grid array) ? 481-terminal tepbga (therm ally enhanc ed plastic ball grid array) gx1 processor module cpu core: ? 32-bit x86, 266 mhz, with mmx compatible instruc- tion set support ? 16 kb unified l1 cache ? integrated fpu (floating point unit) ? re-entrant smm (system management mode) enhanced for vsa 2d graphics accelerator: ? accelerates bitblts, line draw and text ? supports all 256 raster operations ? supports transparent blts ? runs at core clock frequency memory controller: ? 64-bit sdram interface ? 66 mhz to 100 mhz frequency range ? direct interface with cpu/cache, display controller and 2d graphic accelerator ? supports clock suspend and power-down/ self-refresh ? up to two banks of sdram (8 devices total) or one sodimm display controller: ? hardware graphics frame buffer compress/ decompress ? hardware cursor, 32x32 pixels video processor module video accelerator: ? flexible video scaling support of up to 800% (horizontally and vertically) ? bilinear interpolation filter s (with two taps, and eight phases) to smooth output video video/graphics mixer: ? 8-bit value alpha blending ? three blending windows with constant alpha value ? color key video input port (vip): ? video capture or display ? ccir-656 and vesa video interface port v1.1 compliant ? lock display timing to video input timing (genlock) ? able to transfer video data into main memory ? direct video transfer for full screen display ? separate memory location for vbi tft interface: ? direct connection to tft panels ? 800x600 non-interlaced tft @ 16 bpp graphics, up to 85 hz ? 1024x768 non-interlaced tft @ 16 bpp graphics, up to 75 hz ? tft on ide: fpclk max is 40 mhz ? tft on parallel port: fpclk max is 80 mhz core logic module audio codec interface: ? ac97/amc97 (rev. 2.0) codec interface ? six dma channels pc/at functionality: ? programmable interrupt controller (pic), 8259a-equivalent ? programmable interval timer (pit), 8254-equivalent ? dma controller (dmac), 8237-equivalent power management: ? acpi v1.0 compliant ? sx state control of three power planes ? cx/sx state control of clocks and plls ? thermal event input ? wakeup event support: ? three general-purpose events ? ac97 codec event ? uart2 ri# signal ? infrared (ir) event general purpose i/os (gpios): ? 27 multiplexed gpio signals low pin count (lpc) bus interface: ? specification v1.0 compatible
amd geode? sc3200 processor data book 15 amd geode? sc3200 processor revision 5.1 pci bus interface: ? pci v2.1 compliant with wakeup capability ? 32-bit data path, up to 33 mhz ? glueless interface for an external pci device ? fixed priority ? 3.3v signal support only sub-isa bus interface: ? up to 16 mb addressing ? supports a chip select for rom or flash eprom boot device ? supports either: ? m-systems diskonchip doc2000 flash file system ? nand eeprom ? supports up to two chip selects for external i/o devices ? 8-bit (optional 16-bit) data bus width ? shares balls with pci signals ? is not a subtractive agent ide interface: ? two ide channels for up to four external ide devices ? supports ata-33 synchronous dma mode transfers, up to 33 mb/s universal serial bus (usb): ? usb openhci v1.0 compliant ? three ports superi/o module real-time clock (rtc): ? ds1287, mc146818 and pc87911 compatible ? multi-century calendar access.bus (acb) interface: ? two acb interface ports parallel port: ? epp 1.9 compliant ? ieee 1284 ecp compliant , including level 2 serial port (uart): ? uart1, 16550a compatible (sin, sout, bout pins), used for smartcard interface ? uart2, 16550a compatible ? enhanced uart with fast infrared (ir) other features high-resolution timer: ? 32-bit counter with 1 s count interval watchdog timer: ? interfaces to intr, smi, reset clocks: ? input (external crystals): ? 32.768 khz (internal clock oscillator) ? 27 mhz (internal clock oscillator) ?output: ? ac97 clock (24.576 mhz) ? memory controller clock (66 mhz to 100 mhz) ? pci clock (33 mhz) jtag testability: ? bypass, extest, sample/preload, idcode, clamp, hiz voltages ? internal logic: 266 or 233 mhz @ 1.8v ? standby logic: 266 or 233 mhz @ 1.8v ? i/o: 3.3v ? standby i/o: 3.3v ? battery (if used): 3.0v
16 amd geode? sc3200 processor data book amd geode? sc3200 processor revision 5.1
amd geode? sc3200 processor data book 17 2 architecture overview revision 5.1 2.0 architecture overview as illustrated in figure 1-1 on page 13, the sc3200 pro- cessor contains the following modules in one integrated device: gx1 module: ? combines advanced cpu performance with mmx support, fully accelerated 2d graphics, a 64-bit synchronous dram (sdram) interface and a pci bus controller. integrates gx1 silicon revision 8.1.1. video processor module: ? a low-power tft support module with a video input port, and a hardware video accelerator for scaling, filtering and color space conversion. core logic module: ? includes pc/at functionality, an ide interface, a universal serial bus (usb) interface, acpi v1.0 compliant power management, and an audio codec interface. superi/o module: ? includes two serial ports, an infrared (ir) port, a parallel port, two access.bus interfaces, and a real-time clock (rtc). 2.1 gx1 module the gx1 processor (silicon revision 8.1.1) is the central module of the sc3200. for detailed information regarding the gx1 module, refer to the amd geode? gx1 proces- sor data book and the amd geode? gx1 processor sili- con revision 8.1.1 specification update documents. the sc3200 processor?s device id is contained in the gx1 module. software can detect the revision by reading the dir0 and dir1 configuration registers (see configuration registers in the amd geode? gx1 processor data book ). the amd geode? sc3200 specification update docu- ment contains the specific values. 2.1.1 memory controller the gx1 module is connected to external sdram devices. for more information see section 3.4.2 "memory interface signals" on page 65, and the ?memory controller? chapter in the amd geode? gx1 processor data book . there are some differences in the sc3200 processor?s memory controller and the stand-alone gx1 processor?s memory controller: 1) there is drive strength/slew control in the sc3200 that is not in the gx1. the bits that control th is function are in the mc_mem_cntrl1 and mc_mem_cntrl2 registers. in the gx1 processor, these bits are marked as reserved. 2) the sc3200 supports two banks of memory. the gx1 supports four banks of memory. in addition, the sc3200 supports a maximum of eight devices and the gx1 supports up to 32 devices. with this difference, the mc_bank_cfg register is different. table 2-1 summarizes the 32-bit registers contained in the sc3200 processor?s memory controller. table 2-2 gives detailed register/bit formats.
18 amd geode? sc3200 processor data book architecture overview revision 5.1 table 2-1. sc3200 memory controller register summary gx_base+ memory offset width (bits) type name/function reset value 8400h-8403h 32 r/w mc_mem_cntrl1. memory controller control register 1 248c0040h 8404h-8407h 32 r/w mc_mem_cntrl2. memory controller control register 2 00000801h 8408h-840bh 32 r/w mc_bank_cfg. memory controller bank configuration 41104110h 840ch-840fh 32 r/w mc_sync_tim1. memory controller synchronous timing register 1 2a733225h 8414h-8417h 32 r/w mc_gbase_add. memory controller graphics base address register 00000000h 8418h-841bh 32 r/w mc_dr_add. memory controller dirty ram address register 00000000h 841ch-841fh 32 r/w mc_dr_acc. memory controller dirty ram access register 0000000xh table 2-2. sc3200 memory controller registers bit description gx_base+ 8400h-8403h mc_mem_cntrl1 (r/w) reset value: 248c0040h 31:30 mdctl ( md[63:0] drive strength). 11 is strongest, 00 is weakest. 29 rsvd (reserved ) write as 0. 28:27 mabactl ( ma[12:0] and ba[1:0] drive strength). 11 is strongest, 00 is weakest. 26 rsvd (reserved ). write as 0. 25:24 memctl ( rasa#, casa#, wea#, cs[1:0]#, ckea, dqm[7:0] drive strength). 11 is strongest, 00 is weakest. 23:22 rsvd (reserved). write as 0. 21 rsvd (reserved). must be written as 0. wait state on the x-bus x_data during read cycles - for debug only. 20:18 sdclkrate (sdram clock ratio). selects sdram clock ratio. 000: reserved 100: 3.5 001: 2 101: 4 010: 2.5 110: 4.5 011: 3 (default) 111: 5 ratio does not take effect until the sdclkstrt bit (b it 17 of this register) transitions from 0 to 1. 17 sdclkstrt (start sdclk). start operating sdclk using the new ratio and shi ft value (selected in bits [20:18] of this reg- ister). 0: clear. 1: enable. this bit must transition from zero (written to zero) to one (written to one) in order to start sdclk or to change the shift val ue. 16:8 rfshrate (refresh interval). this field determines the num ber of processor core clocks multiplied by 64 between refresh cycles to the dram. by default, the refresh inte rval is 00h. refresh is turned off by default. 7:6 rfshstag (refresh staggering). this field determines number of clocks between the rfsh commands to each of the four banks during refresh cycles: 00: 0 sdram clocks 01: 1 sdram clocks (default) 10: 2 sdram clocks 11: 4 sdram clocks staggering is used to help reduce power spik es during refresh by refreshing one bank at a time. if only one bank is installed, this field must be written as 00. 5 2clkaddr (two clock address setup). assert memory address for one extra clock before cs# is asserted. 0: disable. 1: enable. this can be used to compensate for addres s setup at high frequencies and/or high loads.
amd geode? sc3200 processor data book 19 architecture overview revision 5.1 4 rfshtst (test refresh). this bit, when set high, generates a refresh r equest. this bit is only used for testing purposes. 3 xbusarb (x-bus round robin). when round robin is enabled, processor, graphi cs pipeline, and low priority display con- troller requests are arbitrated at the same priority level. when disabled, processor requests are arbitrated at a higher priori ty level. high priority display controller requests always have the highest arbitration priority. 0: disable. 1: enable round robin. 2 smm_map (smm region mapping). maps the smm memory region at gx_ba se+400000 to physical address a0000 to bffff in sdram. 0: disable. 1: enable. 1 rsvd (reserved). write as 0. 0 sdramprg (program sdram). when this bit is set, the memory controller will program the sdram mrs register using ltmode in mc_sync_tim1. this bit must transition from zero (written to zero) to one (written to one) in order to program the sdram devices. gx_base+8404h-8407h mc_mem_cntrl2 (r/w) reset value: 00000801h 31:14 rsvd (reserved). write as 0. 13:12 sdclkctl (sdclk high drive/slew control). controls the high drive and slew rate of sdclk[3:0] and sdclk_out. 11 is strongest, 00 is weakest. 11 rsvd (reserved). write as 0. 10 sdclkomsk# (enable sdclk_out). turns on the output. 0: enable. 1: disable. 9 sdclk3msk# (enable sdclk3). turns on the output. 0: enable. 1: disable. 8 sdclk2msk# (enable sdclk2). turns on the output. 0: enable. 1: disable. 7 sdclk1msk# (enable sdclk1). turns on the output. 0 0: enable. 1: disable. 6 sdclk0msk# (enable sdclk0). turns on the output. 0: enable. 1: disable. 5:3 shftsdclk (shift sdclk). this function allows shifting sdclk to meet sdram setup and hold time requirements. the shift function will not take effect until the sdclkstrt bit (bit 17 of mc_mem_cntrl1) transitions from 0 to 1: 000: no shift 100: shift 2 core clocks 001: shift 0.5 core clock 101: shift 2.5 core clocks 010: shift 1 core clock 110: shift 3 core clocks 011: shift 1.5 core clock 111: reserved 2 rsvd (reserved). write as 0. 1 rd (read data phase). selects if read data is latched one or two core clock after the rising edge of sdclk. 0: 1 core clock. 1: 2 core clocks. 0 fstrdmsk (fast read mask). do not allow core reads to bypass the request fifo. 0: disable. 1: enable. table 2-2. sc3200 memory controller registers (continued) bit description
20 amd geode? sc3200 processor data book architecture overview revision 5.1 gx_base+8408h-840bh mc_bank_cfg (r/w) reset value: 41104110h 31:16 rsvd (reserved). write as 0070h 15 rsvd (reserved). write as 0. 14 sodimm_mod_bnk (sodimm module banks - banks 0 and 1). selects number of module banks installed per sodimm for sodimm: 0: 1 module bank (bank 0 only) 1: 2 module banks (bank 0 and 1) 13 rsvd (reserved). write as 0. 12 sodimm_comp_bnk (sodimm component banks - banks 0 and 1). selects the number of component banks per module bank for sodimm: 0: 2 component banks 1: 4 component banks banks 0 and 1 must have the same number of component banks. 11 rsvd (reserved). write as 0. 10:8 sodimm_sz (sodimm size - banks 0 and 1). selects the size of sodimm: 000: 4 mb 010: 16 mb 100: 64 mb 110: 256 mb 001: 8 mb 011: 32 mb 101: 128 mb 111: 512 mb this size is the total of both banks 0 and 1. also, banks 0 and 1 must be the same size. 7 rsvd (reserved). write as 0. 6:4 sodimm_pg_sz (sodimm page size - banks 0 and 1). selects the page size of sodimm: 000: 1 kb 010: 4 kb 1xx: 16 kb 001: 2 kb 011: 8 kb 111: sodimm not installed both banks 0 and 1 must have the same page size. 3:0 rsvd (reserved). write as 0. gx_base+840ch-840fh mc_sync_tim1 (r/w) reset value: 2a733225h 31 rsvd (reserved). write as 0. 30:28 ltmode (cas latency). cas latency is the delay, in sdram clock cycl es, between the registration of a read command and the availability of the first piece of output data. this par ameter significantly affects s ystem performance. optimal settin g should be used. if an sodimm is used, bios can interrogate eeprom across the access.bus interface to determine this value: 000: reserved 010: 2 clk 100: 4 clk 110: 6 clk 001: reserved 011: 3 clk 101: 5 clk 111: 7 clk this field will not take effect until sdramprg (bit 0 of mc_mem_ cntrl1) transitions from 0 to 1. 27:24 rc (rfsh to rfsh/act command period, trc). minimum number of sdram clock between rfsh and rfsh/act commands: 0000: reserved 0100: 5 clk 1000: 9 clk 1100: 13 clk 0001: 2 clk 0101: 6 clk 1001: 10 clk 1101: 14 clk 0010: 3 clk 0110: 7 clk 1010: 11 clk 1110: 15 clk 0011: 4 clk 0111: 8 clk 1011: 12 clk 1111: 16 clk 23:20 ras (act to pre command period, tras). minimum number of sdram cl ocks between act and pre commands: 0000: reserved 0100: 5 clk 1000: 9 clk 1100: 13 clk 0001: 2 clk 0101: 6 clk 1001: 10 clk 1101: 14 clk 0010: 3 clk 0110: 7 clk 1010: 11 clk 1110: 15 clk 0011: 4 clk 0111: 8 clk 1011: 12 clk 1111: 16 clk 19 rsvd (reserved). write as 0. 18:16 rp (pre to act command period, trp). minimum number of sdram clocks between pre and act commands: 000: reserved 010: 2 clk 100: 4 clk 110: 6 clk 001: 1 clk 011: 3 clk 101: 5 clk 111: 7 clk 15 rsvd (reserved). write as 0. 14:12 rcd (delay time act to read/wrt command, trcd). minimum number of sdram clock between act and read/ wrt commands. this parameter significantly affect s system performance. optimal setting should be used: 000: reserved 010: 2 clk 100: 4 clk 110: 6 clk 001: 1 clk 011: 3 clk 101: 5 clk 111: 7 clk table 2-2. sc3200 memory controller registers (continued) bit description
amd geode? sc3200 processor data book 21 architecture overview revision 5.1 11 rsvd (reserved). write as 0. 10:8 rrd (act(0) to act(1) command period, trrd). minimum number of sdram clocks between act and act command to two different component banks within the same module bank . the memory controller does not perform back-to-back acti- vate commands to two different component banks without a read or write command between them. hence, this field should be written as 001. 7 rsvd (reserved). write as 0. 6:4 dpl (data-in to pre command period, tdpl). minimum number of sdram clocks from the time the last write datum is sampled till the bank is precharged: 000: reserved 010: 2 clk 100: 4 clk 110: 6 clk 001: 1 clk 011: 3 clk 101: 5 clk 111: 7 clk 3:0 rsvd (reserved). leave unchanged. always returns a 101h. note: refer to the sdram manufacturer?s specific ation for more information on component banks. gx_base+8414h-8417h mc_gbase_add (r/w) reset value: 00000000h 31:18 rsvd (reserved). write as 0. 17 te (test enable test[3:0] ). 0: test[3:0] are driven low (normal operation). 1: test[3:0] pins are used to output test information 16 tectl (test enable shared control pins ). 0: rasb#, casb#, ckeb, web# (normal operation). 1: rasb#, casb#, ckeb, web# are used to output test information 15:12 sel (select). this field is used for debug purposes only and should be left at zero for normal operation. 11 rsvd (reserved). write as 0. 10:0 gbadd (graphics base address). this field indicates the gr aphics memory base address, which is programmable on 512 kb boundaries. this field corresponds to address bits [29:19]. note that bc_dram_top must be set to a value lower than the graphics base address. gx_base+8418h-841bh mc_dr_add (r/w) reset value: 00000000h 31:10 rsvd (reserved). write as 0. 9:0 dradd (dirty ram address). this field is the address inde x that is used to access the dirty ram with the mc_dr_acc register. this field d oes not auto increment. gx_base+841ch-841fh mc_dr_acc (r/w) reset value: 0000000xh 31:2 rsvd (reserved). write as 0. 1 d (dirty bit). this bit is read/write accessible. 0 v (valid bit). this bit is read/write accessible. table 2-2. sc3200 memory controller registers (continued) bit description
22 amd geode? sc3200 processor data book architecture overview revision 5.1 2.1.2 fast-pci bus the gx1 module communicates with the core logic mod- ule via a fast-pci bus that c an work at up to 66 mhz. the fast-pci bus is internal for the sc3200 and is connected to the general configuration block (see section 4.0 on page 87 for details on the general configuration block). this bus supports seven bus masters. the requests (reqs) are fixed in priority. the seven bus masters in order of priority are: 1) vip 2) ide channel 0 3) ide channel 1 4) audio 5) usb 6) external req0# 7) external req1# 2.1.3 display the gx1 module generates display timing, and controls internal vsync and hsync signals of the video proces- sor module. the gx1 module interfaces with the video processor via a video data bus and a graphics data bus. video data. the gx1 module uses the core clock, divided by 2 or 4 (typically 100 - 133 mhz). it drives the video data using this clock. internal signals vid_val and vid_rdy are used as data-flow handshake signals between the gx1 module and the video processor. graphics data. the gx1 module uses the internal signal dclk, supplied by the pll of the video processor, to drive the 18-bit graphics-data bus of the video processor. each six bits of this bus define a different color. each of thes e 6-bit color definitions is expanded (by adding two zero lsb lines) to form an 8- bit bus, at the video processor. for more information about the gx1 module?s interface to the video processor, see the ?display controller? chapter in the amd geode? gx1 processor data book . 2.2 video processor module the video processor provides high resolution and graphics for a tft/dstn interface. the following subsections pro- vide a summary of how the video processor interfaces with the other modules of the sc3200. for detailed information about the video processor, se e section 7.0 "video proces- sor module" on page 327. 2.2.1 gx1 module interface the video processor is connected to the gx1 module in the following way: the video processor?s dotclk output signal is used as the gx1 module?s dclk input signal. the gx1 module?s pclk output signal is used as the gfxclk input signal of the video processor. 2.2.2 video input port the video input port (vip) within the video processor con- tains a standard interface that is typically connected to a media processor or tv encoder. the clock is supplied by the externally connected device; typically at 27 mhz. video input can be sent to the gx1 module?s video frame buffer (capture video mode) or can be used directly (direct video mode). 2.2.3 core logic module interface the video processor interfaces to the core logic module for accessing pci function configuration registers. 2.3 core logic module the core logic module is described in detail in section 6.0 "core logic module" on page 157. the core logic module is connected to the fast-pci bus. it uses signal ad28 as the idsel for all pci configuration functions except for usb which uses ad29. 2.3.1 other core logic module interfaces the following interfaces of the core logic module are implemented via external balls of the sc3200. each inter- face is listed below with a reference to the descriptions of the relevant balls. ide: see section 3.4.9 "ide interface signals" on page 75. ac97: see section 3.4.14 "ac97 audio interface signals" on page 80. pci: see section 3.4.6 "pci bus interface signals" on page 68. usb: see section 3.4.10 "u niversal serial bus (usb) interface signals" on page 76. the usb function uses signal ad29 as the idsel for pci configuration. lpc: see section 3.4.8 "low pin count (lpc) bus inter- face signals" on page 74.
amd geode? sc3200 processor data book 23 architecture overview revision 5.1 sub-isa: see section 3.4.7 "sub-isa interface signals" on page 73, section 6.2.5 "sub-isa bus interface" on page 163, and section 4.2 "multiplexing, interrupt selec- tion, and base address registers" on page 88 gpio: see section 3.4.16 "gpio interface signals" on page 82. more detailed information about each of these interfaces is provided in section 6.2 "module architecture" on page 158. super/io block interfaces: see section 4.2 "multi- plexing, interrupt selection, and base address regis- ters" on page 88, section 3.4.5 "access.bus interface signals" on page 67, section 3.4.13 "fast infrared (ir) port interface signals" on page 79, and section 3.4.12 "parallel port interface signals" on page 78. the core logic module interface to the gx1 module con- sists of seven miscellaneous connections, the pci bus interface signals, plus the display controller connections. note that the pc/at legacy signals nmi, wm_rst, and a20m are all virtual functions executed in smm (system management mode) by the bios. pserial is a one-way serial bus from the gx1 to the core logic module used to communicate power- management states and vsync information for vga emulation. irq13 is an input from the gx 1 module indicating that a floating point error was detected and that intr should be asserted. intr is the level output fr om the integrated 8259a pics and is asserted if an unmask ed interrupt r equest (irqn) is sampled active. smi# is a level-sensitive interrupt to the gx1 module that can be configured to assert on a number of different system events. after an smi# assertion, smm is entered and program execution begins at the base of the smm address space. once assert ed, smi# remains active until the smi source is cleared. susp# and suspa# are handshake signals for imple- menting cpu clock stop and clock throttling. cpu_rst resets the cpu and is asserted for approxi- mately 100 s after the negation of por#. pci bus interface signals. 2.4 super i/o module the superi/o (sio) module is a pc98 and acpi compliant sio that offers a single-cell solution to the most commonly used isa peripherals. the sio module incorporates: two serial ports, an infrared communication port that s upports fir, mir, hp-sir, sharp-ir, and consumer electronics-ir, a full ieee 1284 parallel port, two access.bus interface (acb) ports, sys- tem wakeup control (swc), and a real-time clock (rtc) that provides rtc timekeeping. 2.5 clock, timers, and reset logic in addition to the four main modules (i.e., gx1, core logic, video processor and sio) that make up the sc3200, the following blocks of logic have also been integrated into the sc3200: clock generators as described in section 4.5 "clock generators and plls" on page 99. configuration registers as described in section 4.2 "multiplexing, interrupt selection, and base address registers" on page 88. a watchdog timer as described in section 4.3 "watchdog" on page 95. a high-resolution timer as described in section 4.4 "high-resolution timer" on page 97. 2.5.1 reset logic this section provides a description of the reset flow of the sc3200. 2.5.1.1 power-on reset power-on reset is triggered by assertion of the por# sig- nal. upon power-on reset, the following things happen: strap balls are sampled. pll4, pll5, and pll6 are reset, disabling their output. when the por# signal is negated, the clocks lock and then each pll outputs its cloc k. pll6 is the last clock generator to output a clock. see section 4.5 "clock generators and plls" on page 99. certain watchdog and high-resolution timer register bits are cleared. 2.5.1.2 system reset system reset causes signal pcirst# to be issued, thus triggering a reset of all pci and lpc agents. a system reset is triggered by any of the following events: power-on, as indicated by por# signal assertion. a watchdog reset event (see section 4.3.2 "watchdog registers" on page 96). software initiated system reset.
24 amd geode? sc3200 processor data book architecture overview revision 5.1
amd geode? sc3200 processor data book 25 3 signal definitions revision 5.1 3.0 signal definitions this section defines the signals and describes the external interface of the sc3200. figure 2-1 shows the signals organized by their functional groups. where signals are multiplexed, the default signal name is listed first and is separated by a plus sign (+). a slash (/) in a signal name means that the function is always enabled and available (i.e., cycle multiplexed). figure 3-1. signal groups system por# x32i x27i md[63:0] ma[12:0] ba[1:0] cs[1:0]# rasa# casa# wea# dqm[7:0] ckea sdclk[3:0] sdclk_in sdclk_out access.bus ab1c+gpio20+doccs# ab1d+gpio1+iocs1# gpio12+ab2c gpio13+ab2d pcirst# ack#+tftde afd#/dstrb#+tftd2 busy/wait#+tftd3 err#+tftd4 init#+tftd5 pd[5:0]+tftd[11:6] pe+tftd14 slct+tftd15 slin#/astrb#+tftd16 stb#/write#+tftd17 parallel port/ ide_addr2+tftd4 ide_data15+tftd7 ide_ior0#+tftd10 ide_iow0#+tftd9 ide_cs0#+tftd5 ide_iordy0+tftd11 ide_dreq0+tftd8 ide_dack0#+tftd0 irq14+tftd1 ide/tft ide_cs1#+tftde ide_data12+tftd13 ide_data10 ide_data14+tftd17 ide_data13+tftd15 ide_data11+gpio41 ide_data9 ide_data8+gpio40 ide_data7+intd# ide_data6+irq9 ide_data5+clk27m ide_data4+fp_vdd_on ide_data3+tftd12 ide_data2+tftd14 ide_data1+tftd16 ide_data0+tftd6 ide_addr1+tftd2 ide_addr0+tftd3 ide_rst#+tftdck pd6+tftd1 pd7+tftd13 x32o x27o memory interface interface interface tft interface interface vpd[7:0] vpckin video port interface amd geode? sc3200 processor boot16+romcs# lpc_rom+pciclk1 tft_prsnt+sdata_out fpci_mon+pciclk0 did0+gnt0#, did1+gnt1# straps note: straps are not the default signal, shown with system signals fo r reader convenience. however, also listed in figure with the appropriate functional group.
26 amd geode? sc3200 processor data book signal definitions revision 5.1 figure 3-1. signal groups (continued) the remaining subsections of this chapter describe: section 3.1 "ball assignments": provides a ball assign- ment diagram and tables listing the signals sorted according to ball number and alphabetically by signal name. section 3.2 "strap options": several balls are read at power-up that set up the st ate of the sc3200. this section provides details regarding those balls. section 3.3 "multiplexing co nfiguration": lists multi- plexing options and their configurations. section 3.4 "signal descriptio ns": detailed descriptions of each signal according to functional group. serial ports sin1 sout1+clksel1 gpio7+rts2#+ide_dack1#+sdtest0 gpio8+cts2#+ide_dreq1+sdtest4 gpio6+dtr2#/bout2+ide_ior1#+sdtest5 ac97 audio bit_clk sdata_out+tft_prsnt sdata_in sdata_in2 sync+clksel3 ac97_clk ac97_rst# gpio16+pc_beep power clk32 gpwio[2:0] led# onctl# pwrbtn# pwrcnt[1:2] thrm# tck tdi tdo tms trst# jtag test1+pll6b test0+pll2b gxclk+fp_vdd_on+test3 test2+pll5b gtest test and tdp, tdn gpio11+ri2#+irq15 gpio18+dtr1#/bout1 gpio9+dcd2#+ide_iow1#+sdtest2 gpio10+dsr2#+ide_iordy1+sdtest1 ir port irrx1+sin3 irtx+sout3 pciclk inta#, intb# frame# lock# perr# serr# req[1:0]# gnt0#+did0 power_en over_cur# dpos_port1 dneg_port1 dpos_port2 dneg_port2 dpos_port3 dneg_port3 usb a[23:0]/ad[23:0] d[11:8]/c/be[3:0]# bhe#/devsel# gpio1+iocs1+tftd12 romcs#/boot16 gpio20+doccs#+tftd0 rd#+clksel0 wr# sub-isa/pci bus gpio14+docr#+ior# gpio15+docw#+iow# sout2+clksel2 d[7:0]/ad[31:24] d12/par d13/trdy# d14/irdy# d15/stop# sin2+sdtest3 gpio0+trde# gpio19+intc#+iochrdy gpio17+tftdck+iocs0# gpio32+lad0 gpio33+lad1 gpio34+lad2 gpio35+lad3 gpio36+ldrq# gpio37+lframe# gpio38+irrx2+lpcpd gpio39+serirq gpio/lpc bus pciclk0+fpci_mon pciclk1+lpc_rom gnt1#+did1 interface (uarts)/ide interface interface interface management interface interface measurement interface interface interface amd geode? sc3200 processor
amd geode? sc3200 processor data book 27 signal definitions revision 5.1 3.1 ball assignments the sc3200 is highly configurable as illustrated in figure 3-1 on page 25. strap options and register programming are used to set various modes of operation and specific signals on specific balls. this section describes which sig- nals are available on which balls and provides configuration information: figure 3-2 on page 28 and figure 3-3 on page 42: illus- trations of ebga and tepbga ball assignments. table 3-2 on page 29 and table 3-4 on page 43: lists signals according to ball number. power rail, signal type, buffer type and, where relevant, pull-up or pull- down resistors are indicated for each ball in this table. for multiplexed balls, the necessary configuration for each signal is listed as well. table 3-3 on page 38 and table 3-5 on page 54: quick reference signal list sorted alphabetically - listing all signal names and ball numbers.the tables in this chapter use several common abbreviations. table 3-1 lists the mnemonics and their meanings notes: 1) for each gpio signal, there is an optional pull-up resistor on the relevant ball. after system reset, the pull-up is present. this pull-up resistor can be disabled via registers in the core logic module. the configuration is without regard to the selected ball function (except for gpio12, gpio13, and gpio16). alternate functions for gpio12, gpio13, and gpio16 control pull-up resistors. for more information, see section 6.4.1 "bridge, gpio, and lpc registers - function 0" on page 206. 2) configuration settings listed in this table are with regard to the pin multiplexing register (pmr). see section 4.2 "multiplexing, interrupt selection, and base address registers" on page 88 for a detailed description of this register. table 3-1. signal definitions legend mnemonic definition a analog av ss ground ball: analog av cc power ball: analog gcb general configuration block registers. refer to section 4.0 "general configura- tion block" on page 87. location of the general configuration block cannot be determined by software. see the amd geode? sc3200 specifi- cation update document. i input ball i/o bidirectional ball mcr[x] miscellaneous configuration register bit x: a register, located in the gcb. refer to section 4.1 "configuration block addresses" on page 87 for further details. o output ball od open-drain pd pull-down pmr[x] pin multiplexing register bit x: a regis- ter, located in the gc b, used to config- ure balls with multiple functions. refer to section 4.1 "configuration block addresses" on page 87 for further details. pu pull-up ts tri-state v core power ball: 1.2v v io power ball: 3.3v v ss ground ball # the # symbol in a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. otherwise, the signal is asserted when at a high voltage level. / a / in a signal name indicates both func- tions are always enabled (i.e., cycle mul- tiplexed). + a + in signal name indicates the function is available on the bal l, but that either strapping options or register program- ming is required to select the desired function.
28 amd geode? sc3200 processor data book signal definitions revision 5.1 figure 3-2. 432-ebga ball assignment diagram s s s s s s s s 12345678910111213141516171819202122232425262728293031 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al note: signal names have been abbreviated in this figure due to space constraints. v ss v io ad29 ad26 ad22 ad19 ad16 cbe3# serr# cbe1# ad14 ad12 cbe0# ad5 ad3 ad4 ad0 ad2 idat13 idat10 idat8 irst# idat5 idat1 iordy0 iad0 ics0# gp18 x27i v io v ss 12345678910111213141516171819202122232425262728293031 v io v ss ad31 ad27 dvsl# v io v ss trdy# perr# ad15 v io v ss ad9 ad7 v ss v io v ss idat15 idat12 v io v ss idat7 idat4 idat0 v io v ss sout1 pwre test2 v ss v io rq0# ad30 v io ad28 ad24 ad21 ad17 irdy# lock# par ad13 ad11 ad10 ad8 ad6 ics1# iad2 idat14 idat11 idat9 iior0# idat6 idat3 idrq0 idck0# iad1 ovcr# test1 v io x32i v pll3 prst# gnt1# pck0 gnt0# ad25 ad20 ad18 cbe2# stp# v ss v core v ss v core v ss v core ad1 v core v ss v core v ss v core v ss idat2 iiow0# irq14 sin1 x27o test0 x32o v bat led# frm# pclk req1# pck1 av ssp3 pbtn# octl# gpw0 ior# v ss rd# ad23 thrm# v sb v ss pcnt1 wr# v io iow# rmcs# gpw1 gpw2 v io pcnt2 trde# gp1 gp20 gp19 v sbl ck32 gp11 sdin2 hsyn vsyn irtx gp17 irrx1 por# md0 md1 nc v ss v core v ss v ss md2 md3 md4 v ss v ss v io v core v core md5 v ss md6 v io v io nc v ss v ss md7 v io dqm0 v io nc v ss v core nc nc v ss v ss v core wea# casa# rasa# v ss cs0# ba0 ba1 v pll2 v ss av ssp2 v core bsy v io pe slct pd7 v ss ack# v core pd4 pd5 pd6 v ss slin# pd3 pd2 v core pd1 v io init# v ss pd0 v ss err# v core stb# afd# nc v ss nc nc v io v ss nc nc nc nc nc v io inta# d+p3 intb# v ss d-p3 av ccusb av ssusb d-p2 d-p1 gp9 v core ma10 v ss ma0 dqm4 ma2 v core ma1 v core md33 v ss md32 v ss md36 md35 md34 v core md39 md38 md37 v ss md46 v io md47 v core md44 v ss md45 v ss md41 md42 md43 ckea sdck0 dqm5 md40 ma6 ma7 ma8 ma9 ma3 ma4 v io ma5 md14 md15 v ss dqm1 ma11 md9 md8 md13 d+p2 d+p1 gp6 gp7 tdp tdo vpcki vpd4 vpd0 v ss v core v ss v core v ss v core sdck1 v core v ss v core v ss v core v ss md28 md55 md51 md48 md23 sdcko ma12 md11 md10 gp10 gp8 v io sin2 tms vpd7 vpd6 vpd2 gp38 gp35 gp32 gp12 ab1c acck acrt# sdck 3 md56 md58 md61 dqm7 dqm3 md25 md29 md54 md50 dqm6 md22 md19 v io sdcki md12 v io v ss sout2 trst# tdi v io v ss vpd1 gp37 gp34 v io v ss sdato sdati v ss v io v ss md59 md62 v io v ss md26 md30 md53 v io v ss md21 md18 cs1# v ss v io v ss v io tdn tck gtst vpd5 vpd3 gp39 gp36 gp33 gp13 ab1d sync bitck gp16 gxc k md57 md60 md63 sdck2 md24 md27 md31 md52 md49 dqm2 md20 md17 md16 v io v ss amd geode? s s s = gnd ball = pwr ball = strap option ball = multiplexed ball (top view) sc3200 processor
amd geode? sc3200 processor data book 29 signal definitions revision 5.1 table 3-2. 432-ebga ball assignment - sorted by ball number ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration a1 v ss gnd --- --- --- a2 v io pwr --- --- --- a3 ad29 i/o in pci , o pci v io cycle multiplexed d5 i/o in pci , o pci a4 ad26 i/o in pci , o pci v io cycle multiplexed d2 i/o in pci , o pci a5 ad22 i/o in pci , o pci v io cycle multiplexed a22 o o pci a6 ad19 i/o in pci , o pci v io cycle multiplexed a19 o o pci a7 ad16 i/o in pci , o pci v io cycle multiplexed a16 o o pci a8 c/be3# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d11 i/o (pu 22.5 ) in pci , o pci a9 serr# i/o (pu 22.5 ) in pci , od pci v io --- a10 c/be1# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d9 i/o (pu 22.5 ) in pci , o pci a11 ad14 i/o in pci , o pci v io cycle multiplexed a14 o o pci a12 ad12 i/o in pci , o pci v io cycle multiplexed a12 o o pci a13 c/be0# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d8 i/o (pu 22.5 ) in pci , o pci a14 ad5 i/o in pci , o pci v io cycle multiplexed a5 o o pci a15 ad3 i/o in pci , o pci v io cycle multiplexed a3 o o pci a16 ad4 i/o in pci , o pci v io cycle multiplexed a4 o o pci a17 ad0 i/o in pci , o pci v io cycle multiplexed a0 o o pci a18 ad2 i/o in pci , o pci v io cycle multiplexed a2 o o pci a19 ide_data13 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd15 o o 1/4 pmr[24] = 1 a20 ide_data10 i/o in ts1 , ts 1/4 v io pmr[24] = 0 a21 ide_data8 i/o in ts1 , ts 1/4 v io pmr[24] = 0 gpio40 i/o in ts1 , o 1/4 pmr[24] = 1 a22 ide_rst# o o 1/4 v io pmr[24] = 0 tftdck o o 1/4 pmr[24] = 1 a23 ide_data5 i/o in ts1 , ts 1/4 v io pmr[24] = 0 clk27m o o 1/4 pmr[24] = 1 a24 ide_data1 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd16 o o 1/4 pmr[24] = 1 a25 ide_iordy0 i in ts1 v io pmr[24] = 0 tftd11 o o 1/4 pmr[24] = 1 a26 ide_addr0 o o 1/4 v io pmr[24] = 0 tftd3 o o 1/4 pmr[24] = 1 a27 ide_cs0# o o 1/4 v io pmr[24] = 0 tftd5 o o 1/4 pmr[24] = 1 a28 gpio18 i/o (pu 22.5 ) in ts , o 8/ 8 v io pmr[16] = 0 dtr1#/bout1 o (pu 22.5 ) o 8/8 pmr[16] =1 a29 x27i i wire v io --- a30 v io pwr --- --- --- a31 v ss gnd --- --- --- b1 v io pwr --- --- --- b2 v ss gnd --- --- --- b3 ad31 i/o in pci , o pci v io cycle multiplexed d7 i/o in pci , o pci b4 ad27 i/o in pci , o pci v io cycle multiplexed d3 i/o in pci , o pci b5 devsel# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed bhe# o o pci b6 v io pwr --- --- --- b7 v ss gnd --- --- --- b8 trdy# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d13 i/o (pu 22.5 ) in pci , o pci ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration
30 amd geode? sc3200 processor data book signal definitions revision 5.1 b9 perr# i/o (pu 22.5 ) in pci , o pci v io --- b10 ad15 i/o in pci , o pci v io cycle multiplexed a15 o o pci b11 v io pwr --- --- --- b12 v ss gnd --- --- --- b13 ad9 i/o in pci , o pci v io cycle multiplexed a9 o o pci b14 ad7 i/o in pci , o pci v io cycle multiplexed a7 o o pci b15 v ss gnd --- --- --- b16 v io pwr --- --- --- b17 v ss gnd --- --- --- b18 ide_data15 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd7 o o 1/4 pmr[24] = 1 b19 ide_data12 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd13 o o 1/4 pmr[24] = 1 b20 v io pwr --- --- --- b21 v ss gnd --- --- --- b22 ide_data7 i/o in ts1 , ts 1/4 v io pmr[24] = 0 intd# i in ts pmr[24] = 1 b23 ide_data4 i/o in ts1 , ts 1/4 v io pmr[24] = 0 fp_vdd_on o o 1/4 pmr[24] = 1 b24 ide_data0 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd6 o o 1/4 pmr[24] = 1 b25 v io pwr --- --- --- b26 v ss gnd --- --- --- b27 sout1 o o 8/8 v io --- clksel1 i (pd 100 ) in strp strap (see table 3-6 on page 58.) b28 power_en o o 1/4 v io --- b29 test2 o o 2/5 v io pmr[29] = 1 pll5b i/o in t , ts 2/5 pmr[29] = 0 b30 v ss gnd --- --- --- b31 v io pwr --- --- --- c1 req0# i (pu 22.5 ) inpci v io --- c2 ad30 i/o in pci , o pci v io cycle multiplexed d6 i/o in pci , o pci c3 v io pwr --- --- --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration c4 ad28 i/o in pci , o pci v io cycle multiplexed d4 i/o in pci , o pci c5 ad24 i/o in pci , o pci v io cycle multiplexed d0 i/o in pci , o pci c6 ad21 i/o in pci , o pci v io cycle multiplexed a21 o o pci c7 ad17 i/o in pci , o pci v io cycle multiplexed a17 o o pci c8 irdy# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d14 i/o (pu 22.5 ) in pci , o pci c9 lock# i/o (pu 22.5 ) in pci , o pci v io --- c10 par i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d12 i/o (pu 22.5 ) in pci , o pci c11 ad13 i/o in pci , o pci v io cycle multiplexed a13 o o pci c12 ad11 i/o in pci , o pci v io cycle multiplexed a11 o o pci c13 ad10 i/o in pci , o pci v io cycle multiplexed a10 o o pci c14 ad8 i/o in pci , o pci v io cycle multiplexed a8 o o pci c15 ad6 i/o in pci , o pci v io cycle multiplexed a6 o o pci c16 ide_cs1# o o 1/4 v io pmr[24] = 0 tftde o o 1/4 pmr[24] = 1 c17 ide_addr2 o o 1/4 v io pmr[24] = 0 tftd4 o o 1/4 pmr[24] = 1 c18 ide_data14 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd17 o o 1/4 pmr[24] = 1 c19 ide_data11 i/o in ts1 , ts 1/4 v io pmr[24] = 0 gpio41 i/o in ts1 , o 1/4 pmr[24] = 1 c20 ide_data9 i/o in ts1 , ts 1/4 v io pmr[24] = 0 ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration table 3-2. 432-ebga ball assignment - sorted by ball number (continued)
amd geode? sc3200 processor data book 31 signal definitions revision 5.1 c21 ide_ior0# o o 1/4 v io pmr[24] = 0 tftd10 o o 1/4 pmr[24] = 1 c22 ide_data6 i/o in ts1 , ts 1/4 v io pmr[24] = 0 irq9 i in ts1 pmr[24] = 1 c23 ide_data3 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd12 o o 1/4 pmr[24] = 1 c24 ide_dreq0 i in ts1 v io pmr[24] = 0 tftd8 o o 1/4 pmr[24] = 1 c25 ide_dack0# o o 1/4 v io pmr[24] = 0 tftd0 o o 1/4 pmr[24] = 1 c26 ide_addr1 o o 1/4 v io pmr[24] = 0 tftd2 o o 1/4 pmr[24] = 1 c27 over_cur# i in ts v io --- c28 test1 o o 2/5 v io pmr[29] = 1 pll6b i/o in ts , ts 2/5 pmr[29] = 0 c29 v io pwr --- --- --- c30 x32i i wire v bat --- c31 v pll3 pwr --- --- --- d1 pcirst# o o pci v io --- d2 gnt1# o o pci v io --- did1 i (pd 100 ) in strp strap (see table 3-6 on page 58.) d3 pciclk0 o o pci v io --- fpci_mon i (pd 100 ) in strp strap (see table 3-6 on page 58.) d4 gnt0# o o pci v io --- did0 i (pd 100 ) in strp strap (see table 3-6 on page 58.) d5 ad25 i/o in pci , o pci v io cycle multiplexed d1 i/o in pci , o pci d6 ad20 i/o in pci , o pci v io cycle multiplexed a20 o o pci d7 ad18 i/o in pci , o pci v io cycle multiplexed a18 o o pci d8 c/be2# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d10 i/o (pu 22.5 ) in pci , o pci d9 stop# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d15 i/o (pu 22.5 ) in pci , o pci d10 v ss gnd --- --- --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration d11 v core pwr --- --- --- d12 v ss gnd --- --- --- d13 v core pwr --- --- --- d14 v ss gnd --- --- --- d15 v core pwr --- --- --- d16 ad1 i/o in pci , o pci v io cycle multiplexed a1 o o pci d17 v core pwr --- --- --- d18 v ss gnd --- --- --- d19 v core pwr --- --- --- d20 v ss gnd --- --- --- d21 v core pwr --- --- --- d22 v ss gnd --- --- --- d23 ide_data2 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd14 o o 1/4 pmr[24] = 1 d24 ide_iow0# o o 1/4 v io pmr[24] = 0 tftd9 o o 1/4 pmr[24] = 1 d25 irq14 i in ts1 v io pmr[24] = 0 tftd1 o o 1/4 pmr[24] = 1 d26 sin1 i in ts v io --- d27 x27o o wire v io --- d28 test0 o o 2/5 v io pmr[29] = 1 pll2b i/o in t , ts 2/5 pmr[29] = 0 d29 x32o o wire v bat --- d30 v bat pwr --- --- --- d31 led# o od 14 v sb --- e1 frame# i/o (pu 22.5 ) in pci , o pci v io --- e2 pciclk i in t v io --- e3 req1# i (pu 22.5 ) in pci v io --- e4 pciclk1 o o pci v io --- lpc_rom i (pd 100) in strp strap (see table 3-6 on page 58.) e28 av sspll3 gnd --- --- --- e29 pwrbtn# i (pu 100) in btn v sb --- e30 3, 4 onctl# o od 14 v sb --- e31 gpwio0 i/o (pu 100 ) in ts , ts 2/14 v sb --- f1 ior# o o 3/5 v io pmr[21] = 0 and pmr[2] = 0 docr# o o 3/5 pmr[21] = 0 and pmr[2] = 1 gpio14 i/o (pu 22.5 ) in ts , o 3/ 5 pmr[21] = 1 and pmr[2] = 1 f2 v ss gnd --- --- --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration table 3-2. 432-ebga ball assignment - sorted by ball number (continued)
32 amd geode? sc3200 processor data book signal definitions revision 5.1 f3 rd# o o 3/5 v io --- clksel0 i (pd 100 ) in strp strap (see table 3-6 on page 58.) f4 ad23 i/o in pci , o pci v io cycle multiplexed a23 o o pci f28 thrm# i in ts v sb --- f29 v sb pwr --- --- --- f30 v ss gnd --- --- --- f31 3, 4 pwrcnt1 o od 14 v sb --- g1 wr# o o 3/5 v io g2 v io pwr --- --- --- g3 iow# o o 3/5 v io pmr[21] = 0 and pmr[2] = 0 docw# o o 3/5 pmr[21] = 0 and pmr[2] = 1 gpio15 i/o (pu 22.5 ) in ts , o 3/ 5 pmr[21] = 1 and pmr[2] = 1 g4 romcs# o o 3/5 v io --- boot16 i (pd 100 ) in strp v io strap (see table 3-6 on page 58.) g28 gpwio1 i/o (pu 100 ) in ts , ts 2/ 14 v sb --- g29 gpwio2 i/o (pu 100 ) in ts , ts 2/14 v sb --- g30 v io pwr --- --- --- g31 3, 4 pwrcnt2 o od 14 v sb --- h1 trde# o o 3/5 v io pmr[12] = 0 gpio0 i/o (pu 22.5 ) in ts , o 3/ 5 v io pmr[12] = 1 h2 gpio1 i/o (pu 22.5 ) in t , o 3/5 v io pmr[23] 2 = 0 and pmr[13] = 0 iocs1# o (pu 22.5 ) o 3/5 v io pmr[23] 2 = 0 and pmr[13] = 1 tftd12 o (pu 22.5 ) o 1/4 v io pmr[23] 2 = 1 h3 gpio20 i/o (pu 22.5 ) in t , o 3/5 v io pmr[23] 2 = 0 and pmr[7] = 0 doccs# o (pu 22.5 ) o 3/5 pmr[23] 2 = 0 and pmr[7] = 1 tftd0 o (pu 22.5 ) o 1/4 pmr[23] 2 = 1 h4 gpio19 i/o (pu 22.5 ) in ts , o 3/ 5 v io pmr[9] = 0 and pmr[4] = 0 intc# i (pu 22.5 ) in ts pmr[9] = 0 and pmr[4] = 1 iochrdy i (pu 22.5 ) in ts1 pmr[9] = 1 and pmr[4] = 1 h28 v sbl pwr --- --- --- h29 clk32 o o 2/5 v sb --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration h30 gpio11 i/o (pu 22.5 ) in ts , o 8/ 8 v io pmr[18] = 0 and pmr[8] = 0 ri2# i (pu 22.5 ) in ts pmr[18] = 1 and pmr[8] = 0 irq15 i (pu 22.5 ) in ts1 pmr[18] = 0 and pmr[8] = 1 h31 sdata_in2 i in ts v sb f3bar0+memory offset 08h[21] = 1 j1 hsync o o 1/4 v io --- j2 vsync o o 1/4 v io --- j3 irtx o o 8/8 v io pmr[6] = 0 sout3 o o 8/8 pmr[6] = 1 j4 gpio17 i/o (pu 22.5 ) in ts , o 3/ 5 v io pmr[23] 2 = 0 and pmr[5] = 0 iocs0# o (pu 22.5 ) o 3/5 pmr[23] 2 = 0 and pmr[5] = 1 tftdck o (pu 22.5 ) o 1/4 pmr[23] 2 = 1 j28 irrx1 i in ts v sb pmr[6] = 0 sin3 i in ts v io pmr[6] =1 j29 por# i in ts v io --- j30 3 md0 i/o in t , ts 2/5 v io --- j31 3 md1 i/o in t , ts 2/5 v io --- k1 nc --- --- --- --- k2 v ss gnd --- --- --- k3 v core pwr --- --- --- k4 v ss gnd --- --- --- k28 v ss gnd --- --- --- k29 3 md2 i/o in t , ts 2/5 v io --- k30 3 md3 i/o in t , ts 2/5 v io --- k31 3 md4 i/o in t , ts 2/5 v io --- l1 v ss gnd --- --- --- l2 v ss gnd --- --- --- l3 v io pwr --- --- --- l4 v core pwr --- --- --- l28 v core pwr --- --- --- l29 3 md5 i/o in t , ts 2/5 v io --- l30 v ss gnd --- --- --- l31 3 md6 i/o in t , ts 2/5 v io --- m1 v io pwr --- --- --- m2 v io pwr --- --- --- m3 nc --- --- --- --- m4 v ss gnd --- --- --- m28 v ss gnd --- --- --- m29 3 md7 i/o in t , ts 2/5 v io --- m30 v io pwr --- --- --- m31 dqm0 o o 2/5 v io --- n1 v io pwr --- --- --- n2 nc --- --- --- --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration table 3-2. 432-ebga ball assignment - sorted by ball number (continued)
amd geode? sc3200 processor data book 33 signal definitions revision 5.1 n3 v ss gnd --- --- --- n4 v core pwr --- --- --- n28 v core pwr --- --- --- n29 wea# o o 2/5 v io --- n30 casa# o o 2/5 v io --- n31 rasa# o o 2/5 v io --- p1 nc --- --- --- --- p2 nc --- --- --- --- p3 v ss gnd --- --- --- p4 v ss gnd --- --- --- p28 v ss gnd --- --- --- p29 cs0# o o 2/5 v io --- p30 ba0 o o 2/5 v io --- p31 ba1 o o 2/5 v io --- r1 v pll2 pwr --- --- --- r2 v ss gnd --- --- --- r3 av sspll2 gnd --- --- --- r4 v core pwr --- --- --- r28 v core pwr --- --- --- r29 ma10 o o 2/5 v io --- r30 v ss gnd --- --- --- r31 ma0 o o 2/5 v io --- t1 3, 4 busy/wait# i in t v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd3 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_c/be1# o o 1/4 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) t2 v io pwr --- --- --- t3 3, 4 pe i (pu 22.5 pd 22.5 ) in t v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) (pu/pd under soft- ware control.) tftd14 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_c/be2# o o 1/4 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) t4 3, 4 slct i in t v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd15 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_c/be3# o o 1/4 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) t28 dqm4 o o 2/5 v io --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration t29 ma2 o o 2/5 v io --- t30 v core pwr --- --- --- t31 ma1 o o 2/5 v io --- u1 3, 4 pd7 i/o in t , o 14/ 14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd13 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad7 o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) u2 v ss gnd --- --- --- u3 3, 4 ack# i in t v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftde o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) fpciclk o o 1/4 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) u4 v core pwr --- --- --- u28 v core pwr --- --- --- u29 3 md33 i/o in t , ts 2/5 v io --- u30 v ss gnd --- --- --- u31 3 md32 i/o in t , ts 2/5 v io --- v1 3, 4 pd4 i/o in t , o 14/ 14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd10 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad4 o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) v2 3, 4 pd5 i/o in t , o 14/ 14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd11 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad5 o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) v3 3, 4 pd6 i/o in t , o 14/ 14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd1 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0 f_ad6 o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) v4 v ss gnd --- --- --- v28 v ss gnd --- --- --- v29 3 md36 i/o in t , ts 2/5 v io --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration table 3-2. 432-ebga ball assignment - sorted by ball number (continued)
34 amd geode? sc3200 processor data book signal definitions revision 5.1 v30 3 md35 i/o in t , ts 2/5 v io --- v31 3 md34 i/o in t , ts 2/5 v io --- w1 3, 4 slin#/astrb# o o 14/14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd16 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_irdy# o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) w2 3, 4 pd3 i/o in t , o 14/ 14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd9 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad3 o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) w3 3, 4 pd2 i/o in t , o 14/ 14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd8 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad2 o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) w4 v core pwr --- --- --- w28 v core pwr --- --- --- w29 3 md39 i/o in t , ts 2/5 v io --- w30 3 md38 i/o in t , ts 2/5 v io --- w31 3 md37 i/o in t , ts 2/5 v io --- y1 3, 4 pd1 i/o in t , o 14/ 14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd7 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad1 o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) y2 v io pwr --- --- --- y3 3, 4 init# o o 14/14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd5 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) smi_o o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) y4 v ss gnd --- --- --- y28 v ss gnd --- --- --- y29 3 md46 i/o in t , ts 2/5 v io --- y30 v io pwr --- --- y31 3 md47 i/o in t , ts 2/5 v io --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration aa1 3, 4 pd0 i/o in t , o 14/ 14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd6 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad0 o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) aa2 v ss gnd --- --- --- aa3 3, 4 err# i in t , o 1/4 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd4 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_c/be0# o o 1/4 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) aa4 v core pwr --- --- --- aa28 v core pwr --- --- --- aa29 3 md44 i/o in t , ts 2/5 v io --- aa30 v ss gnd --- --- --- aa31 3 md45 i/o in t , ts 2/5 v io --- ab1 3, 4 stb#/write# o o 14/14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd17 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_frame# o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) ab2 3, 4 afd#/dstrb# o o 14/14 v io pmr[23] 2 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd2 o o 1/4 pmr[23] 2 = 1 and (pmr[27] = 0 and fpci_mon = 0) intr_o o o 14/14 pmr[23] 2 = 0 and (pmr[27] = 1 or fpci_mon = 1) ab3 nc --- --- --- --- ab4 v ss gnd --- --- --- ab28 v ss gnd --- --- --- ab29 3 md41 i/o in t , ts 2/5 v io --- ab30 3 md42 i/o in t , ts 2/5 v io --- ab31 3 md43 i/o in t , ts 2/5 v io --- ac1 nc --- --- --- --- ac2 nc --- --- --- --- ac3 v io pwr --- --- --- ac4 v ss gnd --- --- --- ac28 ckea o o 2/5 v io --- ac29 sdclk0 o o 2/5 v io --- ac30 dqm5 o o 2/5 v io --- ac31 3 md40 i/o in t , ts 2/5 v io --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration table 3-2. 432-ebga ball assignment - sorted by ball number (continued)
amd geode? sc3200 processor data book 35 signal definitions revision 5.1 ad1 nc --- --- --- --- ad2 nc --- --- --- --- ad3 nc --- --- --- --- ad4 nc --- --- --- --- ad28 ma6 o o 2/5 v io --- ad29 ma7 o o 2/5 v io --- ad30 ma8 o o 2/5 v io --- ad31 ma9 o o 2/5 v io --- ae1 nc --- --- --- --- ae2 v io pwr --- --- --- ae3 inta# i (pu 22.5 ) in pci v io --- ae4 3 dpos_port3 i/o in usb , o usb av c- cusb --- ae28 ma3 o o 2/5 v io --- ae29 ma4 o o 2/5 v io --- ae30 v io pwr --- --- --- ae31 ma5 o o 2/5 v io --- af1 intb# i (pu 22.5 ) in pci v io --- af2 v ss gnd --- --- --- af3 3 dneg_port3 i/o in usb , o usb av c- cusb --- af4 av ccusb pwr --- --- --- af28 3 md14 i/o in t , ts 2/5 v io --- af29 3 md15 i/o in t , ts 2/5 v io --- af30 v ss gnd --- --- --- af31 dqm1 o o 2/5 v io --- ag1 av ssusb gnd --- --- --- ag2 3 dneg_port2 i/o in usb , o usb av c- cusb --- ag3 3 dneg_port1 i/o in usb , o usb av c- cusb --- ag4 gpio9 i/o (pu 22.5 ) in ts , o 1/ 4 v io pmr[18] = 0 and pmr[8] = 0 dcd2# i (pu 22.5 ) in ts pmr[18] = 1 and pmr[8] = 0 ide_iow1# o (pu 22.5 ) o 1/4 pmr[18] = 0 and pmr[8] = 1 sdtest2 o (pu 22.5 ) o 2/5 pmr[18] = 1 and pmr[8] = 1 ag28 ma11 o o 2/5 v io --- ag29 3 md9 i/o in t , ts 2/5 v io --- ag30 3 md8 i/o in t , ts 2/5 v io --- ag31 3 md13 i/o in t , ts 2/5 v io --- ah1 3 dpos_port2 i/o in usb , o usb av c- cusb --- ah2 3 dpos_port1 i/o in usb , o usb av c- cusb --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration ah3 gpio6 i/o (pu 22.5 ) in ts , o 1/ 4 v io pmr[18] = 0 and pmr[8] = 0 dtr2#/bout2 o (pu 22.5 ) o 1/4 pmr[18] = 1 and pmr[8] = 0 ide_ior1# o (pu 22.5 ) o 1/4 pmr[18] = 0 and pmr[8] = 1 sdtest5 o (pu 22.5 ) o 2/5 pmr[18] = 1 and pmr[8] = 1 ah4 gpio7 i/o (pu 22.5 ) in ts , o 1/ 4 v io pmr[17] = 0 and pmr[8] = 0 rts2# o (pu 22.5 ) o 1/4 pmr[17] = 1 and pmr[8] = 0 ide_dack1# o (pu 22.5 ) o 1/4 pmr[17] = 0 and pmr[8] = 1 sdtest0 o (pu 22.5 ) o 2/5 pmr[17] = 1 and pmr[8] = 1 ah5 tdp i/o diode --- --- ah6 tdo o o pci v io --- ah7 vpckin i in t v io --- ah8 vpd4 i in t v io --- ah9 vpd0 i in t v io --- ah10 v ss gnd --- --- --- ah11 v core pwr --- --- --- ah12 v ss gnd --- --- --- ah13 v core pwr --- --- --- ah14 v ss gnd --- --- --- ah15 v core pwr --- --- --- ah16 sdclk1 o o 2/5 v io --- ah17 v core pwr --- --- --- ah18 v ss gnd --- --- --- ah19 v core pwr --- --- --- ah20 v ss gnd --- --- --- ah21 v core pwr --- --- --- ah22 v ss gnd --- --- --- ah23 3 md28 i/o in t , ts 2/5 v io --- ah24 3 md55 i/o in t , ts 2/5 v io --- ah25 3 md51 i/o in t , ts 2/5 v io --- ah26 3 md48 i/o in t , ts 2/5 v io --- ah27 3 md23 i/o in t , ts 2/5 v io --- ah28 sdclk_out o o 2/5 v io --- ah29 ma12 o o 2/5 v io --- ah30 3 md11 i/o in t , ts 2/5 v io --- ah31 3 md10 i/o in t , ts 2/5 v io --- aj1 gpio10 i/o (pu 22.5 ) in ts , o 8/ 8 v io pmr[18] = 0 and pmr[8] = 0 dsr2# i (pu 22.5 ) in ts pmr[18] = 1 and pmr[8] = 0 ide_iordy1 i (pu 22.5 ) in ts1 pmr[18] = 0 and pmr[8] = 1 sdtest1 o (pu 22.5 ) o 2/5 pmr[18] = 1 and pmr[8] = 1 ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration table 3-2. 432-ebga ball assignment - sorted by ball number (continued)
36 amd geode? sc3200 processor data book signal definitions revision 5.1 aj2 gpio8 i/o (pu 22.5 ) in ts , o 8/ 8 v io pmr[17] = 0 and pmr[8] = 0 cts2# i (pu 22.5 ) in ts pmr[17] = 1 and pmr[8] = 0 ide_dreq1 i (pu 22.5 ) in ts1 pmr[17] = 0 and pmr[8] = 1 sdtest4 o (pu 22.5 ) o 2/5 pmr[17] = 1 and pmr[8] = 1 aj3 v io pwr --- --- --- aj4 sin2 i in ts v io pmr[28] = 0 sdtest3 o o 2/5 pmr[28] = 1 aj5 tms i (pu 22.5 ) in pci v io --- aj6 vpd7 i in t v io --- aj7 vpd6 i in t v io --- aj8 vpd2 i in t v io --- aj9 gpio38/irrx2 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 5 = 0 and pmr[22] 5 = 0. the irrx2 input is connected to the input path of gpio38. there is no logic required to enable irrx2, just a simple connec- tion. hence, when gpio38 is the selected function, irrx2 is also selected. lpcpd# o o pci pmr[14] 5 = 1 and pmr[22] 5 = 1 aj10 gpio35 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 5 = 0 and pmr[22] 5 = 0 lad3 i/o (pu 22.5 ) in pci , o pci pmr[14] 5 = 1 and pmr[22] 5 = 1 aj11 gpio32 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 5 = 0 and pmr[22] 5 = 0 lad0 i/o (pu 22.5 ) in pci , o pci pmr[14] 5 = 1 and pmr[22] 5 = 1 aj12 gpio12 i/o (pu 22.5 ) in ab , o 8/ 8 v io pmr[19] = 0 ab2c i/o (pu 22.5 ) in ab , od 8 pmr[19] = 1 aj13 ab1c i/o (pu 22.5 ) in ab , od 8 v io pmr[23] 2 = 0 gpio20 i/o (pu 22.5 ) in t , o 3/5 pmr[23] 2 = 1 and pmr[7] = 0 doccs# o o3/5 pmr[23] 2 = 1 and pmr[7] = 1 aj14 ac97_clk o o 2/5 v io pmr[25] = 1 aj15 ac97_rst# o o 2/5 v io fpci_mon = 0 f_stop# o o 2/5 fpci_mon = 1 aj16 sdclk3 o o 2/5 v io --- aj17 3 md56 i/o in t , ts 2/5 v io --- aj18 3 md58 i/o in t , ts 2/5 v io --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration aj19 3 md61 i/o in t , ts 2/5 v io --- aj20 dqm7 o o 2/5 v io --- aj21 dqm3 o o 2/5 v io --- aj22 3 md25 i/o in t , ts 2/5 v io --- aj23 3 md29 i/o in t , ts 2/5 v io --- aj24 3 md54 i/o in t , ts 2/5 v io --- aj25 3 md50 i/o in t , ts 2/5 v io --- aj26 dqm6 o o 2/5 v io --- aj27 3 md22 i/o in t , ts 2/5 v io --- aj28 3 md19 i/o in t , ts 2/5 v io --- aj29 v io pwr --- --- --- aj30 sdclk_in i in t v io --- aj31 3 md12 i/o in t , ts 2/5 v io --- ak1 v io pwr --- --- --- ak2 v ss gnd --- --- --- ak3 sout2 o o 8/8 v io --- clksel2 i (pd 100 ) in strp strap (see table 3-6 on page 58.) ak4 trst# i (pu 22.5 ) in pci v io --- ak5 tdi i (pu 22.5 ) in pci v io --- ak6 v io pwr --- --- --- ak7 v ss gnd --- --- --- ak8 vpd1 i in t v io --- ak9 gpio37 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 5 = 0 and pmr[22] 5 = 0 lframe# o o pci pmr[14] 5 = 1 and pmr[22] 5 = 1 ak10 gpio34 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 5 = 0 and pmr[22] 5 = 0 lad2 i/o (pu 22.5 ) in pci , o pci pmr[14] 5 = 1 and pmr[22] 5 = 1 ak11 v io pwr --- --- --- ak12 v ss gnd --- --- --- ak13 sdata_out o o ac97 v io --- tft_prsnt i (pd 100 ) in strp v io strap (see table 3-6 on page 58.) ak14 sdata_in i in t v io fpci_mon = 0 f_gnt0# o o 2/5 fpci_mon = 1 ak15 v ss gnd --- --- --- ak16 v io pwr --- --- --- ak17 v ss gnd --- --- --- ak18 3 md59 i/o in t , ts 2/5 v io --- ak19 3 md62 i/o in t , ts 2/5 v io --- ak20 v io pwr --- --- --- ak21 v ss gnd --- --- --- ak22 3 md26 i/o in t , ts 2/5 v io --- ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration table 3-2. 432-ebga ball assignment - sorted by ball number (continued)
amd geode? sc3200 processor data book 37 signal definitions revision 5.1 ak23 3 md30 i/o in t , ts 2/5 v io --- ak24 3 md53 i/o in t , ts 2/5 v io --- ak25 v io pwr --- --- --- ak26 v ss gnd --- --- --- ak27 3 md21 i/o in t , ts 2/5 v io --- ak28 3 md18 i/o in t , ts 2/5 v io --- ak29 cs1# o o 2/5 v io --- ak30 v ss gnd --- --- --- ak31 v io pwr --- --- --- al1 v ss gnd --- --- --- al2 v io pwr --- --- --- al3 tdn i/o wire v io --- al4 tck i (pu 22.5 ) in pci v io --- al5 gtest i (pd 22.5 ) in t v io --- al6 vpd5 i in t v io --- al7 vpd3 i in t v io --- al8 gpio39 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 5 = 0 and pmr[22] 5 = 0 serirq i/o in pci , o pci pmr[14] 5 = 1 and pmr[22] 5 = 1 al9 gpio36 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 5 = 0 and pmr[22] 5 = 0 ldrq# i in pci pmr[14] 5 = 1 and pmr[22] 5 = 1 al10 gpio33 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 5 = 0 and pmr[22] 5 = 0 lad1 i/o (pu 22.5 ) in pci , o pci pmr[14] 5 = 1 and pmr[22] 5 = 1 al11 gpio13 i/o (pu 22.5 ) in ab , o 8/ 8 v io pmr[19] = 0 ab2d i/o (pu 22.5 ) in ab , od 8 v io pmr[19] = 1 al12 ab1d i/o (pu 22.5 ) in ab , od 8 v io pmr[23] 2 = 0 gpio1 i/o (pu 22.5 ) in t , o 3/5 pmr[23] 2 = 1and pmr[13] = 0 iocs1# o o 3/5 pmr[23] 2 = 1 and pmr[13] = 1 al13 sync o o ac97 v io --- clksel3 i (pd 100 ) in strp strap (see table 3-6 on page 58.) al14 bit_clk i in t v io fpci_mon = 0 f_trdy# o o 1/4 fpci_mon = 1 al15 gpio16 i/o (pu 22.5 ) in t , o 2/5 v io pmr[0] = 0 and fpci_mon = 0 pc_beep o o 2/5 pmr[0] = 1 = 0 and fpci_mon = 0 f_devsel# o o 2/5 fpci_mon = 1 ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration al16 gxclk o o 2/5 v io pmr[23] 2 = 0 and pmr[29] = 0 fp_vdd_on o o 1/4 pmr[23] 2 = 1 test3 o o 2/5 pmr[23] 2 = 0 and pmr[29] = 1 and al17 3 md57 i/o in t , ts 2/5 v io --- al18 3 md60 i/o in t , ts 2/5 v io --- al19 3 md63 i/o in t , ts 2/5 v io --- al20 sdclk2 o o 2/5 v io --- al21 3 md24 i/o in t , ts 2/5 v io --- al22 3 md27 i/o in t , ts 2/5 v io --- al23 3 md31 i/o in t , ts 2/5 v io --- al24 3 md52 i/o in t , ts 2/5 v io --- al25 3 md49 i/o in t , ts 2/5 v io --- al26 dqm2 o o 2/5 v io --- al27 3 md20 i/o in t , ts 2/5 v io --- al28 3 md17 i/o in t , ts 2/5 v io --- al29 3 md16 i/o in t , ts 2/5 v io --- al30 v io pwr --- --- --- al31 v ss gnd --- --- --- 1. for buffer type definitions, refer to table 9-10 "buffer types" on page 375. 2. the tft_prsnt strap determines the power-on reset (por) state of pmr[23]. 3. is back-drive protected (md[63:0], dpos_port1, dneg_port1, dpos_port2, dneg_port2, dpos_port3, dneg_port3, ack#, afd#/dstrb#, busy/wait#, err#, init#, pd[7:0], pe, slct, slin#/astrb#, stb#/wri te#, onctl#, pwrcnt[2:1]). 4. is 5v tolerant (ack#, afd#/dstrb#, busy/wait#, err#, init#, pd[7:0], pe, slct, slin#/astrb#, stb#/write#, onctl#, pwrcnt[2:1]). 5. the lpc_rom strap determines the power-on reset (por) state of pmr[14] and pmr[22]. ball no. signal name i/o (pu/ pd) buffer 1 type power rail configuration table 3-2. 432-ebga ball assignment - sorted by ball number (continued)
38 amd geode? sc3200 processor data book signal definitions revision 5.1 table 3-3. 432-ebga ball assignment - sorted alphabetically by signal name signal name ball no. a0 a17 a1 d16 a2 a18 a3 a15 a4 a16 a5 a14 a6 c15 a7 b14 a8 c14 a9 b13 a10 c13 a11 c12 a12 a12 a13 c11 a14 a11 a15 b10 a16 a7 a17 c7 a18 d7 a19 a6 a20 d6 a21 c6 a22 a5 a23 f4 ab1c aj13 ab1d al12 ab2c aj12 ab2d al11 ac97_clk aj14 ac97_rst# aj15 ack# u3 ad0 a17 ad1 d16 ad2 a18 ad3 a15 ad4 a16 ad5 a14 ad6 c15 ad7 b14 ad8 c14 ad9 b13 ad10 c13 ad11 c12 ad12 a12 ad13 c11 ad14 a11 ad15 b10 ad16 a7 ad17 c7 ad18 d7 ad19 a6 ad20 d6 ad21 c6 ad22 a5 ad23 f4 ad24 c5 ad25 d5 ad26 a4 ad27 b4 ad28 c4 ad29 a3 ad30 c2 ad31 b3 afd#/dstrb# ab2 av ccusb af4 av sspll2 r3 av sspll3 e28 av ssusb ag1 ba0 p30 ba1 p31 bhe# b5 bit_clk al14 boot16 g4 busy/wait# t1 c/be0# a13 c/be1# a10 c/be2# d8 c/be3# a8 casa# n30 ckea ac28 clk27m a23 clk32 h29 clksel0 f3 clksel1 b27 clksel2 ak3 clksel3 al13 cs0# p29 cs1# ak29 cts2# aj2 d0 c5 d1 d5 d2 a4 d3 b4 d4 c4 d5 a3 d6 c2 d7 b3 d8 a13 signal name ball no. d9 a10 d10 d8 d11 a8 d12 c10 d13 b8 d14 c8 d15 d9 dcd2# ag4 devsel# b5 did0 d4 did1 d2 dneg_port1 ag3 dneg_port2 ag2 dneg_port3 af3 doccs# h3, aj13 docr# f1 docw# g3 dpos_port1 ah2 dpos_port2 ah1 dpos_port3 ae4 dqm0 m31 dqm1 af31 dqm2 al26 dqm3 aj21 dqm4 t28 dqm5 ac30 dqm6 aj26 dqm7 aj20 dsr2# aj1 dtr1#/bout1 a28 dtr2#/bout2 ah3 err# aa3 f_ad0 aa1 f_ad1 y1 f_ad2 w3 f_ad3 w2 f_ad4 v1 f_ad5 v2 f_ad6 v3 f_ad7 u1 f_c/be0# aa3 f_c/be1# t1 f_c/be2# t3 f_c/be3# t4 f_devsel# al15 f_frame# ab1 f_gnt0# ak14 f_irdy# w1 f_stop# aj15 signal name ball no.
amd geode? sc3200 processor data book 39 signal definitions revision 5.1 f_trdy# al14 fp_vdd_on b23, al16 fpci_mon d3 fpciclk u3 frame# e1 gnt0# d4 gnt1# d2 gpio0 h1 gpio1 h2, al12 gpio6 ah3 gpio7 ah4 gpio8 aj2 gpio9 ag4 gpio10 aj1 gpio11 h30 gpio12 aj12 gpio13 al11 gpio14 f1 gpio15 g3 gpio16 al15 gpio17 j4 gpio18 a28 gpio19 h4 gpio20 h3, aj13 gpio32 aj11 gpio33 al10 gpio34 ak10 gpio35 aj10 gpio36 al9 gpio37 ak9 gpio38/irrx2 aj9 gpio39 al8 gpio40 a21 gpio41 c19 gpwio0 e31 gpwio1 g28 gpwio2 g29 gtest al5 gxclk al16 hsync j1 ide_addr0 a26 ide_addr1 c26 ide_addr2 c17 ide_cs0# a27 ide_cs1# c16 ide_dack0# c25 ide_dack1# ah4 ide_data0 b24 ide_data1 a24 signal name ball no. ide_data2 d23 ide_data3 c23 ide_data4 b23 ide_data5 a23 ide_data6 c22 ide_data7 b22 ide_data8 a21 ide_data9 c20 ide_data10 a20 ide_data11 c19 ide_data12 b19 ide_data13 a19 ide_data14 c18 ide_data15 b18 ide_dreq0 c24 ide_dreq1 aj2 ide_ior0# c21 ide_ior1# ah3 ide_iordy0 a25 ide_iordy1 aj1 ide_iow0# d24 ide_iow1# ag4 ide_rst# a22 init# y3 inta# ae3 intb# af1 intc# h4 intd# b22 intr_o ab2 iochrdy h4 iocs0# j4 iocs1# h2, al12 ior# f1 iow# g3 irdy# c8 irq14 d25 irq15 h30 irq9 c22 irrx1 j28 irtx j3 lad0 aj11 lad1 al10 lad2 ak10 lad3 aj10 ldrq# al9 led# d31 lframe# ak9 lock# c9 lpc_rom e4 signal name ball no. lpcpd# aj9 ma0 r31 ma1 t31 ma2 t29 ma3 ae28 ma4 ae29 ma5 ae31 ma6 ad28 ma7 ad29 ma8 ad30 ma9 ad31 ma10 r29 ma11 ag28 ma12 ah29 md0 j30 md1 j31 md2 k29 md3 k30 md4 k31 md5 l29 md6 l31 md7 m29 md8 ag30 md9 ag29 md10 ah31 md11 ah30 md12 aj31 md13 ag31 md14 af28 md15 af29 md16 al29 md17 al28 md18 ak28 md19 aj28 md20 al27 md21 ak27 md22 aj27 md23 ah27 md24 al21 md25 aj22 md26 ak22 md27 al22 md28 ah23 md29 aj23 md30 ak23 md31 al23 md32 u31 md33 u29 md34 v31 signal name ball no. table 3-3. 432-ebga ball assignment - sorted alphabetically by signal name (continued)
40 amd geode? sc3200 processor data book signal definitions revision 5.1 md35 v30 md36 v29 md37 w31 md38 w30 md39 w29 md40 ac31 md41 ab29 md42 ab30 md43 ab31 md44 aa29 md45 aa31 md46 y29 md47 y31 md48 ah26 md49 al25 md50 aj25 md51 ah25 md52 al24 md53 ak24 md54 aj24 md55 ah24 md56 aj17 md57 al17 md58 aj18 md59 ak18 md60 al18 md61 aj19 md62 ak19 md63 al19 nc (total of 13) k1, m3, n2, p1, p2, ab3, ac1, ac2, ad1, ad2, ad3, ad4, ae1 onctl# e30 over_cur# c27 pa r c 1 0 pc_beep al15 pciclk e2 pciclk0 d3 pciclk1 e4 pcirst# d1 pd0 aa1 pd1 y1 pd2 w3 pd3 w2 pd4 v1 pd5 v2 pd6 v3 pd7 u1 signal name ball no. pe t3 perr# b9 pll2b d28 pll5b b29 pll6b c28 por# j29 power_en b28 pwrbtn# e29 pwrcnt1 f31 pwrcnt2 g31 rasa# n31 rd# f3 req0# c1 req1# e3 ri2# h30 romcs# g4 rts2# ah4 sdata_in ak14 sdata_in2 h31 sdata_out ak13 sdclk_in aj30 sdclk_out ah28 sdclk0 ac29 sdclk1 ah16 sdclk2 al20 sdclk3 aj16 sdtest0 ah4 sdtest1 aj1 sdtest2 ag4 sdtest3 aj4 sdtest4 aj2 sdtest5 ah3 serirq al8 serr# a9 sin1 d26 sin2 aj4 sin3 j28 slct t4 slin#/astrb# w1 smi_o y3 sout1 b27 sout2 ak3 sout3 j3 stb#/write# ab1 stop# d9 sync al13 tck al4 tdi ak5 signal name ball no. tdn al3 tdo ah6 tdp ah5 test0 d28 test1 c28 test2 b29 test3 al16 tft_prsnt ak13 tftd0 c25, h3 tftd1 d25, v3 tftd10 c21, v1 tftd11 a25, v2 tftd12 c23, h2 tftd13 b19, u1 tftd14 d23, t3 tftd15 a19, t4 tftd16 a24, w1 tftd17 c18, ab1 tftd2 c26, ab2 tftd3 a26, t1 tftd4 c17, aa3 tftd5 a27, y3 tftd6 b24, aa1 tftd7 b18, y1 tftd8 c24, w3 tftd9 d24, w2 tftdck a22, j4 tftde c16, u3 thrm# f28 tms aj5 trde# h1 trdy# b8 trst# ak4 v bat d30 v core (total of 26) d11, d13, d15, d17, d19, d21, k3, l4, l28, n4, n28, r4, r28, t30, u4, u28, w4, w28, aa4, aa28, ah11, ah13, ah15, ah17, ah19, ah21 signal name ball no. table 3-3. 432-ebga ball assignment - sorted alphabetically by signal name (continued)
amd geode? sc3200 processor data book 41 signal definitions revision 5.1 v io (total of 35) a2, a30, b1, b6, b11, b16, b20, b25, b31, c3, c29, g2, g30, l3, m1, m2, m30, n1, t2, y2, y30, ac3, ae2, ae30, aj3, aj29, ak1, ak6, ak11, ak16, ak20, ak25, ak31, al2, al30 vpckin ah7 vpd0 ah9 vpd1 ak8 vpd2 aj8 vpd3 al7 vpd4 ah8 vpd5 al6 vpd6 aj7 vpd7 aj6 v pll2 r1 signal name ball no. v pll3 c31 v sb f29 v sbl h28 v ss (total of 61) a1, a31, b2, b7, b12, b15, b17, b21, b26, b30, d10, d12, d14, d18, d20, d22, f2, f30, k2, k4, k28, l1, l2, l30, m4, m28, n3, p3, p4, p28, r2, r30, u2, u30, v4, v28, y4, y28, aa2, aa30, ab4, ab28, ac4, af2, af30, ah10, ah12, ah14, ah18, ah20, ah22, ak2, ak7, ak12, ak15, ak17, ak21, ak26, ak30, al1, al31 signal name ball no. vsync j2 wea# n29 wr# g1 x27i a29 x27o d27 x32i c30 x32o d29 signal name ball no. table 3-3. 432-ebga ball assignment - sorted alphabetically by signal name (continued)
42 amd geode? sc3200 processor data book signal definitions revision 5.1 figure 3-3. 481-tepbga ball assignment diagram s s s s s s s s s 12345678910111213141516171819202122232425262728293031 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al note: signal names have been abbreviated in this figure due to space constraints. v ss v io ad30 pck0 req1# prst# pcick iow# gp20 gp17 hsnc v io v ss nc nc v ss v pll2 pd7 v ss pd6 pd1 stb# nc nc nc d+p3 d-p3 d+p1 d-p1 v io v ss 12345678910111213141516171819202122232425262728293031 v ss v io ad29 ad28 req0# ad23 v ss rd# wr# v ss vsnc nc v io v ss nc v io busy ack# v io slin# init# v ss nc v ss v ss nc d+p2 d-p2 gp10 v ss v io ad26 ad24 v io ad25 gnt0# gnt1# v io rmcs# gp19 v io irtx v ss v io v ss v ss av ssp2 slct pd4 pd5 pd3 pd0 v io nc nc v io intb# av ssusb gp9 v io gp7 gp8 ad21 ad22 ad20 ad27 ad31 pck1 v ss frm# ior# gp1 trde# v core v ss v io v io nc pe v io v ss pd2 err# afd# v io nc v ss inta# av ccusb gp6 sout tdp tdn ad16 ad19 ad18 dvsl# sin2 trst# tdo tck trdy# irdy# cbe2# ad17 tms tdi gtst vpcki stop# v ss v io v ss v ss v io v ss vpd7 srr# prr# lock# cbe3# vpd6 vpd5 vpd4 vpd3 ad13 cbe1# ad15 par vpd2 vpd1 vpd0 gp39 ad11 v io v ss ad14 gp38 v io v ss gp37 cbe0# ad9 ad10 ad12 gp36 gp35 gp34 gp33 v ss ad7 v io ad8 gp32 gp13 v io v ss ad3 ad6 ad5 v ss ad4 ics1# ad1 v core v ss gp12 ab1d ab1c v core sdo sync acck v ss v ss v ss v ss v core v core v core v core ad0 iad2 ad2 v core idat15 idat14 idat13 v ss v io v ss idat12 idat11 idat10 idat9 idat8 iior0# irst# idat7 idat6 idat5 idat4 v ss v io idat3 idat1 idat2 idat0 idrq0 iiory0 iiow0# iad0 idack0# iad1 v ss v io v ss irq14 ics0# sout1 ovrcur# gp18 sin1 x27i test1 v ss v ss v ss v ss v core v core v core v core v core acrst# bitck sdi v ss sdck3 gxck gp16 md57 sdck1 v ss v io md58 md59 md60 md56 sdck2 md61 md62 md63 md24 v io v ss dqm7 md25 md26 md27 dqm3 md52 md29 md30 md31 v ss v io v ss md28 md50 md49 md54 md53 md21 dqm6 dqm2 md55 pwre x27o test0 v io pbtn# gpw0 v ss ck32 por# md3 md5 wea# v ss v io ma1 md34 md37 v io v ss md41 ma9 ma8 dqm1 md13 v ss ma11 cs1# md18 md48 md20 md51 test2 x32i x32o v pll3 onct# gpw2 v io gp11 md0 v io md6 casa# ba0 ma10 md32 md33 md36 md47 md45 md42 sdck0 v io ma6 ma3 v io md11 sdcki md19 v io md22 md17 v io v ss av ssp3 thrm#gpw1 pcnt1 v ss irrx1 md1 v ss md7 rasa# v io ba1 ma2 v io md35 md46 v io md43 dqm5 v ss ma5 md15 v ss md14 md12 sdcko md16 v ss v io v ss v io v bat led# v sb v sbl pcnt2 sdati2 md2 md4 dqm0 cs0# v ss ma0 dqm4 v ss md38 md39 v ss md44 md40 ckea ma7 ma4 md8 md10 md9 ma12 md23 v io v ss s = gnd ball = pwr ball = strap option ball = multiplexed ball s v core v core v ss v ss v ss v core v core v core v core v ss v ss v ss v core v core v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v core v core v ss v ss v ss v core v core v core v core v ss v ss v ss v core v core (top view) amd geode? sc3200 processor
amd geode? sc3200 processor data book 43 signal definitions revision 5.1 table 3-4. 481-tepbga ball assignment - sorted by ball number ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration a1 v ss gnd --- --- --- a2 v io pwr --- --- --- a3 ad30 i/o in pci , o pci v io cycle multiplexed d6 i/o in pci , o pci a4 pciclk0 o o pci v io --- fpci_mon i (pd 100 ) in strp strap (see table 3- 6 on page 58.) a5 req1# i (pu 22.5 ) in pci v io --- a6 pcirst# o o pci v io --- a7 pciclk i in t v io --- a8 iow# o o 3/5 v io pmr[21] = 0 and pmr[2] = 0 docw# o o 3/5 pmr[21] = 0 and pmr[2] = 1 gpio15 i/o (pu 22.5 ) in ts , o 3/5 pmr[21] = 1 and pmr[2] = 1 a9 gpio20 i/o (pu 22.5 ) in t , o 3/ 5 v io pmr[23] 3 = 0 and pmr[7] = 0 doccs# o (pu 22.5 ) o 3/5 pmr[23] 3 = 0 and pmr[7] = 1 tftd0 o (pu 22.5 ) o 1/4 pmr[23] 3 = 1 a10 gpio17 i/o (pu 22.5 ) in ts , o 3/5 v io pmr[23] 3 = 0 and pmr[5] = 0 iocs0# o (pu 22.5 ) o 3/5 pmr[23] 3 = 0 and pmr[5] = 1 tftdck o (pu 22.5 ) o 1/4 pmr[23] 3 = 1 a11 hsync o o 1/4 v io --- a12 v io pwr --- --- --- a13 v ss gnd --- --- --- a14 nc --- --- --- --- a15 nc --- --- --- --- a16 v ss gnd --- --- --- a17 v pll2 pwr --- --- --- a18 5, 2 pd7 i/o in t , o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd13 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad7 o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) a19 v ss gnd --- --- --- a20 5, 2 pd6 i/o in t , o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd1 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0 f_ad6 o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) a21 5, 2 pd1 i/o in t , o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd7 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad1 o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) a22 5, 2 stb#/write# o o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd17 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_frame# o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) a23 nc --- --- --- --- a24 nc --- --- --- --- a25 nc --- --- --- --- a26 5 dpos_port3 i/o in usb , o usb av c- cusb --- a27 5 dneg_port3 i/o in usb , o usb av c- cusb --- a28 5 dpos_port1 i/o in usb , o usb av c- cusb --- a29 5 dneg_port1 i/o in usb , o usb av c- cusb --- a30 v io pwr --- --- --- a31 v ss gnd --- --- --- b1 v ss gnd --- --- --- b2 v io pwr --- --- --- b3 ad29 i/o in pci , o pci v io cycle multiplexed d5 i/o in pci , o pci b4 ad28 i/o in pci , o pci v io cycle multiplexed d4 i/o in pci , o pci b5 req0# i (pu 22.5 ) inpci v io --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration
44 amd geode? sc3200 processor data book signal definitions revision 5.1 b6 ad23 i/o in pci , o pci v io cycle multiplexed a23 o o pci b7 v ss gnd --- --- --- b8 rd# o o 3/5 v io --- clksel0 i (pd 100 ) in strp strap (see table 3- 6 on page 58.) b9 wr# o o 3/5 v io b10 v ss gnd --- --- --- b11 vsync o o 1/4 v io --- b12 nc --- --- --- --- b13 v io pwr --- --- --- b14 v ss gnd --- --- --- b15 nc --- --- --- --- b16 v io pwr --- --- --- b17 5, 2 busy/wait# i in t v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd3 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_c/be1# o o 1/4 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) b18 5, 2 ack# i in t v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftde o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) fpciclk o o 1/4 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) b19 v io pwr --- --- --- b20 5,2 slin#/astrb# o o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd16 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_irdy# o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) b21 5,2 init# o o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd5 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) smi_o o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) b22 v ss gnd --- --- --- b23 nc --- --- --- --- b24 v ss gnd --- --- --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration b25 v ss gnd --- --- --- b26 nc --- --- --- --- b27 5 dpos_port2 i/o in usb , o usb av c- cusb --- b28 5 dneg_port2 i/o in usb , o usb av c- cusb --- b29 gpio10 i/o (pu 22.5 ) in ts , o 8/8 v io pmr[18] = 0 and pmr[8] = 0 dsr2# i (pu 22.5 ) in ts pmr[18] = 1 and pmr[8] = 0 ide_iordy1 i (pu 22.5 ) in ts1 pmr[18] = 0 and pmr[8] = 1 sdtest1 o (pu 22.5 ) o 2/5 pmr[18] = 1 and pmr[8] = 1 b30 v ss gnd --- --- --- b31 v io pwr --- --- --- c1 ad26 i/o in pci , o pci v io cycle multiplexed d2 i/o in pci , o pci c2 ad24 i/o in pci , o pci v io cycle multiplexed d0 i/o in pci , o pci c3 v io pwr --- --- --- c4 ad25 i/o in pci , o pci v io cycle multiplexed d1 i/o in pci , o pci c5 gnt0# o o pci v io --- did0 i (pd 100 ) in strp strap (see table 3- 6 on page 58.) c6 gnt1# o o pci v io --- did1 i (pd 100 ) in strp strap (see table 3- 6 on page 58.) c7 v io pwr --- --- --- c8 romcs# o o 3/5 v io --- boot16 i (pd 100 ) in strp v io strap (see table 3- 6 on page 58.) c9 gpio19 i/o (pu 22.5 ) in ts , o 3/5 v io pmr[9] = 0 and pmr[4] = 0 intc# i (pu 22.5 ) in ts pmr[9] = 0 and pmr[4] = 1 iochrdy i (pu 22.5 ) in ts1 pmr[9] = 1 and pmr[4] = 1 c10 v io pwr --- --- --- c11 irtx o o 8/8 v io pmr[6] = 0 sout3 o o 8/8 pmr[6] = 1 c12 v ss gnd --- --- --- c13 v io pwr --- --- --- c14 v ss gnd --- --- --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration table 3-4. 481-tepbga ball assignment - sorted by ball number (continued)
amd geode? sc3200 processor data book 45 signal definitions revision 5.1 c15 v ss gnd --- --- --- c16 av sspll2 gnd --- --- --- c17 5,2 slct i in t v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd15 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_c/be3# o o 1/4 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) c18 pd4 i/o in t , o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd10 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad4 o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) c19 5,2 pd5 i/o in t , o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd11 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad5 o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) c20 5,2 pd3 i/o in t , o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd9 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad3 o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) c21 5,2 pd0 i/o in t , o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd6 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad0 o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) c22 v io pwr --- --- --- c23 nc --- --- --- --- c24 nc --- --- --- --- c25 v io pwr --- --- --- c26 intb# i (pu 22.5 ) in pci v io --- c27 av ssusb gnd --- --- --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration c28 gpio9 i/o (pu 22.5 ) in ts , o 1/4 v io pmr[18] = 0 and pmr[8] = 0 dcd2# i (pu 22.5 ) in ts pmr[18] = 1 and pmr[8] = 0 ide_iow1# o (pu 22.5 ) o 1/4 pmr[18] = 0 and pmr[8] = 1 sdtest2 o (pu 22.5 ) o 2/5 pmr[18] = 1 and pmr[8] = 1 c29 v io pwr --- --- --- c30 gpio7 i/o (pu 22.5 ) in ts , o 1/4 v io pmr[17] = 0 and pmr[8] = 0 rts2# o (pu 22.5 ) o 1/4 pmr[17] = 1 and pmr[8] = 0 ide_dack1# o (pu 22.5 ) o 1/4 pmr[17] = 0 and pmr[8] = 1 sdtest0 o (pu 22.5 ) o 2/5 pmr[17] = 1 and pmr[8] = 1 c31 gpio8 i/o (pu 22.5 ) in ts , o 8/8 v io pmr[17] = 0 and pmr[8] = 0 cts2# i (pu 22.5 ) in ts pmr[17] = 1 and pmr[8] = 0 ide_dreq1 i (pu 22.5 ) in ts1 pmr[17] = 0 and pmr[8] = 1 sdtest4 o (pu 22.5 ) o 2/5 pmr[17] = 1 and pmr[8] = 1 d1 ad21 i/o in pci , o pci v io cycle multiplexed a21 o o pci d2 ad22 i/o in pci , o pci v io cycle multiplexed a22 o o pci d3 ad20 i/o in pci , o pci v io cycle multiplexed a20 o o pci d4 ad27 i/o in pci , o pci v io cycle multiplexed d3 i/o in pci , o pci d5 ad31 i/o in pci , o pci v io cycle multiplexed d7 i/o in pci , o pci d6 pciclk1 o o pci v io --- lpc_rom i (pd 100 ) in strp strap (see table 3- 6 on page 58.) d7 v ss gnd --- --- --- d8 frame# i/o (pu 22.5 ) in pci , o pci v io --- d9 ior# o o 3/5 v io pmr[21] = 0 and pmr[2] = 0 docr# o o 3/5 pmr[21] = 0 and pmr[2] = 1 gpio14 i/o (pu 22.5 ) in ts , o 3/5 pmr[21] = 1 and pmr[2] = 1 ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration table 3-4. 481-tepbga ball assignment - sorted by ball number (continued)
46 amd geode? sc3200 processor data book signal definitions revision 5.1 d10 gpio1 i/o (pu 22.5 ) in t , o 3/ 5 v io pmr[23] 3 = 0 and pmr[13] = 0 iocs1# o (pu 22.5 ) o 3/5 v io pmr[23] 3 = 0 and pmr[13] = 1 tftd12 o (pu 22.5 ) o 1/4 v io pmr[23] 3 = 1 d11 trde# o o 3/5 v io pmr[12] = 0 gpio0 i/o (pu 22.5 ) in ts , o 3/5 v io pmr[12] = 1 d12 v core pwr --- --- --- d13 v ss gnd --- --- --- d14 v io pwr --- --- --- d15 v io pwr --- --- --- d16 nc --- --- --- --- d17 5, 2 pe i (pu 22.5 pd 22.5 ) in t v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) (pu/pd under soft- ware control.) tftd14 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_c/be2# o o 1/4 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) d18 v io pwr --- --- --- d19 v ss gnd --- --- --- d20 5, 2 pd2 i/o in t , o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd8 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_ad2 o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) d21 5, 2 err# i in t , o 1/ 4 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd4 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) f_c/be0# o o 1/4 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) d22 5, 2 afd#/dstrb# o o 14/14 v io pmr[23] 3 = 0 and (pmr[27] = 0 and fpci_mon = 0) tftd2 o o 1/4 pmr[23] 3 = 1 and (pmr[27] = 0 and fpci_mon = 0) intr_o o o 14/14 pmr[23] 3 = 0 and (pmr[27] = 1 or fpci_mon = 1) d23 v io pwr --- --- --- d24 nc --- --- --- --- d25 v ss gnd --- --- --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration d26 inta# i (pu 22.5 ) in pci v io --- d27 av ccusb pwr --- --- --- d28 gpio6 i/o (pu 22.5 ) in ts , o 1/4 v io pmr[18] = 0 and pmr[8] = 0 dtr2#/bout2 o (pu 22.5 ) o 1/4 pmr[18] = 1 and pmr[8] = 0 ide_ior1# o (pu 22.5 ) o 1/4 pmr[18] = 0 and pmr[8] = 1 sdtest5 o (pu 22.5 ) o 2/5 pmr[18] = 1 and pmr[8] = 1 d29 sout2 o o 8/8 v io --- clksel2 i (pd 100 ) in strp strap (see table 3- 6 on page 58.) d30 tdp i/o diode --- --- d31 tdn i/o wire v io --- e1 ad16 i/o in pci , o pci v io cycle multiplexed a16 o o pci e2 ad19 i/o in pci , o pci v io cycle multiplexed a19 o o pci e3 ad18 i/o in pci , o pci v io cycle multiplexed a18 o o pci e4 devsel# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed bhe# o o pci e28 sin2 i in ts v io pmr[28] = 0 sdtest3 o o 2/5 pmr[28] = 1 e29 trst# i (pu 22.5 ) in pci v io --- e30 tdo o o pci v io --- e31 tck i (pu 22.5 ) in pci v io --- f1 trdy# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d13 i/o (pu 22.5 ) in pci , o pci f2 irdy# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d14 i/o (pu 22.5 ) in pci , o pci f3 c/be2# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d10 i/o (pu 22.5 ) in pci , o pci f4 ad17 i/o in pci , o pci v io cycle multiplexed a17 o o pci f28 tms i (pu 22.5 ) in pci v io --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration table 3-4. 481-tepbga ball assignment - sorted by ball number (continued)
amd geode? sc3200 processor data book 47 signal definitions revision 5.1 f29 tdi i (pu 22.5 ) in pci v io --- f30 gtest i (pd 22.5 ) in t v io --- f31 vpckin i in t v io --- g1 stop# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d15 i/o (pu 22.5 ) in pci , o pci g2 v ss gnd --- --- --- g3 v io pwr --- --- --- g4 v ss gnd --- --- --- g28 v ss gnd --- --- --- g29 v io pwr --- --- --- g30 v ss gnd --- --- --- g31 vpd7 i in t v io --- h1 serr# i/o (pu 22.5 ) in pci , od pci v io --- h2 perr# i/o (pu 22.5 ) in pci , o pci v io --- h3 lock# i/o (pu 22.5 ) in pci , o pci v io --- h4 c/be3# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d11 i/o (pu 22.5 ) in pci , o pci h28 vpd6 i in t v io --- h29 vpd5 i in t v io --- h30 vpd4 i in t v io --- h31 vpd3 i in t v io --- j1 ad13 i/o in pci , o pci v io cycle multiplexed a13 o o pci j2 c/be1# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d9 i/o (pu 22.5 ) in pci , o pci j3 ad15 i/o in pci , o pci v io cycle multiplexed a15 o o pci j4 par i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d12 i/o (pu 22.5 ) in pci , o pci j28 vpd2 i in t v io --- j29 vpd1 i in t v io --- j30 vpd0 i in t v io --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration j31 gpio39 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 4 = 0 and pmr[22] 4 = 0 serirq i/o in pci , o pci pmr[14] 4 = 1 and pmr[22] 4 = 1 k1 ad11 i/o in pci , o pci v io cycle multiplexed a11 o o pci k2 v io pwr --- --- --- k3 v ss gnd --- --- --- k4 ad14 i/o in pci , o pci v io cycle multiplexed a14 o o pci k28 gpio38/irrx2 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 4 = 0 and pmr[22] 4 = 0. the irrx2 input is con- nected to the input path of gpio38. there is no logic required to enable irrx2, just a sim- ple connection. hence, when gpio38 is the selected function, irrx2 is also selected. lpcpd# o o pci pmr[14] 4 = 1 and pmr[22] 4 = 1 k29 v io pwr --- --- --- k30 v ss gnd --- --- --- k31 gpio37 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 4 = 0 and pmr[22] 4 = 0 lframe# o o pci pmr[14] 4 = 1 and pmr[22] 4 = 1 l1 c/be0# i/o (pu 22.5 ) in pci , o pci v io cycle multiplexed d8 i/o (pu 22.5 ) in pci , o pci l2 ad9 i/o in pci , o pci v io cycle multiplexed a9 o o pci l3 ad10 i/o in pci , o pci v io cycle multiplexed a10 o o pci l4 ad12 i/o in pci , o pci v io cycle multiplexed a12 o o pci l28 gpio36 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 4 = 0 and pmr[22] 4 = 0 ldrq# i in pci pmr[14] 4 = 1 and pmr[22] 4 = 1 ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration table 3-4. 481-tepbga ball assignment - sorted by ball number (continued)
48 amd geode? sc3200 processor data book signal definitions revision 5.1 l29 gpio35 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 4 = 0 and pmr[22] 4 = 0 lad3 i/o (pu 22.5 ) in pci , o pci pmr[14] 4 = 1 and pmr[22] 4 = 1 l30 gpio34 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 4 = 0 and pmr[22] 4 = 0 lad2 i/o (pu 22.5 ) in pci , o pci pmr[14] 4 = 1 and pmr[22] 4 = 1 l31 gpio33 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 4 = 0 and pmr[22] 4 = 0 lad1 i/o (pu 22.5 ) in pci , o pci pmr[14] 4 = 1 and pmr[22] 4 = 1 m1 v ss gnd --- --- --- m2 ad7 i/o in pci , o pci v io cycle multiplexed a7 o o pci m3 v io pwr --- --- --- m4 ad8 i/o in pci , o pci v io cycle multiplexed a8 o o pci m28 gpio32 i/o (pu 22.5 ) in pci , o pci v io pmr[14] 4 = 0 and pmr[22] 4 = 0 lad0 i/o (pu 22.5 ) in pci , o pci pmr[14] 4 = 1 and pmr[22] 4 = 1 m29 gpio13 i/o (pu 22.5 ) in ab , o 8/8 v io pmr[19] = 0 ab2d i/o (pu 22.5 ) in ab , od 8 v io pmr[19] = 1 m30 v io pwr --- --- --- m31 v ss gnd --- --- --- n1 ad3 i/o in pci , o pci v io cycle multiplexed a3 o o pci n2 ad6 i/o in pci , o pci v io cycle multiplexed a6 o o pci n3 ad5 i/o in pci , o pci v io cycle multiplexed a5 o o pci n4 v ss gnd --- --- --- n13 v core pwr --- --- --- n14 v core pwr --- --- --- n15 v ss gnd --- --- --- n16 v ss gnd --- --- --- n17 v ss gnd --- --- --- n18 v core pwr --- --- --- n19 v core pwr --- --- --- n28 v ss gnd --- --- --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration n29 gpio12 i/o (pu 22.5 ) in ab , o 8/8 v io pmr[19] = 0 ab2c i/o (pu 22.5 ) in ab , od 8 pmr[19] = 1 n30 ab1d i/o (pu 22.5 ) in ab , od 8 v io pmr[23] 3 = 0 gpio1 i/o (pu 22.5 ) in t , o 3/ 5 pmr[23] 3 = 1 and pmr[13] = 0 iocs1# o o 3/5 pmr[23] 3 = 1 and pmr[13] = 1 n31 ab1c i/o (pu 22.5 ) in ab , od 8 v io pmr[23] 3 = 0 gpio20 i/o (pu 22.5 ) in t , o 3/ 5 pmr[23] 3 = 1 and pmr[7] = 0 doccs# o o3/5 pmr[23] 3 = 1 and pmr[7] = 1 p1 ad4 i/o in pci , o pci v io cycle multiplexed a4 o o pci p2 ide_cs1# o o 1/4 v io pmr[24] = 0 tftde o o 1/4 pmr[24] = 1 p3 ad1 i/o in pci , o pci v io cycle multiplexed a1 o o pci p4 v core pwr --- --- --- p13 v core pwr --- --- --- p14 v core pwr --- --- --- p15 v ss gnd --- --- --- p16 v ss gnd --- --- --- p17 v ss gnd --- --- --- p18 v core pwr --- --- --- p19 v core pwr --- --- --- p28 v core pwr --- --- --- p29 sdata_out o o ac97 v io --- tft_prsnt i (pd 100 ) in strp v io strap (see table 3- 6 on page 58.) p30 sync o o ac97 v io --- clksel3 i (pd 100 ) in strp strap (see table 3- 6 on page 58.) p31 ac97_clk o o 2/5 v io pmr[25] = 1 r1 v ss gnd --- --- --- r2 v ss gnd --- --- --- r3 v ss gnd --- --- --- r4 v ss gnd --- --- --- r13 v ss gnd --- --- --- r14 v ss gnd --- --- --- r15 v ss gnd --- --- --- r16 v ss gnd --- --- --- r17 v ss gnd --- --- --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration table 3-4. 481-tepbga ball assignment - sorted by ball number (continued)
amd geode? sc3200 processor data book 49 signal definitions revision 5.1 r18 v ss gnd --- --- --- r19 v ss gnd --- --- --- r28 v ss gnd --- --- --- r29 v ss gnd --- --- --- r30 v ss gnd --- --- --- r31 v ss gnd --- --- --- t1 v core pwr --- --- --- t2 v core pwr --- --- --- t3 v core pwr --- --- --- t4 v core pwr --- --- --- t13 v ss gnd --- --- --- t14 v ss gnd --- --- --- t15 v ss gnd --- --- --- t16 v ss gnd --- --- --- t17 v ss gnd --- --- --- t18 v ss gnd --- --- --- t19 v ss gnd --- --- --- t28 v core pwr --- --- --- t29 v core pwr --- --- --- t30 v core pwr --- --- --- t31 v core pwr --- --- --- u1 ad0 i/o in pci , o pci v io cycle multiplexed a0 o o pci u2 ide_addr2 o o 1/4 v io pmr[24] = 0 tftd4 o o 1/4 pmr[24] = 1 u3 ad2 i/o in pci , o pci v io cycle multiplexed a2 o o pci u4 v core pwr --- --- --- u13 v ss gnd --- --- --- u14 v ss gnd --- --- --- u15 v ss gnd --- --- --- u16 v ss gnd --- --- --- u17 v ss gnd --- --- --- u18 v ss gnd --- --- --- u19 v ss gnd --- --- --- u28 v core pwr --- --- --- u29 ac97_rst# o o 2/5 v io fpci_mon = 0 f_stop# o o 2/5 fpci_mon = 1 u30 bit_clk i in t v io fpci_mon = 0 f_trdy# o o 1/4 fpci_mon = 1 u31 sdata_in i in t v io fpci_mon = 0 f_gnt0# o o 2/5 fpci_mon = 1 ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration v1 ide_data15 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd7 o o 1/4 pmr[24] = 1 v2 ide_data14 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd17 o o 1/4 pmr[24] = 1 v3 ide_data13 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd15 o o 1/4 pmr[24] = 1 v4 v ss gnd --- --- --- v13 v core pwr --- --- --- v14 v core pwr --- --- --- v15 v ss gnd --- --- --- v16 v ss gnd --- --- --- v17 v ss gnd --- --- --- v18 v core pwr --- --- --- v19 v core pwr --- --- --- v28 v ss gnd --- --- --- v29 sdclk3 o o 2/5 v io --- v30 gxclk o o 2/5 v io pmr[23] 3 = 0 and pmr[29] = 0 fp_vdd_on o o 1/4 pmr[23] 3 = 1 test3 o o 2/5 pmr[23] 3 = 0 and pmr[29] = 1 v31 gpio16 i/o (pu 22.5 ) in t , o 2/ 5 v io pmr[0] = 0 and fpci_mon = 0 pc_beep o o 2/5 pmr[0] = 1 = 0 and fpci_mon = 0 f_devsel# o o 2/5 fpci_mon = 1 w1 v io pwr --- --- --- w2 v ss gnd --- --- --- w3 ide_data12 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd13 o o 1/4 pmr[24] = 1 w4 ide_data11 i/o in ts1 , ts 1/4 v io pmr[24] = 0 gpio41 i/o in ts1 , o 1/4 pmr[24] = 1 w13 v core pwr --- --- --- w14 v core pwr --- --- --- w15 v ss gnd --- --- --- w16 v ss gnd --- --- --- w17 v ss gnd --- --- --- w18 v core pwr --- --- --- w19 v core pwr --- --- --- w28 5 md57 i/o in t , ts 2/5 v io --- w29 sdclk1 o o 2/5 v io --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration table 3-4. 481-tepbga ball assignment - sorted by ball number (continued)
50 amd geode? sc3200 processor data book signal definitions revision 5.1 w30 v ss gnd --- --- --- w31 v io pwr --- --- --- y1 ide_data10 i/o in ts1 , ts 1/4 v io pmr[24] = 0 y2 ide_data9 i/o in ts1 , ts 1/4 v io pmr[24] = 0 y3 ide_data8 i/o in ts1 , ts 1/4 v io pmr[24] = 0 gpio40 i/o in ts1 , o 1/4 pmr[24] = 1 y4 ide_ior0# o o 1/4 v io pmr[24] = 0 tftd10 o o 1/4 pmr[24] = 1 y28 5 md58 i/o in t , ts 2/5 v io --- y29 5 md59 i/o in t , ts 2/5 v io --- y30 5 md60 i/o in t , ts 2/5 v io --- y31 5 md56 i/o in t , ts 2/5 v io --- aa1 ide_rst# o o 1/4 v io pmr[24] = 0 tftdck o o 1/4 pmr[24] = 1 aa2 ide_data7 i/o in ts1 , ts 1/4 v io pmr[24] = 0 intd# i in ts pmr[24] = 1 aa3 ide_data6 i/o in ts1 , ts 1/4 v io pmr[24] = 0 irq9 i in ts1 pmr[24] = 1 aa4 ide_data5 i/o in ts1 , ts 1/4 v io pmr[24] = 0 clk27m o o 1/4 pmr[24] = 1 aa28 sdclk2 o o 2/5 v io --- aa29 5 md61 i/o in t , ts 2/5 v io --- aa30 5 md62 i/o in t , ts 2/5 v io --- aa31 5 md63 i/o in t , ts 2/5 v io --- ab1 ide_data4 i/o in ts1 , ts 1/4 v io pmr[24] = 0 fp_vdd_on o o 1/4 pmr[24] = 1 ab2 v ss gnd --- --- --- ab3 v io pwr --- --- --- ab4 ide_data3 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd12 o o 1/4 pmr[24] = 1 ab28 5 md24 i/o in t , ts 2/5 v io --- ab29 v io pwr --- --- --- ab30 v ss gnd --- --- --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration ab31 dqm7 o o 2/5 v io --- ac1 ide_data1 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd16 o o 1/4 pmr[24] = 1 ac2 ide_data2 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd14 o o 1/4 pmr[24] = 1 ac3 ide_data0 i/o in ts1 , ts 1/4 v io pmr[24] = 0 tftd6 o o 1/4 pmr[24] = 1 ac4 ide_dreq0 i in ts1 v io pmr[24] = 0 tftd8 o o 1/4 pmr[24] = 1 ac28 5 md25 i/o in t , ts 2/5 v io --- ac29 5 md26 i/o in t , ts 2/5 v io --- ac30 5 md27 i/o in t , ts 2/5 v io --- ac31 dqm3 o o 2/5 v io --- ad1 ide_iordy0 i in ts1 v io pmr[24] = 0 tftd11 o o 1/4 pmr[24] = 1 ad2 ide_iow0# o o 1/4 v io pmr[24] = 0 tftd9 o o 1/4 pmr[24] = 1 ad3 ide_addr0 o o 1/4 v io pmr[24] = 0 tftd3 o o 1/4 pmr[24] = 1 ad4 ide_dack0# o o 1/4 v io pmr[24] = 0 tftd0 o o 1/4 pmr[24] = 1 ad28 5 md52 i/o in t , ts 2/5 v io --- ad29 5 md29 i/o in t , ts 2/5 v io --- ad30 5 md30 i/o in t , ts 2/5 v io --- ad31 5 md31 i/o in t , ts 2/5 v io --- ae1 ide_addr1 o o 1/4 v io pmr[24] = 0 tftd2 o o 1/4 pmr[24] = 1 ae2 v ss gnd --- --- --- ae3 v io pwr --- --- --- ae4 v ss gnd --- --- --- ae28 v ss gnd --- --- --- ae29 v io pwr --- --- --- ae30 v ss gnd --- --- --- ae31 5 md28 i/o in t , ts 2/5 v io --- af1 irq14 i in ts1 v io pmr[24] = 0 tftd1 o o 1/4 pmr[24] = 1 ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration table 3-4. 481-tepbga ball assignment - sorted by ball number (continued)
amd geode? sc3200 processor data book 51 signal definitions revision 5.1 af2 ide_cs0# o o 1/4 v io pmr[24] = 0 tftd5 o o 1/4 pmr[24] = 1 af3 sout1 o o 8/8 v io --- clksel1 i (pd 100 ) in strp strap (see table 3- 6 on page 58.) af4 over_cur# i in ts v io --- af28 5 md50 i/o in t , ts 2/5 v io --- af29 5 md49 i/o in t , ts 2/5 v io --- af30 5 md54 i/o in t , ts 2/5 v io --- af31 5 md53 i/o in t , ts 2/5 v io --- ag1 gpio18 i/o (pu 22.5 ) in ts , o 8/8 v io pmr[16] = 0 dtr1#/bout1 o (pu 22.5 ) o 8/8 pmr[16] =1 ag2 sin1 i in ts v io --- ag3 x27i i wire v io --- ag4 test1 o o 2/5 v io pmr[29] = 1 pll6b i/o in ts , ts 2/5 pmr[29] = 0 ag28 5 md21 i/o in t , ts 2/5 v io --- ag29 dqm6 o o 2/5 v io --- ag30 dqm2 o o 2/5 v io --- ag31 5 md55 i/o in t , ts 2/5 v io --- ah1 power_en o o 1/4 v io --- ah2 x27o o wire v io --- ah3 test0 o o 2/5 v io pmr[29] = 1 pll2b i/o in t , ts 2/5 pmr[29] = 0 ah4 v io pwr --- --- --- ah5 pwrbtn# i (pu 100 ) in btn v sb --- ah6 gpwio0 i/o (pu 100 ) in ts , ts 2/14 v sb --- ah7 v ss gnd --- --- --- ah8 clk32 o o 2/5 v sb --- ah9 por# i in ts v io --- ah10 5 md3 i/o in t , ts 2/5 v io --- ah11 5 md5 i/o in t , ts 2/5 v io --- ah12 wea# o o 2/5 v io --- ah13 v ss gnd --- --- --- ah14 v io pwr --- --- --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration ah15 ma1 o o 2/5 v io --- ah16 5 md34 i/o in t , ts 2/5 v io --- ah17 5 md37 i/o in t , ts 2/5 v io --- ah18 v io pwr --- --- --- ah19 v ss gnd --- --- --- ah20 5 md41 i/o in t , ts 2/5 v io --- ah21 ma9 o o 2/5 v io --- ah22 ma8 o o 2/5 v io --- ah23 dqm1 o o 2/5 v io --- ah24 5 md13 i/o in t , ts 2/5 v io --- ah25 v ss gnd --- --- --- ah26 ma11 o o 2/5 v io --- ah27 cs1# o o 2/5 v io --- ah28 5 md18 i/o in t , ts 2/5 v io --- ah29 5 md48 i/o in t , ts 2/5 v io --- ah30 5 md20 i/o in t , ts 2/5 v io --- ah31 5 md51 i/o in t , ts 2/5 v io --- aj1 test2 o o 2/5 v io pmr[29] = 1 pll5b i/o in t , ts 2/5 pmr[29] = 0 aj2 x32i i wire v bat --- aj3 x32o o wire v bat --- aj4 v pll3 pwr --- --- --- aj5 5, 2 onctl# o od 14 v sb --- aj6 gpwio2 i/o (pu 100 ) in ts , ts 2/14 v sb --- aj7 v io pwr --- --- --- aj8 gpio11 i/o (pu 22.5 ) in ts , o 8/8 v io pmr[18] = 0 and pmr[8] = 0 ri2# i (pu 22.5 ) in ts pmr[18] = 1 and pmr[8] = 0 irq15 i (pu 22.5 ) in ts1 pmr[18] = 0 and pmr[8] = 1 aj9 5 md0 i/o in t , ts 2/5 v io --- aj10 v io pwr --- --- --- aj11 5 md6 i/o in t , ts 2/5 v io --- aj12 casa# o o 2/5 v io --- aj13 ba0 o o 2/5 v io --- aj14 ma10 o o 2/5 v io --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration table 3-4. 481-tepbga ball assignment - sorted by ball number (continued)
52 amd geode? sc3200 processor data book signal definitions revision 5.1 aj15 5 md32 i/o in t , ts 2/5 v io --- aj16 5 md33 i/o in t , ts 2/5 v io --- aj17 5 md36 i/o in t , ts 2/5 v io --- aj18 5 md47 i/o in t , ts 2/5 v io --- aj19 5 md45 i/o in t , ts 2/5 v io --- aj20 5 md42 i/o in t , ts 2/5 v io --- aj21 sdclk0 o o 2/5 v io --- aj22 v io pwr --- --- --- aj23 ma6 o o 2/5 v io --- aj24 ma3 o o 2/5 v io --- aj25 v io pwr --- --- --- aj26 5 md11 i/o in t , ts 2/5 v io --- aj27 sdclk_in i in t v io --- aj28 5 md19 i/o in t , ts 2/5 v io --- aj29 v io pwr --- --- --- aj30 5 md22 i/o in t , ts 2/5 v io --- aj31 5 md17 i/o in t , ts 2/5 v io --- ak1 v io pwr --- --- --- ak2 v ss gnd --- --- --- ak3 av sspll3 gnd --- --- --- ak4 thrm# i in ts v sb --- ak5 gpwio1 i/o (pu 100 ) in ts , ts 2/14 v sb --- ak6 5, 2 pwrcnt1 o od 14 v sb --- ak7 v ss gnd --- --- --- ak8 irrx1 i in ts v sb pmr[6] = 0 sin3 i in ts v io pmr[6] =1 ak9 5 md1 i/o in t , ts 2/5 v io --- ak10 v ss gnd --- --- --- ak11 5 md7 i/o in t , ts 2/5 v io --- ak12 rasa# o o 2/5 v io --- ak13 v io pwr --- --- --- ak14 ba1 o o 2/5 v io --- ak15 ma2 o o 2/5 v io --- ak16 v io pwr --- --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration ak17 5 md35 i/o in t , ts 2/5 v io --- ak18 5 md46 i/o in t , ts 2/5 v io --- ak19 v io pwr --- --- --- ak20 5 md43 i/o in t , ts 2/5 v io --- ak21 dqm5 o o 2/5 v io --- ak22 v ss gnd --- --- --- ak23 ma5 o o 2/5 v io --- ak24 5 md15 i/o in t , ts 2/5 v io --- ak25 v ss gnd --- --- --- ak26 5 md14 i/o in t , ts 2/5 v io --- ak27 5 md12 i/o in t , ts 2/5 v io --- ak28 sdclk_out o o 2/5 v io --- ak29 5 md16 i/o in t , ts 2/5 v io --- ak30 v ss gnd --- --- --- ak31 v io pwr --- --- --- al1 v ss gnd --- --- --- al2 v io pwr --- --- --- al3 v bat pwr --- --- --- al4 led# o od 14 v sb --- al5 v sb pwr --- --- --- al6 v sbl pwr --- --- --- al7 5, 2 pwrcnt2 o od 14 v sb --- al8 sdata_in2 i in ts v sb f3bar0+memory offset 08h[21] = 1 al9 5 md2 i/o in t , ts 2/5 v io --- al10 5 md4 i/o in t , ts 2/5 v io --- al11 dqm0 o o 2/5 v io --- al12 cs0# o o 2/5 v io --- al13 v ss gnd --- --- --- al14 ma0 o o 2/5 v io --- al15 dqm4 o o 2/5 v io --- al16 v ss gnd --- --- --- al17 5 md38 i/o in t , ts 2/5 v io --- al18 5 md39 i/o in t , ts 2/5 v io --- al19 v ss gnd --- --- --- al20 5 md44 i/o in t , ts 2/5 v io --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration table 3-4. 481-tepbga ball assignment - sorted by ball number (continued)
amd geode? sc3200 processor data book 53 signal definitions revision 5.1 al21 5 md40 i/o in t , ts 2/5 v io --- al22 ckea o o 2/5 v io --- al23 ma7 o o 2/5 v io --- al24 ma4 o o 2/5 v io --- al25 5 md8 i/o in t , ts 2/5 v io --- al26 5 md10 i/o in t , ts 2/5 v io --- al27 5 md9 i/o in t , ts 2/5 v io --- al28 ma12 o o 2/5 v io --- ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration al29 5 md23 i/o in t , ts 2/5 v io --- al30 v io pwr --- --- --- al31 v ss gnd --- --- --- 1. for buffer type definitions, refer to table 9-10 "buffer types" on page 375. 2. is 5v tolerant (ack#, afd#/dstrb#, busy/wait#, err#, init#, pd[7:0], pe, slct, slin#/astrb#, stb#/write#, onctl#, pwrcnt[2:1]). 3. the tft_prsnt strap determines the power-on reset (por) state of pmr[23]. 4. the lpc_rom strap determines the power-on reset (por) state of pmr[14] and pmr[22]. 5. is back-drive protected (md[63:0], dpos_port1, dneg_port1, dpos_port2, dneg_port2, dpos_port3, dneg_port3, ack#, afd#/dstrb#, busy/wait#, err#, init#, pd[7:0], pe, slct, slin#/astrb#, stb#/wri te#, onctl#, pwrcnt[2:1]). ball no. signal name i/o (pu/pd) buffer 1 type power rail configuration table 3-4. 481-tepbga ball assignment - sorted by ball number (continued)
54 amd geode? sc3200 processor data book signal definitions revision 5.1 table 3-5. 481-tepbga ball assignment - sorted alphabetically by signal name signal name ball no. a0 u1 a1 p3 a2 u3 a3 n1 a4 p1 a5 n3 a6 n2 a7 m2 a8 m4 a9 l2 a10 l3 a11 k1 a12 l4 a13 j1 a14 k4 a15 j3 a16 e1 a17 f4 a18 e3 a19 e2 a20 d3 a21 d1 a22 d2 a23 b6 ab1c n31 ab1d n30 ab2c n29 ab2d m29 ac97_clk p31 ac97_rst# u29 ack# b18 ad0 u1 ad1 p3 ad2 u3 ad3 n1 ad4 p1 ad5 n3 ad6 n2 ad7 m2 ad8 m4 ad9 l2 ad10 l3 ad11 k1 ad12 l4 ad13 j1 ad14 k4 ad15 j3 ad16 e1 ad17 f4 ad18 e3 ad19 e2 ad20 d3 ad21 d1 ad22 d2 ad23 b6 ad24 c2 ad25 c4 ad26 c1 ad27 d4 ad28 b4 ad29 b3 ad30 a3 ad31 d5 afd#/dstrb# d22 av ccusb d27 av sspll2 c16 av sspll3 ak3 av ssusb c27 ba0 aj13 ba1 ak14 bhe# e4 bit_clk u30 boot16 c8 busy/wait# b17 c/be0# l1 c/be1# j2 c/be2# f3 c/be3# h4 casa# aj12 ckea al22 clk27m aa4 clk32 ah8 clksel0 b8 clksel1 af3 clksel2 d29 clksel3 p30 cs0# al12 cs1# ah27 cts2# c31 d0 c2 d1 c4 d2 c1 d3 d4 d4 b4 d5 b3 d6 a3 d7 d5 signal name ball no. d8 l1 d9 j2 d10 f3 d11 h4 d12 j4 d13 f1 d14 f2 d15 g1 dcd2# c28 devsel# e4 did0 c5 did1 c6 dneg_port1 a29 dneg_port2 b28 dneg_port3 a27 doccs# a9, n31 docr# d9 docw# a8 dpos_port1 a28 dpos_port2 b27 dpos_port3 a26 dqm0 al11 dqm1 ah23 dqm2 ag30 dqm3 ac31 dqm4 al15 dqm5 ak21 dqm6 ag29 dqm7 ab31 dsr2# b29 dtr1#/bout1 ag1 dtr2#/bout2 d28 err# d21 f_ad0 c21 f_ad1 a21 f_ad2 d20 f_ad3 c20 f_ad4 c18 f_ad5 c19 f_ad6 a20 f_ad7 a18 f_c/be0# d21 f_c/be1# b17 f_c/be2# d17 f_c/be3# c17 f_devsel# v31 f_frame# a22 f_gnt0# u31 f_irdy# b20 signal name ball no.
amd geode? sc3200 processor data book 55 signal definitions revision 5.1 f_stop# u29 f_trdy# u30 fp_vdd_on v30, ab1 fpci_mon a4 fpciclk b18 frame# d8 gnt0# c5 gnt1# c6 gpio0 d11 gpio1 d10, n30 gpio6 d28 gpio7 c30 gpio8 c31 gpio9 c28 gpio10 b29 gpio11 aj8 gpio12 n29 gpio13 m29 gpio14 d9 gpio15 a8 gpio16 v31 gpio17 a10 gpio18 ag1 gpio19 c9 gpio20 a9, n31 gpio32 m28 gpio33 l31 gpio34 l30 gpio35 l29 gpio36 l28 gpio37 k31 gpio38/irrx2 k28 gpio39 j31 gpio40 y3 gpio41 w4 gpwio0 ah6 gpwio1 ak5 gpwio2 aj6 gtest f30 gxclk v30 hsync a11 ide_addr0 ad3 ide_addr1 ae1 ide_addr2 u2 ide_cs0# af2 ide_cs1# p2 ide_dack0# ad4 ide_dack1# c30 ide_data0 ac3 signal name ball no. ide_data1 ac1 ide_data2 ac2 ide_data3 ab4 ide_data4 ab1 ide_data5 aa4 ide_data6 aa3 ide_data7 aa2 ide_data8 y3 ide_data9 y2 ide_data10 y1 ide_data11 w4 ide_data12 w3 ide_data13 v3 ide_data14 v2 ide_data15 v1 ide_dreq0 ac4 ide_dreq1 c31 ide_ior0# y4 ide_ior1# d28 ide_iordy0 ad1 ide_iordy1 b29 ide_iow0# ad2 ide_iow1# c28 ide_rst# aa1 init# b21 inta# d26 intb# c26 intc# c9 intd# aa2 intr_o d22 iochrdy c9 iocs0# a10 iocs1# d10 iocs1# n30 ior# d9 iow# a8 irdy# f2 irq9 aa3 irq14 af1 irq15 aj8 irrx1 ak8 irtx c11 lad0 m28 lad1 l31 lad2 l30 lad3 l29 ldrq# l28 led# al4 lframe# k31 signal name ball no. lock# h3 lpc_rom d6 lpcpd# k28 ma0 al14 ma1 ah15 ma2 ak15 ma3 aj24 ma4 al24 ma5 ak23 ma6 aj23 ma7 al23 ma8 ah22 ma9 ah21 ma10 aj14 ma11 ah26 ma12 al28 md0 aj9 md1 ak9 md2 al9 md3 ah10 md4 al10 md5 ah11 md6 aj11 md7 ak11 md8 al25 md9 al27 md10 al26 md11 aj26 md12 ak27 md13 ah24 md14 ak26 md15 ak24 md16 ak29 md17 aj31 md18 ah28 md19 aj28 md20 ah30 md21 ag28 md22 aj30 md23 al29 md24 ab28 md25 ac28 md26 ac29 md27 ac30 md28 ae31 md29 ad29 md30 ad30 md31 ad31 md32 aj15 signal name ball no. table 3-5. 481-tepbga ball assignment - sorted alphabetically by signal name (continued)
56 amd geode? sc3200 processor data book signal definitions revision 5.1 md33 aj16 md34 ah16 md35 ak17 md36 aj17 md37 ah17 md38 al17 md39 al18 md40 al21 md41 ah20 md42 aj20 md43 ak20 md44 al20 md45 aj19 md46 ak18 md47 aj18 md48 ah29 md49 af29 md50 af28 md51 ah31 md52 ad28 md53 af31 md54 af30 md55 ag31 md56 y31 md57 w28 md58 y28 md59 y29 md60 y30 md61 aa29 md62 aa30 md63 aa31 nc (total of 13) a14, a15, a23, a24, a25, b12, b15, b23, b26, c23, c24, d16, d24 onctl# aj5 over_cur# af4 pa r j 4 pc_beep v31 pciclk a7 pciclk0 a4 pciclk1 d6 pcirst# a6 pd0 c21 pd1 a21 pd2 d20 pd3 c20 signal name ball no. pd4 c18 pd5 c19 pd6 a20 pd7 a18 pe d17 perr# h2 pll2b ah3 pll5b aj1 pll6b ag4 por# ah9 power_en ah1 pwrbtn# ah5 pwrcnt1 ak6 pwrcnt2 al7 rasa# ak12 rd# b8 req0# b5 req1# a5 ri2# aj8 romcs# c8 rts2# c30 sdata_in u31 sdata_in2 al8 sdata_out p29 sdclk_in aj27 sdclk_out ak28 sdclk0 aj21 sdclk1 w29 sdclk2 aa28 sdclk3 v29 sdtest0 c30 sdtest1 b29 sdtest2 c28 sdtest3 e28 sdtest4 c31 sdtest5 d28 serirq j31 serr# h1 sin1 ag2 sin2 e28 sin3 ak8 slct c17 slin#/astrb# b20 smi_o b21 sout1 af3 sout2 d29 sout3 c11 signal name ball no. stb#/write# a22 stop# g1 sync p30 tck e31 tdi f29 tdn d31 tdo e30 tdp d30 test0 ah3 test1 ag4 test2 aj1 test3 v30 tft_prsnt p29 tftd0 a9, ad4 tftd1 a20, af1 tftd2 d22, ae1 tftd3 b17, ad3 tftd4 d21, u2 tftd5 b21, af2 tftd6 c21, ac3 tftd7 a21, v1 tftd8 d20, ac4 tftd9 c20, ad2 tftd10 c18, y4 tftd11 c19, ad1 tftd12 d10, ab4 tftd13 a18, w3 tftd14 d17, ac2 tftd15 c17, v3 tftd16 b20, ac1 tftd17 a22, v2 tftdck a10, aa1 tftde b18, p2 thrm# ak4 tms f28 trde# d11 trdy# f1 trst# e29 v bat al3 v core (total of 29) d12, n13, n14, n18, n19, p4, p13, p14, p18, p19, p28, t1, t2, t3, t4, t28, t29, t30, t31, u4, u28, v13, v14, v18, v19, w13, w14, w18, w19 signal name ball no. table 3-5. 481-tepbga ball assignment - sorted alphabetically by signal name (continued)
amd geode? sc3200 processor data book 57 signal definitions revision 5.1 v io (total of 46) a2, a12, a30, b2, b13, b16, b19, b31, c3, c7, c10, c13, c22, c25, c29, d14, d15, d18, d23, g3, g29, k2, k29, m3, m30, w1, w31, ab3, ab29, ae3, ae29, ah4, ah14, ah18, aj7, aj10, aj22, aj25, aj29, ak1, ak13, ak16, ak19, ak31, al2, al30 vpckin f31 vpd0 j30 vpd1 j29 vpd2 j28 vpd3 h31 vpd4 h30 vpd5 h29 vpd6 h28 vpd7 g31 v pll2 a17 v pll3 aj4 v sb al5 v sbl al6 signal name ball no. v ss (total of 96) a1, a13, a16, a19, a31, b1, b7, b10, b14, b22, b24, b25, b30, c12, c14, c15, d7, d13, d19, d25, g2, g4, g28, g30, k3, k30, m1, m31, n4, n15, n16, n17, n28, p15, p16, p17, r1, r2, r3, r4, r13, r14, r15, r16, r17, r18, r19, r28, r29, r30, r31, t13, t14, t15, t16, t17, t18, t19, u13, u14, u15, u16, u17, u18, u19, v4, v15, v16, v17, v28, w2, w15, w16, w17, w30, ab2, ab30, ae2, ae4, ae28, ae30, ah7, ah13, ah19, ah25, ak2, ak7, ak10, ak22, ak25, ak30, al1, al13, al16, al19, al31 vsync b11 signal name ball no. wea# ah12 wr# b9 x27i ag3 x27o ah2 x32i aj2 x32o aj3 signal name ball no. table 3-5. 481-tepbga ball assignment - sorted alphabetically by signal name (continued)
58 amd geode? sc3200 processor data book signal definitions revision 5.1 3.2 strap options several balls are read at powe r-up that set up the state of the sc3200. these balls are typically multiplexed with other functions that are outputs after the power-up sequence is complete. the sc 3200 must read the state of the balls at power-up and the internal pu or pd resistors do not guarantee the correct state will be read. therefore, it is required that an external pu or pd resistor with a value of 1.5 k ? be placed on the balls listed in table 3-6. the value of the resistor is import ant to ensure that the proper state is read during the power-up sequence. if the ball is not read correctly at power-up, the sc3200 may default to a state that causes it to func tion improperly, possibly result- ing in application failure. table 3-6. strap options strap option muxed with ball no. nominal internal pu or pd external pu/pd strap settings register references ebga tepbga strap = 0 (pd) strap = 1 (pu) clksel0 rd# f3 b8 pd 100 see table 4-7 on page 101 for clksel strap options. gcb+i/o offset 1eh[9:8] (aka ccfc register bits [9:8]) (ro): value programmed at reset by clksel[1:0]. gcb+i/o offset 10h[3:0] (aka mccm register bits [3:0]) (ro): value programmed at reset by clksel[3:0]. gcb+i/o offset 1eh[3:0] (aka ccfc register bits [3:0]) (r/w, but write not recommended): value programmed at reset by clksel[3:0]. note: values for gcb+i/o off- set 10h[3:0] and 1eh[3:0] are not the same. clksel1 sout1 b27 af3 pd 100 clksel2 sout2 ak3 d29 pd 100 clksel3 sync al13 p30 pd 100 boot16 romcs# g4 c8 pd 100 enable boot from 8-bit rom enable boot from 16-bit rom gcb+i/o offset 34h[3] (aka mcr register bit 3) (ro): reads back strap setting. gcb+i/o offset 34h[14] (r/w): used to allow the romcs# width to be changed under program control. tft_prsnt sdata_ou t ak13 p29 pd 100 tft not muxed onto parallel port tft muxed onto parallel port gcb+i/o offset 30h[23] (aka pmr register bit 23) (r/w): reads back strap setting. lpc_rom pciclk1 e4 d6 pd 100 disable boot from rom on lpc bus enable boot from rom on lpc bus f0bar1+i/o offset 10h[15] (r/ w): reads back strap setting and allows lpc rom to be changed under program control. fpci_mon pciclk0 d3 a4 pd 100 disable fast- pci, intr_o, and smi_o monitoring sig- nals. enable fast- pci, intr_o, and smi_o monitoring sig- nals. (useful during debug.) gcb+i/o offset 34h[30] (aka mcr register bit 30) (ro): reads back strap setting. note: for normal operation, strap this signal low using a 1.5 k ? resistor. did0 gnt0# d4 c5 pd 100 defines the system-level chip id . gcb+i/o offset 34h[31,29] (aka mcr register bits 31 and 29) (ro): reads back strap setting. note: gnt0# must have a pu resistor of 1.5 k ? and gnt1# must have a pu resistor of 1.5 k ? . did1 gnt1# d2 c6 pd 100 note: accuracy of internal pu/pd resistors: 80k to 250k. location of the gcb (general configuration bl ock) cannot be determined by software. see the amd geode? sc3200 speci- fication update document.
amd geode? sc3200 processor data book 59 signal definitions revision 5.1 3.3 multiplexing configuration the tables that follow list multiplexing options and their configurations. certain multiplexing options may be chosen per signal; others are available only for a group of signals. where ever a gpio pin is mu ltiplexed with another func- tion, there is an optional pull-up resistor on this pin; after system reset, the pull-up is present. this pull-up resistor can be disabled by writing core logic registers. the con- figuration is without regard to the selected ball function. the above applies to all pins multiplexed with gpio, except gpio12, gp io13, and gpio16. table 3-7. two-signal/group multiplexing ebga tepbga default alternate signal configuration signal configuration ball no. ide tft, pci, gpio, system a26 ad3 ide_addr0 pmr[24] = 0 tftd3 pmr[24] = 1 c26 ae1 ide_addr1 tftd2 c17 u2 ide_addr2 tftd4 b24 ac3 ide_data0 tftd6 a24 ac1 ide_data1 tftd16 d23 ac2 ide_data2 tftd14 c23 ab4 ide_data3 tftd12 b23 ab1 ide_data4 fp_vdd_on a23 aa4 ide_data5 clk27m c22 aa3 ide_data6 irq9 b22 aa2 ide_data7 intd# a21 y3 ide_data8 gpio40 c20 y2 ide_data9 ddc_sda a20 y1 ide_data10 ddc_scl c19 w4 ide_data11 gpio41 b19 w3 ide_data12 tftd13 a19 v3 ide_data13 tftd15 c18 v2 ide_data14 tftd17 b18 v1 ide_data15 tftd7 c21 y4 ide_ior0# tftd10 a25 ad1 ide_iordy0 tftd11 c24 ac4 ide_dreq0 tftd8 d24 ad2 ide_iow0# tftd9 a27 af2 ide_cs0# tftd5 c16 p2 ide_cs1# tftde c25 ad4 ide_dack0# tftd0 a22 aa1 ide_rst# tftdck d25 af1 irq14 tftd1 ball no. sub-isa gpio h1 d11 trde# pmr[12] = 0 gpio0 pmr[12] = 1
60 amd geode? sc3200 processor data book signal definitions revision 5.1 ball no. gpio access.bus aj12 n29 gpio12 pmr[19] = 0 ab2c pmr[19] = 1 al11 m29 gpio13 ab2d ball no. gpio uart a28 ag1 gpio18 pmr[16] = 0 dtr1#/bout1 pmr[16] = 1 ball no. infrared uart j3 c11 irtx pmr[6] = 0 sout3 pmr[6] = 1 j28 ak8 irrx1 sin3 ball no. gpio lpc aj11 m28 gpio32 pmr[14] = 0 and pmr[22] = 0 lad0 pmr[14] = 1 and pmr[22] = 1 al10 l31 gpio33 lad1 ak10 l30 gpio34 lad2 aj10 l29 gpio35 lad3 al9 l28 gpio36 ldrq# ak9 k31 gpio37 lframe# aj9 k28 gpio38/irrx2 lpcpd# al8 j31 gpio39 serirq ball no. uart internal test aj4 e28 sin2 pmr[28] = 0 sdtest3 pmr[28] = 1 ball no. ac97 fpci monitoring aj15 u29 ac97_rst# fpci_mon = 0 f_stop# fpci_mon = 1 ak14 u31 sdata_in f_gnt0# al14 u30 bit_clk f_trdy# ball no. internal test internal test c28 ag4 pll6b pmr[29] = 0 test1 pmr[29] = 1 b29 aj1 pll5b test2 d28 ah3 pll2b test0 table 3-7. two-signal/group multiplexing (continued) ebga tepbga default alternate signal configuration signal configuration table 3-8. three-signal/group multiplexing ebga tepbga default alternate1 alternate2 signal configuration signal configuration signal configuration ball no. sub-isa sub-isa 1 gpio f1 d9 ior# pmr[21] = 0 and pmr[2] = 0 docr# pmr[21] = 0 and pmr[2] = 1 gpio14 pmr[21] = 1 and pmr[2] = 1 g3 a8 iow# docw# gpio15 ball no. gpio ac97 fpci monitoring
amd geode? sc3200 processor data book 61 signal definitions revision 5.1 al15 v31 gpio16 pmr[0] = 0 and fpci_mon = 0 pc_beep pmr[0] = 1 = 0 and fpci_mon = 0 f_devsel fpci_mon = 1 ball no. gpio pci 2 sub-isa h4 c9 gpio19 pmr[9] = 0 and pmr[4] = 0 intc# pmr[9] = 0 and pmr[4] = 1 iochrdy pmr[9] = 1 and pmr[4] = 1 ball no. parallel port tft 3 fpci monitoring u3 b18 ack# pmr[23] = 0 and (pmr[27] = 0 and fpci_mon = 0) tftde pmr[23] = 1 and (pmr[27] = 0 and fpci_mon = 0) fpci_clk pmr[23] = 0 and (pmr[27] = 1 or fpci_mon = 1) ab2 d22 afd#/dstrb# tftd2 intr_o t1 b17 busy/wait# tftd3 f_c/be1# aa3 d21 err# tftd4 f_c/be0# y3 b21 init# tftd5 smi_o aa1 c21 pd0 tftd6 f_ad0 y1 a21 pd1 tftd7 f_ad1 w3 d20 pd2 tftd8 f_ad2 w2 c20 pd3 tftd9 f_ad3 v1 c18 pd4 tftd10 f_ad4 v2 c19 pd5 tftd11 f_ad5 v3 a20 pd6 tftd1 f_ad6 u1 a18 pd7 tftd13 f_ad7 t3 d17 pe tftd14 f_c/be2# t4 c17 slct tftd15 f_c/be3# w1 b20 slin# /astrb# tftd16 f_irdy ab1 a22 stb#/write# tftd17 f_frame# ball no. gpio sub-isa tft 3 j4 a10 gpio17 pmr[23] = 0 and pmr[5] = 0 iocs0# pmr[23] = 0 and pmr[5] = 1 tftdck pmr[23] = 1 h3 a9 gpio20 pmr[23] = 0 and pmr[7] = 0 doccs# pmr[23] = 0 and pmr[7] = 1 tftd0 pmr[23] = 1 h2 d10 gpio1 pmr[23] = 0 and pmr[13] = 0 iocs1# pmr[23] = 0 and pmr[13] = 1 tftd12 pmr[23] = 1 ball no. ab1 gpio sub-isa aj13 n31 ab1c pmr[23] = 0 gpio20 pmr[23] = 1 and pmr[7] = 0 doccs# pmr[23] = 1 and pmr[7] = 1 al12 n30 ab1d pmr[23] = 0 gpio1 pmr[23] = 1 and pmr[13] = 0 iocs1# pmr[23] = 1 and pmr[13] = 1 ball no. gpio uart2 ide2 h30 aj8 gpio11 pmr[18] = 0 and pmr[8] = 0 ri2# pmr[18] = 1 and pmr[8] = 0 irq15 pmr[18] = 0 and pmr[8] = 1 ball no. internal test internal test tft al16 v30 gxclk pmr[23] = 0 and pmr[29] = 0 test3 pmr[23] = 0 and pmr[29] = 1 fp_vdd_on pmr[23] = 1 1. the combination of pmr[21] = 1 and pmr[2] = 0 is undefined and should not be used. 2. the combination of pmr[9] = 1 and pmr[4] = 0 is undefined and should not be used. 3. these tft outputs are reset to 0 by por# if the tft_prsnt str ap is pulled high or pmr[10] = 0. this relates to signals tftd[1 7:0], tftde, tftdck. table 3-8. three-signal/group multiplexing (continued) ebga tepbga default alternate1 alternate2 signal configuration signal configuration signal configuration
62 amd geode? sc3200 processor data book signal definitions revision 5.1 table 3-9. four-signal/group multiplexing ebga tepbga default alternate1 alternate2 alternate3 signal configuration signal configuration signal configuration signal configuration ball no. gpio uart2 ide2 internal test ah4 c30 gpio7 pmr[17] = 0 and pmr[8] = 0 rts2# pmr[17] = 1 and pmr[8] = 0 ide_dack1# pmr[17] = 0 and pmr[8] = 1 sdtest0 pmr[17] = 1 and pmr[8] = 1 aj2 c31 gpio8 cts2# ide_dreq1 sdtest4 ah3 d28 gpio6 pmr[18] = 0 and pmr[8] = 0 dtr2#/bout2 pmr[18] = 1 and pmr[8] = 0 ide_ior1# pmr[18] = 0 and pmr[8] = 1 sdtest5 pmr[18] = 1 and pmr[8] = 1 ag4 c28 gpio9 dcd2# ide_iow1# sdtest2 aj1 b29 gpio10 dsr2# ide_iordy1 sdtest1
amd geode? sc3200 processor data book 63 signal definitions revision 5.1 3.4 signal descriptions information in the tables that follow may have duplicate inform ation in multiple tables. multiple references all contain identi - cal information. 3.4.1 system interface signal name ball no. type description mux ebga tepbga clksel1 b27 af3 i fast-pci clock selects. these strap signals are used to set the internal fast-pci clock. 00 = 33.3 mhz 01 = 48 mhz 10 = 66.7 mhz 11 = 33.3 mhz during system reset, an internal pull-down resistor of 100 k ? exists on these balls. an external pull-up or pull-down resistor of 1.5 k ? must be used. sout1 clksel0 f3 b8 rd# clksel3 al13 p30 i maximum core cl ock multiplier. these strap signals are used to set the maximum allowed multiplier value for the core clock. during system reset, an internal pull-down resistor of 100 k ? exists on these balls. an external pull-up or pull-down resistor of 1.5 k ? must be used. sync clksel2 ak3 d29 sout2 boot16 g4 c8 i boot rom is 16 bits wide. this strap signal enables the optional 16-bit wide sub-isa bus. during system reset, an internal pull-down resistor of 100 k ? exists on these balls. an external pull-up or pull-down resistor of 1.5 k ? must be used. romcs# lpc_rom e4 d6 i lpc_rom. this strap signal forces selecting of the lpc bus and sets bit f0bar1+i/o off- set 10h[15], lpc rom addressing enable. it enables the sc3200 to boot from a rom connected to the lpc bus. during system reset, an internal pull-down resistor of 100 k ? exists on these balls. an external pull-up or pull-down resistor of 1.5 k ? must be used. pciclk1 tft_prsnt ak13 p29 i tft present. a strap used to select multi- plexing of tft signals at power-up. enables using tft instead of parallel port, acb1, and gpio17. during system reset, an internal pull-down resistor of 100 k ? exists on these balls. an external pull-up or pull-down resistor of 1.5 k ? must be used. sdata_out
64 amd geode? sc3200 processor data book signal definitions revision 5.1 fpci_mon d3 a4 i fast-pci monitoring. the strap on this ball forces selection of fast-pci monitoring sig- nals. for normal operation, strap this signal low using a 1.5 k ? resistor. the value of this strap can be read on the mcr[30]. pciclk0 did1 d2 c6 i device id . together, the straps on these sig- nals define the system-level chip id. the value of did1 can be read in the mcr[29]. the value of did0 can be read in the mcr[31]. did0 and did1 must have a pull-up resistor of 1.5 k ? . gnt1# did0 d4 c5 i gnt0# por# j29 ah9 i power on reset. por# is the system reset signal generated from the power supply to indicate that the syst em should be reset. --- x32i c30 aj2 i/o crystal connections. connected directly to a 32.768 khz crystal. this clock input is required even if the internal rtc is not being used. some of the internal clocks are derived from this clock. if an external clock is used, it should be connected to x32i, using a voltage level of 0 volts to v core +10% maximum. x32o should remain unconnected. --- x32o d29 aj3 --- x27i a29 ag3 i/o crystal connections. connected directly to a 27.000 mhz crystal. some of the internal clocks are derived from this clock. if an exter- nal clock is used, it should be connected to x27i, using a voltage level of 0 volts to v io and x27o should be remain unconnected. --- x27o d27 ah2 --- clk27m a23 aa4 o 27 mhz output clock. output of crystal oscillator. ide_data5 pcirst# d1 a6 o pci and system reset. pcirst# is the reset signal for the pci bus and system. it is asserted for approximately 100 s after por# is negated. --- 3.4.1 system interface (continued) signal name ball no. type description mux ebga tepbga
amd geode? sc3200 processor data book 65 signal definitions revision 5.1 3.4.2 memory interface signals signal name ball no. type description mux ebga tepbga md[63:0] see table 3-3 on page 38. see table 3-5 on page 54. i/o memory data bus. the data bus lines driven to/from system memory. --- ma[12:0] see table 3-3 on page 38. see table 3-5 on page 54. o memory address bus. the multiplexed row/ column address lines driven to the system memory. supports 256-mbit sdram. --- ba1 p31 ak14 o bank address bits. these bits are used to select the component bank within the sdram. --- ba0 p30 aj13 --- cs1# ak29 ah27 o chip selects. these bits are used to select the module bank within system memory. each chip select corre sponds to a specific module bank. if cs# is high, the bank(s) do not respond to ras#, cas#, and we# until the bank is selected again. --- cs0# p29 al12 --- rasa# n31 ak12 o row address strobe. ras#, cas#, we# and cke are encoded to support the different sdram commands. rasa# is used with cs[1:0]#. --- casa# n30 aj12 o column address strobe. ras#, cas#, we# and cke are encoded to support the different sdram commands. casa# is used with cs[1:0]#. --- wea# n29 ah12 o write enable. ras#, cas#, we# and cke are encoded to support the different sdram commands. wea# is used with cs[1:0]#. --- dqm7 aj20 ab31 o data mask control bits. during memory read cycles, these outp uts control whether sdram output buffers are driven on the md bus or not. all dqm signals are asserted dur- ing read cycles. during memory write cycles, these outputs control whether or not md data is written into sdram. dqm[7:0] connect direct ly to the [dqm7:0] pins of each dimm connector. --- dqm6 aj26 ag29 --- dqm5 ac30 ak21 --- dqm4 t28 al15 --- dqm3 aj21 ac31 --- dqm2 al26 ag30 --- dqm1 af31 ah23 --- dqm0 m31 al11 --- ckea ac28 al22 o clock enable. these signals are used to enter suspend/power-down mode. ckea is used with cs[1:0]#. if cke goes low when no read or write cycle is in progress, the sdram enters power- down mode. to ensure that sdram data remains valid, the self-refresh command is executed. to exit this mode, and return to normal operation, drive cke high. these signals should have an external pull- down resistor of 33 k ? . ---
66 amd geode? sc3200 processor data book signal definitions revision 5.1 sdclk3 aj16 v29 o sdram clocks. sdram uses these clocks to sample all control, address, and data lines. to ensure that the suspend mode functions correctly, sdclk3 and sdclk1 should be used with cs1#. sdclk2 and sdclk0 should be used together with cs0#. --- sdclk2 al20 aa28 --- sdclk1 ah16 w29 --- sdclk0 ac29 aj21 --- sdclk_in aj30 aj27 i sdram clock input. the sc3200 samples the memory read data on this clock. works in conjunction with the sdclk_out signal. --- sdclk_out ah28 ak28 o sdram clock output. this output is routed back to sdclk_in. the board designer should vary the length of the board trace to control skew between sdclk_in and sdclk. --- 3.4.2 memory interface signals (continued) signal name ball no. type description mux ebga tepbga 3.4.3 video port interface signals signal name ball no. type description mux ebga tepbga vpd7 aj6 g31 i video port data. the data is input from the ccir-656 video decoder. --- vpd6 aj7 h28 --- vpd5 al6 h29 --- vpd4 ah8 h30 --- vpd3 al7 h31 --- vpd2 aj8 j28 --- vpd1 ak8 j29 --- vpd0 ah9 j30 --- vpckin ah7 f31 i video port clock input. the clock input from the video decoder. ---
amd geode? sc3200 processor data book 67 signal definitions revision 5.1 3.4.4 tft interface signals signal name ball no. type description mux ebga tepbga hsync j1 a11 o horizontal sync --- vsync j2 b11 o vertical sync --- tftdck a22 aa1 o tft clock. ide_rst# j4 a10 gpio17+ iocs0# tftde c16 p2 o tft data enable. ide_cs1# u3 b18 ack#+fpciclk fp_vdd_on b23 ab1 o tft power control. used to enable power to the flat panel display, with power sequence timing. ide_data4 al16 v30 gxclk+test3 tftd[17:0] see table 3-3 on page 38. see table 3-5 on page 54. o digital rgb data to tft. tftd[5:0] - connect to the blue tft inputs. tftd[11:6] - connect to green tft inputs. tftd[17:12] - connect to red tft inputs. the tft interface is muxed with the ide interface or the par- allel port. see table 3-7 on page 59 and table 3-8 on page 60 for details. 3.4.5 access.bus interface signals signal name ball no. type description mux ebga tepbga ab1c aj13 n31 i/o access.bus 1 serial clock. this is the serial clock for the interface. note: if selected as ab1c function but not used, tie ab1c high. gpio20+doccs# ab1d al12 n30 i/o access.bus 1 serial data. this is the bidi- rectional serial data signal for the interface. note: if ab1d function is selected but not used, tie ab1d high. gpio1+iocs1# ab2c aj12 n29 i/o access.bus 2 serial clock. this is the serial clock for the interface. note: if ab2c function is selected but not used, tie ab2c high. gpio12 ab2d al11 m29 i/o access.bus 2 serial data. this is the bidi- rectional serial data signal for the interface. note: if ab2d function is selected but not used, tie ab2d high. gpio13
68 amd geode? sc3200 processor data book signal definitions revision 5.1 3.4.6 pci bus interface signals signal name ball no. type description mux ebga tepbga pciclk e2 a7 i pci clock. pciclk provides timing for all transactions on the pci bus. all other pci signals are sampled on the rising edge of pciclk, and all timing parameters are defined with respect to this edge. --- pciclk0 d3 a4 o pci clock outputs. pciclk0 and pciclk1 provide clock drives for the system at 33 mhz. these clocks are asynchronous to pci signals. there is low skew between all out- puts. one of these clock signals should be connected to the pciclk input. all pci clock users in the system (including pciclk) should receive the clock with as low a skew as possible. fpci_mon (strap) pciclk1 e4 d6 o lpc_rom (strap) ad[31:24] see table 3-3 on page 38. see table 3-5 on page 54. i/o multiplexed address and data. a bus transaction consists of an address phase in the cycle in which frame# is asserted fol- lowed by one or more data phases. during the address phase, ad[31:0] contain a physi- cal 32-bit address. for i/o, this is a byte address. for configuration and memory, it is a dword address. during data phases, ad[7:0] contain the least significant byte (lsb) and ad[31:24] contain the most signifi- cant byte (msb). d[7:0] ad[23:0] a[23:0] c/be3# a8 h4 i/o multiplexed command and byte enables. during the address phase of a transaction when frame# is active, c/be[3:0]# define the bus command. during the data phase, c/ be[3:0]# are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes carry mean- ingful data. c/be0# applies to byte 0 (lsb) and c/be3# applies to byte 3 (msb). d11 c/be2# d8 f3 d10 c/be1# a10 j2 d9 c/be0# a13 l1 d8 inta# ae3 d26 i pci interrupts. the sc3200 provides inputs for the optional ?level -sensitive? pci inter- rupts (also known in industry terms as pirqx#). these interrupts can be mapped to irqs of the internal 8259a interrupt control- lers using pci interrupt steering registers 1 and 2 (f0 index 5ch and 5dh). note: if selected as intc# or intd# func- tion(s) but not used, tie intc# and intd# high. --- intb# af1 c26 --- intc# h4 c9 gpio19+iochrdy intd# b22 aa2 ide_data7
amd geode? sc3200 processor data book 69 signal definitions revision 5.1 par c10 j4 i/o parity. parity generation is required by all pci agents. the master drives par for address- and write-data phases. the target drives par for read-data phases. parity is even across ad[31:0] and c/be[3:0]#. for address phases, par is stable and valid one pci clock after the address phase. it has the same timing as ad[31:0] but is delayed by one pci clock. for data phases, par is stable and valid one pci clock after either irdy# is asserted on a write transaction or after trdy# is asserted on a read transaction. once par is valid, it remains valid until one pci clock after the completion of the data phase. (also see perr#.) d12 frame# e1 d8 i/o frame cycle. frame is driven by the current master to indicate the beginning and duration of an access. frame# is asserted to indi- cate the beginning of a bus transaction. while frame# is asserted, data transfers continue. frame# is de-asserted when the transaction is in the final data phase. this signal is internally connected to a pull- up resistor. --- irdy# c8 f2 i/o initiator ready. irdy# is asserted to indi- cate that the bus master is able to complete the current data phase of the transaction. irdy# is used in conjunction with trdy#. a data phase is completed on any pci clock in which both irdy# and trdy# are sampled as asserted. during a write, irdy# indicates that valid data is present on ad[31:0]. during a read, it indicates that the master is pre- pared to accept data. wait cycles are inserted until both irdy# and trdy# are asserted together. this signal is internally connected to a pull- up resistor. d14 3.4.6 pci bus interface signals (continued) signal name ball no. type description mux ebga tepbga
70 amd geode? sc3200 processor data book signal definitions revision 5.1 trdy# b8 f1 i/o target ready. trdy# is asserted to indi- cate that the target agent is able to complete the current data phase of the transaction. trdy# is used in conjunction with irdy#. a data phase is complete on any pci clock in which both trdy# and irdy# are sampled as asserted. during a read, trdy# indicates that valid data is present on ad[31:0]. during a write, it indicates that the target is prepared to accept da ta. wait cycles are inserted until both irdy# and trdy# are asserted together. this signal is internally connected to a pull- up resistor. d13 stop# d9 g1 i/o target stop. stop# is asserted to indicate that the current target is requesting that the master stop the current transaction. this sig- nal is used with devsel# to indicate retry, disconnect, or target abort. if stop# is sam- pled active by the master, frame# is de- asserted and the cycle is stopped within three pci clock cycles. as an input, stop# can be asserted in the following cases: 1) if a pci master tries to access memory that has been locked by another master. this condition is detected if frame# and lock# are asserted during an address phase. 2) if the pci write buffers are full or if a pre- viously buffered cycle has not com- pleted. 3) on read cycles that cross cache line boundaries. this is conditional based upon the programming of gx1 module?s pci configuration register, index 41h[1]. this signal is internally connected to a pull- up resistor. d15 3.4.6 pci bus interface signals (continued) signal name ball no. type description mux ebga tepbga
amd geode? sc3200 processor data book 71 signal definitions revision 5.1 lock# c9 h3 i/o lock operation. lock# indicates an atomic operation that may require multiple transac- tions to complete. when lock# is asserted, non-exclusive transactions may proceed to an address that is not currently locked (at least 16 bytes must be locked). a grant to start a transaction on pci does not guaran- tee control of lock#. control of lock# is obtained under its own protocol in conjunc- tion with gnt#. it is possible for different agents to use pci while a single master retains ownership of lock#. the arbiter can implement a com- plete system lock. in this mode, if lock# is active, no other master can gain access to the system until the lo ck# is de-asserted. this signal is internally connected to a pull- up resistor. --- devsel# b5 e4 i/o device select. devsel# indicates that the driving device has decoded its address as the target of the current access. as an input, devsel# indicates whether any device on the bus has been selected. devsel# is also driven by any agent that has the ability to accept cycles on a subtractive decode basis. as a master, if no devsel# is detected within and up to the subtractive decode clock, a master abort cycle is initiated (except for special cycles which do not expect a devsel# returned). this signal is internally connected to a pull- up resistor. bhe# perr# b9 h2 i/o parity error. perr# is used for reporting data parity errors during all pci transactions except a special cycle. the perr# line is driven two pci clocks a fter the data in which the error was detected. this is one pci clock after the par that is attached to the data. the minimum duration of perr# is one pci clock for each data phase in which a data parity error is detect ed. perr# must be driven high for one pci clock before being placed in tri-state. a target asserts perr# on write cycles if it has claimed the cycle with devsel#. the master asserts perr# on read cycles. this signal is internally connected to a pull- up resistor. --- 3.4.6 pci bus interface signals (continued) signal name ball no. type description mux ebga tepbga
72 amd geode? sc3200 processor data book signal definitions revision 5.1 serr# a9 h1 i/o system error. serr# can be asserted by any agent for reporting errors other than pci parity. when the pfs bit is enabled in the gx1 module?s pci control function 2 regis- ter (index 41h[5]), serr# is asserted upon assertion of perr#. this signal is internally connected to a pull- up resistor. --- req1# e3 a5 i request lines. req[1:0]# indicate to the arbiter that an agent requires the bus. each master has its own req# line. req# priori- ties (in order) are: 1) vip 2) ide channel 0 3) ide channel 1 4) audio 5) usb 6) external req0# 7) external req1#. each req# is internally connected to a pull- up resistor. --- req0# c1 b5 --- gnt1# d2 c6 o grant lines. gnt[1:0]# indicate to the requesting master that it has been granted access to the bus. each master has its own gnt# line. gnt# can be retracted at any time a higher req# is received or if the mas- ter does not begin a cycle within a minimum period of time (16 pci clocks). each of these signals is internally connected to a pull-up resistor. gnt0# must have a pull-up resistor of 1.5 k ? and gnt1# must have a pull-up resistor of 1.5 k ? . did1 (strap) gnt0# d4 c5 did0 (strap) 3.4.6 pci bus interface signals (continued) signal name ball no. type description mux ebga tepbga
amd geode? sc3200 processor data book 73 signal definitions revision 5.1 3.4.7 sub-isa interface signals signal name ball no. type description mux ebga tepbga a[23:0] see table 3-3 on page 38. see table 3-5 on page 54. o address lines ad[23:0] d15 see table 3-3 on page 38. see table 3-5 on page 54. i/o data bus stop# d14 irdy# d13 trdy# d12 pa r d11 c/be3# d10 c/be2# d9 c/be1# d8 c/be0# d[7:0] ad[31:24] bhe# b5 e4 o byte high enable. with a0, defines byte accessed for 16 bit wide bus cycles. devsel# iocs1# h2 d10 o i/o chip selects gpio1+tftd12 al12 n30 ab1d+gpio1 iocs0# j4 a10 gpio17+tftdck romcs# g4 c30 o rom or flash rom chip select boot16 (strap) doccs# h3 a9 o diskonchip or nand flash chip select gpio20+tftd0 aj13 n31 ab1c+gpio20 trde# h1 d11 o transceiver data enable control. active low for sub-isa data transfers. the signal timing is as follows: in a read cycle, trde# has the same timing as rd#. in a write cycle, trde# is asserted (to active low) at the time wr# is asserted. it continues being asserted for one pci clock cycle after wr# has been negated, then it is negated. gpio0 rd# f3 b8 o memory or i/o read. active on any read cycle. clksel0 (strap) wr# g1 b9 o memory or i/o write. active on any write cycle. --- ior# f1 d9 o i/o read. active on any i/o read cycle. docr#+gpio14 iow# g3 a8 o i/o write. active on any i/o wr ite cycle. docw#+gpio15 docr# f1 d9 o diskonchip or nand flash read. active on any memory read cycle to diskonchip. ior#+gpio14 docw# g3 a8 o diskonchip or nand flash write. active on any memory write cycle to diskonchip. iow#+gpio15
74 amd geode? sc3200 processor data book signal definitions revision 5.1 irq9 c22 aa3 i interrupt 9 request input. active high. note: if irq9 function is selected but not used, tie irq9 low. ide_data6 iochrdy h4 c9 i i/o channel ready note: if iochrdy function is selected but not used, tie iochrdy high. gpio19+intc# 3.4.7 sub-isa interface signals (continued) signal name ball no. type description mux ebga tepbga 3.4.8 low pin count (lpc) bus interface signals signal name ball no. type description mux ebga tepbga lad3 aj10 l29 i/o lpc address-data. multiplexed command, address, bidirectional data, and cycle status. gpio35 lad2 ak10 l30 gpio34 lad1 al10 l31 gpio33 lad0 aj11 m28 gpio32 ldrq# al9 l28 i lpc dma request. encoded dma request for lpc interface. note: if ldrq# function is selected but not used, tie ldrq# high. gpio36 lframe# ak9 k31 o lpc frame. a low pulse indicates the begin- ning of a new lpc cycle or termination of a broken cycle. gpio37 lpcpd# aj9 k28 o lpc power-down. signals the lpc device to prepare for power shut-down on the lpc interface. gpio38/irrx2 serirq al8 j31 i/o serial irq. the interrupt requests are serial- ized over a single signal, where each irq level is delivered during a designated time slot. note: if serirq function is selected but not used, tie serirq high. gpio39
amd geode? sc3200 processor data book 75 signal definitions revision 5.1 3.4.9 ide interface signals signal name ball no. type description mux ebga tepbga ide_rst# a22 aa1 o ide reset. this signal resets all the devices that are attached to the ide interface. tftdck ide_addr2 c17 u2 o ide address bits. these address bits are used to access a register or data port in a device on the ide bus. tftd4 ide_addr1 c26 ae1 tftd2 ide_addr0 a26 ad3 tftd3 ide_data[15:0] see table 3-3 on page 38. see table 3-5 on page 54. i/o ide data lines. ide_data[15:0] transfers data to/from the ide devices. the ide interface is muxed with the tft interface. see table 3-7 on page 59 for details. ide_ior0# c21 y4 o ide i/o read chan nels 0 and 1. ide_ior0# is the read signal for channel 0 and ide_ior1# is the read signal for chan- nel 1. each signal is asserted at read accesses to the corre sponding ide port addresses. tftd10 ide_ior1# ah3 d28 o gpio6+dtr2#/ bout2+sdtest5# ide_iow0# d24 ad2 o ide i/o write channels 0 and 1. ide_iow0# is the write signal for channel 0. ide_iow1# is the write signal for channel 1. each signal is asserted at write accesses to corresponding ide port addresses. tftd9 ide_iow1# ag4 c28 o gpio9+dcd2#+ sdtest2 ide_cs0# a27 af2 o ide chip selects 0 and 1. these signals are used to select the command block registers in an ide device. tftd5 ide_cs1# c16 p2 o tftde ide_iordy0 a25 ad1 i i/o ready channels 0 and 1. when de- asserted, these signals extend the transfer cycle of any host register access if the required device is not ready to respond to the data transfer request. note: if selected as ide_iordy0 or ide_iordy1 function(s) but not used, then signal(s) should be tied high. tftd11 ide_iordy1 aj1 b29 i gpio10+dsr2#+ sdtest1 ide_dreq0 c24 ac4 i dma request channels 0 and 1. the ide_dreq signals are used to request a dma transfer from the sc3200. the direction of transfer is determined by the ide_ior/ iow signals. note: if selected as ide_dreq0/ ide_dreq1 function but not used, tie ide_dreq0/ide_dreq1 low. tftd8 ide_dreq1 aj2 c31 i gpio8+cts2# +sdtest5 ide_dack0# c25 ad4 o dma acknowledge channels 0 and 1. the ide_dack# signals acknowledge the dreq request to initiate dma transfers. tftd0 ide_dack1# ah4 c30 o gpio7+rts2# +sdtest0
76 amd geode? sc3200 processor data book signal definitions revision 5.1 irq14 d25 af1 i interrupt request channels 0 and 1. these input signals are edge-sensitive inter- rupts that indicate wh en the ide device is requesting a cpu interrupt service. note: if selected as irq14/irq15 function but not used, tie irq14/irq15 low. tftd1 irq15 h30 aj8 i gpio11+ri2# 3.4.9 ide interface signals (continued) signal name ball no. type description mux ebga tepbga 3.4.10 universal serial bus (usb) interface signals signal name ball no. type description mux ebga tepbga power_en b28 ah1 o power enable. this signal enables the power to a self-powered usb hub. --- over_cur# c27 af4 i overcurrent. this signal indicates that the usb hub has detected an overcurrent on the usb. --- dpos_port1 ah2 a28 i/o usb port 1 data positive for port 1. 1 --- dneg_port1 ag3 a29 i/o usb port 1 data negative for port 1. 1 --- dpos_port2 ah1 b27 i/o usb port 2 data positive for port 2. 1 --- dneg_port2 ag2 b28 i/o usb port 2 data negative for port 2. 1 --- dpos_port3 ae4 a26 i/o usb port 3 data positive for port 3. 1 --- dneg_port3 af3 a27 i/o usb port 3 data negative for port 3. 1 --- 1. a 15k ohm pull-down resistor is required on all ports (even if unused). 3.4.11 serial ports (uarts) interface signals signal name ball no. type description mux ebga tepbga sin1 d26 ag2 i serial inputs. receive composite serial data from the communications link (peripheral device, modem or other data transfer device). note: if selected as sin2 or sin3 func- tion(s) but not used, then signal(s) should be tied high. --- sin2 aj4 e28 sdtest3 sin3 j28 ak8 irrx1 sout1 b27 af3 o serial outputs. send composite serial data to the communications link (peripheral device, modem or other data transfer device). these signals are set active high after a system reset. clksel1 (strap) sout2 ak3 d29 clksel2 (strap) sout3 j3 c11 irtx
amd geode? sc3200 processor data book 77 signal definitions revision 5.1 rts2# ah4 c30 o request to send. when low, indicates to the modem or other data trans fer device that the corresponding uart is ready to exchange data. a system reset sets these signals to inactive high, and loopback operation holds them inactive. gpio7+ ide_dack1# cts2# aj2 c31 i clear to send. when low, indicates that the modem or other data transfer device is ready to exchange data. note: if selected as cts2# function but not used, tie cts2# low. gpio8+ ide_dreq1 dtr1#/bout1 a28 ag1 o data terminal ready outputs. when low, indicate to the modem or other data transfer device that the uart is ready to establish a communications link. af ter a system reset, these balls provide the dtr# function and set these signals to inactive high. loopback operation drive them inactive. baud outputs. provide the associated serial channel baud rate generator output signal if test mode is selected (i.e., bit 7 of the excr1 register is set). gpio18 dtr2#/bout2 ah3 d28 gpio6+ide_ior1# ri2# h30 aj8 i ring indicator. when low, indicates to the modem that a telephone ring signal has been received by the modem. they are monitored during power-off for wakeup event detection. note: if selected as ri2# function but not used, tie ri2# high. gpio11+irq15 dcd2# ag4 c28 i data carrier detected. when low, indicates that the data transfer device (e.g., modem) is ready to establish a communications link. note: if selected as dcd2# function but not used, tie dcd2# high. gpio9+ide_iow1# +sdtest2 dsr2# aj1 b29 i data set ready. when low, indicates that the data transfer device (e.g., modem) is ready to establish a communications link. note: if selected as dsr2# function but not used, tie dsr2# low. gpio10+ ide_iordy1 3.4.11 serial ports (uarts) interface signals (continued) signal name ball no. type description mux ebga tepbga
78 amd geode? sc3200 processor data book signal definitions revision 5.1 3.4.12 parallel port interface signals signal name ball no. type description mux ebga tepbga ack# u3 b18 i acknowledge. pulsed low by the printer to indicate that it has received data from the par- allel port. tftde+fpciclk afd#/dstrb# ab2 d22 o automatic feed. when low, instructs the printer to automatically feed a line after print- ing each line. this signal is in tri-state after a 0 is loaded into the corresponding control register bit. an external 4.7 k ? pull- up resistor should be attached to this ball. data strobe (epp). active low, used in epp mode to denote a data cycle. when the cycle is aborted, dstrb# becomes inactive (high). tftd2+intr_o busy/wait# t1 b17 i busy. set high by the printer when it cannot accept another character. wait. in epp mode, the parallel port device uses this active low signal to extend its access cycle. tftd3+f_c/be1# err# aa3 d21 i error. set active low by the printer when it detects an error. tftd4+f_c/be0# init# y3 b21 o initialize. when low, initializes the printer. this signal is in tri-state after a 1 is loaded into the corresponding control register bit. use an external 4.7 k ? pull-up resistor. tftd5+smi_o pd7 u1 a18 i/o parallel port data. transfer data to and from the peripheral data bus and the appropriate parallel port data register. these signals have a high current drive capability. tftd13+f_ad7 pd6 v3 a20 tftd1+f_ad6 pd5 v2 c19 tftd11+f_ad5 pd4 v1 c18 tftd10+f_ad4 pd3 w2 c20 tftd9+f_ad3 pd2 w3 d20 tftd8+f_ad2 pd1 y1 a21 tftd7+f_ad1 pd0 aa1 c21 tftd6+f_ad0 pe t3 d17 i paper end. set high by the printer when it is out of paper. this ball has an internal weak pull-up or pull- down resistor that is programmed by soft- ware. tftd14+f_c/be2# slct t4 c17 i select. set active high by the printer when the printer is selected. tftd15+f_c/be3# slin#/astrb# w1 b20 o select input. when low, selects the printer. this signal is in tri-state after a 0 is loaded into the corresponding control register bit. uses an external 4.7 k ? pull-up resistor. address strobe (epp). active low, used in epp mode to denote an address or data cycle. when the cycle is aborted, astrb# becomes inactive (high). tftd16+ f_irdy#
amd geode? sc3200 processor data book 79 signal definitions revision 5.1 stb#/write# ab1 a22 o data strobe. when low, indicates to the printer that valid data is available at the printer port. this signal is in tri-state after a 0 is loaded into the corresponding control register bit. an external 4.7 k ? pull-up resis- tor should be employed. write strobe. active low, used in epp mode to denote an address or data cycle. when the cycle is aborted, write# becomes inac- tive (high). tftd17+ f_frame# 3.4.12 parallel port interface signals (continued) signal name ball no. type description mux ebga tepbga 3.4.13 fast infrared (ir) port interface signals signal name ball no. type description mux ebga tepbga irrx1 j28 ak8 i ir receive . primary input to receive serial data from the ir transceiver. monitored dur- ing power-off for wakeup event detection. note: if selected as irrx1 function but not used, tie irrx1 high. sin3 irrx2/gpio38 aj9 k28 i ir receive 2 . auxiliary ir receiver input to support a second transceiver. this input sig- nal can be used when gpio38 is selected using pmr[14], and when aux_irrx bit in register ircr2 of the ir module in internal superi/o is set. lpcpd# irtx j3 c11 o ir transmit . ir serial output data. sout3
80 amd geode? sc3200 processor data book signal definitions revision 5.1 3.4.14 ac97 audio interface signals signal name ball no. type description mux ebga tepbga bit_clk al14 u30 i audio bit clock. the serial bit clock from the codec. note: if selected as bit_clk function but not used, tie bit_clk low. f_trdy# sdata_out ak13 p29 o serial data output. this output transmits audio serial data to the codec. tft_prsnt (strap) sdata_in ak14 u31 i serial data input. this input receives serial data from the primary codec. note: if selected as sdata_in function but not used, tie sdata_in low. f_gnt0# sdata_in2 h31 al8 i serial data input 2. this input receives serial data from the secondary codec. this signal has wakeup capability. --- sync al13 p30 o serial bus synchronization. this bit is asserted to synchronize the transfer of data between the sc3200 and the ac97 codec. clksel3 (strap) ac97_clk aj14 p31 o codec clock. it is twice the frequency of the audio bit clock. --- ac97_rst# aj15 u29 o codec reset. s3 to s5 wakeup is not sup- ported because ac97_rst# is powered by v io . if wakeup from states s3 to s5 are needed, a circuit in the system board should be used to reset the ac97 codec. f_stop# pc_beep al15 v31 o pc beep. legacy pc/at speaker output. gpio16+ f_devsel# 3.4.15 power management interface signals signal name ball no. type description mux ebga tepbga clk32 h29 ah8 o 32.768 khz output clock --- gpwio0 e31 ah6 i/o general purpose wakeup i/os. these sig- nals each have an internal pull-up of 100 k ? . --- gpwio1 g28 ak5 --- gpwio2 g29 aj6 --- led# d31 al4 o led control. drives an externally connected led (on, off or a 1 hz blink). sleeping / working indicator. this signal is an open- drain output. --- onctl# e30 aj5 o on / off control. this signal indicates to the main power supply that power should be turned on. this signal is an open-drain out- put. ---
amd geode? sc3200 processor data book 81 signal definitions revision 5.1 pwrbtn# e29 ah5 i power button. input used by the power management logic to monitor external sys- tem events, most typi cally a system on/off button or switch. the signal has an internal pull-up of 100 k ? , a schmitt-trigger input buffer and debounce protection of at least 16 ms. acpi is non-functional and all acpi outputs are undefined when the power-up sequence does not include using the power button. susp# is an internal signal generated from the acpi block. without an acpi reset, susp# can be permanently asserted. if the use_susp bit in ccr2 of gx1 module is enabled (index c2h[7] = 1), the cpu will stop. if acpi functionality is desired, or the situa- tion described above avoided, the power but- ton must be toggled. this can be done externally or internally . gpio63 is internally connected to pwrbtn#. to toggle the power button with software, gpio63 must be programmed as an output using the normal gpio programming protocol (see section 6.4.1.1 "gpio support registers" on page 240). gpio63 must be pulsed low for at least 16 ms and not more than 4 sec. asserting por# has no effect on acpi. if por# is asserted and acpi was active prior to por#, then acpi will remain active after por#. therefore, bios must ensure that acpi is inactive before gpio63 is pulsed low. --- pwrcnt1 f31 ak6 o suspend power plane control 1 and 2. control signal asserted during power man- agement suspend states. these signals are open-drain outputs. --- pwrcnt2 g31 al7 o --- thrm# f28 ak4 i thermal event. active low signal generated by external hardware indicating that the sys- tem temperature is too high. --- 3.4.15 power management interface signals (continued) signal name ball no. type description mux ebga tepbga
82 amd geode? sc3200 processor data book signal definitions revision 5.1 3.4.16 gpio interface signals signal name ball no. type description mux ebga tepbga gpio0 h1 d11 i/o gpio port 0. each signal is configured inde- pendently as an input or i/o, with or without static pull-up, and with either open-drain or totem-pole output type. a debouncer and an interrupt can be enabled or masked for each of signals gpio[00:01] and [06:15] independently. note: gpio12, gpio13, gpio16 inputs: if gpiox function is selected but not used, tie gpiox low. trde# gpio1 h2 d10 iocs1#+tftd12 al12 n30 ab1d+iocs1# gpio6 ah3 d28 dtr2#/bout2+ ide_ior1#+ sdtest5 gpio7 ah4 c30 rts2#+ide_dack1# +sdtest0 gpio8 aj2 c31 cts2#+ide_dreq1 +sdtest4 gpio9 ag4 c28 dcd2#+ide_iow1#+ sdtest2 gpio10 aj1 b29 dsr2#+ide_iordy1 +sdtest1 gpio11 h30 aj8 ri2#+irq15 gpio12 aj12 n29 ab2c gpio13 al11 m29 ab2d gpio14 f1 d9 ior#+docr# gpio15 g3 a8 iow#+docw# gpio16 al15 v31 pc_beep+ f_devsel# gpio17 j4 a10 iocs0#+tftdck gpio18 a28 ag1 dtr1#/bout1 gpio19 h4 c9 intc#+iochrdy gpio20 h3 a9 doccs#+tftd0 aj13 n31 ab1c+doccs# gpio32 aj11 m28 i/o gpio port 1. each signal is configured inde- pendently as an input or i/o, with or without static pull-up, and with either open-drain or totem-pole output type. a debouncer and an interrupt can be enabled or masked for each of signals gpio[32:41] independently. lad0 gpio33 al10 l31 lad1 gpio34 ak10 l30 lad2 gpio35 aj10 l29 lad3 gpio36 al9 l28 ldrq# gpio37 ak9 k31 lframe# gpio38/irrx2 aj9 k28 lpcpd# gpio39 al8 j31 serirq gpio40 a21 y3 ide_data8 gpio41 c19 w4 ide_data11
amd geode? sc3200 processor data book 83 signal definitions revision 5.1 3.4.17 debug monitoring interface signals signal name ball no. type description mux ebga tepbga fpciclk u3 b18 o fast-pci bus monitoring signals. when enabled, this group of signals provides for monitoring of the internal fast-pci bus for debug purposes. to enable, pull up fpci_mon (ebga ball d3 / tepbga ball a4). ack#+tftde f_ad7 u1 a18 o pd7+tftd13 f_ad6 v3 a20 o pd6+tftd1 f_ad5 v2 c19 o pd5+tftd11 f_ad4 v1 c18 o pd4+tftd10 f_ad3 w2 c20 o pd3+tftd9 f_ad2 w3 d20 o pd2+tftd8 f_ad1 y1 a21 o pd1+tftd7 f_ad0 aa1 c21 o pd0+tftd6 f_c/be3# t4 c17 o slct+tftd15 f_c/be2# t3 d17 o pe+tftd14 f_c/be1# t1 b17 o busy/wait#+ tftd3 f_c/be0# aa3 d21 o err#+tftd4+ f_frame# ab1 a22 o stb#/write#+ tftd17 f_irdy# w1 b20 o slin#/astrb#+ tftd16 f_stop# aj15 u29 o ac97_rst# f_devsel# al15 v31 o gpio16+ pc_beep f_gnt0# ak14 u31 o sdata_in f_trdy# al14 u30 o bit_clk intr_o ab2 d22 o cpu core interrupt. when enabled, this sig- nal provides for monitoring of the internal gx1 core intr signal for debug purposes. to enable, pull up fpci_mon (ebga ball d3 / tepbga ball a4). afd#/dstrb#+ tftd2 smi_o y3 b21 o system management interrupt. this is the input to the gx1 core. when enabled, this signal provides for monitoring of the internal gx1 core smi# signal for debug purposes. to enable, pull up fpci_mon (ebga ball d3 / tepbga ball a4). init#+tftd5+
84 amd geode? sc3200 processor data book signal definitions revision 5.1 3.4.18 jtag interface signals signal name ball no. type description mux ebga tepbga tck al4 e31 i jtag test clock. this signal has an inter- nal weak pull-up resistor. --- tdi ak5 f29 i jtag test data input. this signal has an internal weak pull-up resistor. --- tdo ah6 e30 o jtag test data output --- tms aj5 f28 i jtag test mode select. this signal has an internal weak pull-up resistor. --- trst# ak4 e29 i jtag test reset. this signal has an inter- nal weak pull-up resistor. for normal jtag operation, this signal should be active at power-up. if the jtag interface is not being used, this signal can be tied low. --- 3.4.19 test and measurement interface signals signal name ball no. type description mux ebga tepbga gxclk al16 v30 o gx clock. this signal is for internal testing only. for normal operation either program as fp_vdd_on or leave unconnected. fp_vdd_on+ test3 test3 al16 v30 o internal test signal. this signal is used for internal testing only. for normal operation leave unconnected, unless programmed as fp_vdd_on. fp_vdd_on+ gxclk test2 b29 aj1 o internal test signals. these signals are used for internal testing only. for normal operation, leave unconnected unless pro- grammed as one of their muxed options. pll5b test1 c28 ag4 o pll6b test0 d28 ah3 o pll2b gtest al5 f30 i global test. this signal is used for internal testing only. for normal operation this signal should be pulled down with 1.5 k ? . --- pll6b c28 ag4 i/o pll6, pll5 and pll2 bypass. these sig- nals are used for internal testing only. for normal operation leave unconnected. test1 pll5b b29 aj1 i/o test2 pll2b d28 ah3 i/o test0
amd geode? sc3200 processor data book 85 signal definitions revision 5.1 sdtest5 ah3 d28 o memory internal test signals. these sig- nals are used for internal testing only. for normal operation, these signals should be programmed as one of their muxed options. gpio6+ dtr2#/bout2+ ide_ior1# sdtest4 aj2 c31 o gpio8+cts2#+ ide_dreq1 sdtest3 aj4 e28 o sin2 sdtest2 ag4 c28 o gpio9+dcd2#+ ide_iow1# sdtest1 aj1 b29 o gpio10+dsr2# +ide_iordy1 sdtest0 ah4 c30 o gpio7+rts2#+ ide_dack1# tdp ah5 d30 i/o thermal diode po sitive / negative . these signals are for internal testing only. for nor- mal operation leave unconnected. --- tdn al3 d31 i/o --- 3.4.19 test and measurement interface signals (continued) signal name ball no. type description mux ebga tepbga
86 amd geode? sc3200 processor data book signal definitions revision 5.1 3.4.20 power, ground and no connections 1 signal name ball no. type description ebga tepbga av sspll2 r3 c16 gnd analog pll2 ground connection. av sspll3 e28 ak3 gnd analog pll3 ground connection. v pll2 r1 a17 pwr 3.3v pll2 analog power connection. low noise power for pll2 and pll5. v pll3 c31 aj4 pwr 3.3v pll3 analog power connection. low noise power for pll3, pll4, and pll6. av ccusb af4 d27 pwr 3.3v analog usb power connection. low noise power. av ssusb ag1 c27 gnd analog usb ground connection. v bat d30 al3 pwr battery. provides battery back-up to the rtc and acpi registers, when v sb is lower than the minimum value (see table 9-3 on page 370). the ball is con- nected to the internal logic through a series resistor for ul protection. if battery backup is not desired, connect v bat to v ss . v sb f29 al5 pwr 3.3v standby power supply. provides power to the real-time clock (rtc) and acpi circuitry while the main power supply is turned off. v sbl h28 al6 pwr 1.8v standby power supply. provides power to the internal logic while the main power supply is turned off. this signal requires a 0.1 f bypass capacitor to v ss . this supply must be present when v sb is present. v core seetable 3-3 on page 38. (total of 26) see table 3-5 on page 54. (total of 29) pwr 1.8v core processor power connections. v io see table 3-3 on page 38. (total of 35) see table 3-5 on page 54. (total of 46) pwr 3.3v i/o power connections. v ss see table 3-3 on page 38. (total of 61) see table 3-5 on page 54. (total of 96) gnd ground connections. nc see table 3-3 on page 38. (total of 13) see table 3-5 on page 54. (total of 13) --- no connections. these lines should be left discon- nected. connecting a pull-up/-d own resistor or to an active signal could cause unexpected results and pos- sible malfunctions. 1. all power sources except v bat must be connected, even if the function is not used.
amd geode? sc3200 processor data book 87 4 general configuration block revision 5.1 4.0 general configuration block the general configuration block includes registers for: pin multiplexing and miscellaneous configuration watchdog timer high-resolution timer clock generators a selectable interrupt is shared by all these functions. 4.1 configuration block addresses registers of the general configuration block are i/o mapped in a 64-byte address range. these registers are physically connected to the internal fast-pci bus, but do not have a register block in pci configuration space (i.e., they do not appear to software as pci registers). after system reset, the base ad dress register is located at i/o address 02eah. this address can be used only once. before accessing any pci registers, the boot code must program this 16-bit register to the i/o base address for the general configuration block registers. all subsequent writes to this address, ar e ignored until system reset. note: location of the general configuration block can- not be determined by software. see the amd geode? sc3200 specification update document. reserved bits in the general configuration block should read as written unless otherwise specified. table 4-1. general configuration block register summary offset width (bits) type name reset value reference 00h-01h 16 r/w wdto. watchdog timeout 0000h page 96 02h-03h 16 r/w wdcnfg. watchdog configuration 0000h page 96 04h 8 r/wc wdsts. watchdog status 00h page 97 05h-07h --- --- rsvd. reserved --- --- 08h-0bh 32 ro tmvalue. timer value xxxxxxxxh page 98 0ch 8 r/w tmsts. timer status 00h page 98 0dh 8 r/w tmcnfg. timer configuration 00h page 98 0eh-0fh --- --- rsvd. reserved --- --- 10h 8 ro mccm. maximum core clock multiplier strapped value page 103 11h --- --- rsvd. reserved --- --- 12h 8 r/w ppcr. pll power control 2fh page 103 13h-17h --- --- rsvd. reserved --- --- 18h-1bh 32 r/w pll3c. pll3 configuration e1040005h page 103 1ch-1dh --- --- rsvd. reserved --- --- 1eh-1fh 16 r/w ccfc. core clock frequency control strapped value page 104 20h-2fh --- --- rsvd. reserved --- --- 30h-33h 32 r/w pmr. pin multiplexing register 00000000h page 88 34h-37h 32 r/w mcr. miscellaneous configuration register 00000001h page 92 38h 8 r/w intsel. interrupt selection 00h page 94 39h-3bh --- --- rsvd. reserved --- --- 3ch 8 ro id. device id xxh page 94 3dh 8 ro rev. revision xxh page 94 3eh-3fh 16 ro cba. configuration base address xxxxh page 94
88 amd geode? sc3200 processor data book general configuration block revision 5.1 4.2 multiplexing, inte rrupt selection, and base address registers the registers described intable 4-2 are used to determine general configuration for the sc3200. these registers also indicate which multiplexed signals are issued via balls from which more than one signal ma y be output. for more infor- mation about multiplexed signals and the appropriate con- figurations, see section 3.1 "ball assignments" on page 27. table 4-2. multiplexing, interrupt selection, and base address registers bit description offset 30h-33h pin multiplexing re gister - pmr (r/w) reset value: 00000000h this register configures pins with multiple functions. see section 3.1 on page 27 for more information about multiplexing infor mation. 31:30 reserved: always write 0. 29 test signals. selects ball functions. ball # 0: internal test signals 1: internal test signals ebga / tepbga name add?l dependencies name add?l dependencies d28 / ah3 pll2b none test0 none c28 / ag4 pll6b none test1 none b29 / aj1 pll5b none test2 none al16 / v30 gxclk see pmr[23] test3 pmr[23] = 0 28 test signals. selects ball function. ball # 0: ac97 signal 1: internal test signal ebga / tepbga name add?l dependencies name add?l dependencies aj4 / e28 sin2 none sdtest3 see note. note: if this bit is set, pmr[8] and pmr[18] must be set by software. 27 fpci_mon (fast-pci monitoring). selects fast-pci monitoring output signals instead of parallel port signals. fast-pci monitoring output signals can be enabled in two ways : by setting this bit to 1 or by strapping fpci_mon (ebga ball d3 / tepbga ball a4) high. (the strapped value can be r ead back at mcr[30].) listed below is how these two options work together and the signals that are enabled (enabling over rides add?l dependencies except fpci_mon = 1). note that the fpci monitoring signals that are muxed with audio signals are not enabled via this bit. th ey are only enabled using the strap option. pmr[27] fpci_mon 0 0 disable all fast-pci monitoring signals 0 1 enable all fast-pci monitoring signals 1 0 enable fast-pci monitoring signals muxed with parallel port signals only 1 1 enable all fast-pci monitoring signals ball # ebga / tepbga fpci_mon signal other signal add?l dependencies u3 / b18 fpciclk ack#+tftde see pmr[23] u1 / a18 f_ad7 pd7+tftd13 see pmr[23] v3 / a20 f_ad6 pd6+tftd1 see pmr[23] v2 / c19 f_ad5 pd5+tft11 see pmr[23] v1 / c18 f_ad4 pd4+tftd10 see pmr[23] w2 / c20 f_ad3 pd3+tftd9 see pmr[23] w3 / d20 f_ad2 pd2+tftd8 see pmr[23] y1 / a21 f_ad1 pd1+tftd7 see pmr[23] aa1 / c21 f_ad0 pd0_tftd5 see pmr[23] t4 / c17 f_c/be3# slct+tftd15 see pmr[23] t3 / d17 f_c/be2# pe+tftd14 see pmr[23] t1 / b17 f_c/be1# busy/wait#+tftd3 see pmr[23] aa3 / d21 f_c/be0# err#+tftd4 see pmr[23] ab1 / a22 f_frame# stb#/write#+tftd7 see pmr[23] w1 / b20 f_irdy# slin#/astrb#+tftd16 see pmr[23] ab2 / d22 intr_o afd#/dstrb#+tftd2 see pmr[23] y3 / b21 smi_o init#+tftd5 see pmr[23] al15 / v31 f_devsel# gpio16+pc_beep fpci_mon = 1 and see pmr[0] aj15 / u29 f_stop# ac97_rst# fpci_mon = 1 ak14 / u31 f_gnt0# sdata_in fpci_mon = 1 al14 / u30 f_trdy# bit_clk fpci_mon = 1
amd geode? sc3200 processor data book 89 general configuration block revision 5.1 26 reserved. always write 0. 25 ac97cken (enable ac97_clk output). this bit enables the output drive of ac97_clk (ebga ball aj14 / tepbga ball p31). 0: ac97_clk output is hiz. 1: ac97_clk output is enabled. 24 tftide (tft/ide). determines whether certain ball s are used for tft signals or for id e signals. note that there are no additional dependencies. ball # 0: ide signals 1: gpio and tft signals ebga / tepbga name name a26 / ad3 ide_addr0 tftd3 c26 / ae1 ide_addr1 tftd2 c17 / u2 ide_addr2 tftd4 b24 / ac3 ide_data0 tftd6 a24 / ac1 ide_data1 tftd16 d23 / ac2 ide_data2 tftd14 c23 / ab4 ide_data3 tftd12 b23 / ab1 ide_data4 fp_vdd_on a23 / aa4 ide_data5 clk27m c22 / aa3 ide_data6 irq9 b22 / aa2 ide_data7 intd# a21 / y3 ide_data8 gpio40 c20 / y2 ide_data9 ddc_sda a20 / y1 ide_data10 ddc_scl c19 / w4 ide_data11 gpio41 b19 / w3 ide_data12 tftd13 a19 / v3 ide_data13 tftd15 c18 / v2 ide_data14 tftd17 b18 / v1 ide_data15 tftd7 a27 / af2 ide_cs0# tftd5 c16 / p2 ide_cs1# tftde c21 / y4 ide_ior0# tftd10 d24 / ad2 ide_iow0# tftd9 c24 / ac4 ide_dreq0 tftd8 c25 / ad4 ide_dack0# tftd0 a22 / aa1 ide_rst# tftdck a25 / ad1 ide_iordy0 tftd11 d25 / af1 irq14 tftd1 table 4-2. multiplexing, interrupt selecti on, and base address registers (continued) bit description
90 amd geode? sc3200 processor data book general configuration block revision 5.1 23 tftpp (tft/parallel port). determines whether certain balls are used for tft or pp/acb1/fpci. this bit is set to 1 at power-on if the tft_prsnt strap (ebga ball ak13 / tepbga ball p29) is pulled high. ball # 0: pp/acb1/fpci 1: tft ebga / tepbga name add?l dependencies name add?l dependencies h2 / d10 gpio1 pmr[13] = 0 tftd12 none iocs1# pmr[13] = 1 h3 / a9 gpio20 pmr[7] = 0 tftd0 none doccs# pmr[7] = 1 j4 / a10 gpio17 pmr[5] = 0 tftdck none iocs0# pmr[5] = 1 t1 / b17 busy/wait# note 1 tftd3 none f_c/be1# note 2 t3 / d17 pe note 1 tftd14 note 1 f_c/be2# note 2 t4 / c17 slct note 1 tftd15 note 1 f_c/be3# note 2 u1 / a18 pd7 note 1 tftd13 note 1 f_ad7 note 2 u3 / b18 ack# note 1 tftde note 1 fpciclk note 2 v1 / c18 pd4 note 1 tftd10 note 1 f_ad4 note 2 v2 / c19 pd5 note 1 tftd11 note 1 f_ad5 note 2 v3 / a20 pd6 note 1 tftd1 note 1 f_ad6 note 2 w1 / b20 slin#/astrb# note 1 tftd16 note 1 f_irdy# note 2 w2 / c20 pd3 note 1 tftd9 note 1 f_ad3 note 2 w3 / d20 pd2 note 1 tftd8 note 1 f_ad2 note 2 y1 / a21 pd1 note 1 tftd7 note 1 f_ad1 note 2 y3 / b21 init# note 1 tftd5 note 1 smi_o note 2 aa1 / c21 pd0 note 1 tftd6 note 1 f_ad0 note 2 aa3 / d21 err# note 1 tftd4 note 1 f_c/be0# note 2 ab1 / a22 stb#/write# note 1 tftd17 none f_frame# note 2 ab2 / d22 afd#/dstrb# note 1 tftd2 note 1 intr_o note 2 aj13 / n31 ab1c none gpio20 pmr[7] = 0 doccs# pmr[7] = 1 al12 / n30 ab1d none gpio1 pmr[13] = 0 iocs1# pmr[13] = 1 al16 / v30 gxclk pmr[29] = 0 fp_vdd_on none test3 pmr[29] = 1 note: 1. pmr[27] = 0 and fpci_mon = 0 2. pmr[27] = 1 or fpci_mon = 1 3. access.bus interface 1 is not available if pmr[23] = 1. 4. if fpci_mon strap is enabled, the tft_prsnt strap should pulled low. 22 rsvd (reserved). must be set equal to pmr[14] (lpcsel). the lpc_rom strap (ebga ball e4 / tepbga ball d6) deter- mines the power-on reset (por) state of pmr[14] and pmr[22]. table 4-2. multiplexing, interrupt selecti on, and base address registers (continued) bit description
amd geode? sc3200 processor data book 91 general configuration block revision 5.1 21 iocsel (select i/o commands ) . selects ball functions. ball # 0: i/o command signals 1: gpio signals ebga / tepbga name add?l dependencies name add?l dependencies f1 / d9 ior# pmr[2] = 0 gpio14 pmr[2] = 1 docr# pmr[2] = 1 undefined pmr[2] = 0 g3 / a8 iow# pmr[2] = 0 gpio15 pmr[2] = 1 docw# pmr[2] = 1 undefined pmr[2] = 0 20 reserved. must be set to 0. 19 ab2sel (select access.bus 2). selects ball functions. ball # 0: gpio signals 1: access.bus 2 signals ebga / tepbga name add?l dependencies name add?l dependencies aj12 / n29 gpio12 none ab2c none al11 / m29 gpio13 none ab2d none 18 sp2sel (select sp2 additional pins). selects ball functions. ball # 0: gpio, ide signals 1: serial port signals ebga / tepbga name add?l dependencies name add?l dependencies ah3 / d28 gpio6 pmr[8] = 0 dtr2#/bout2 pmr[8] = 0 ide_ior1# pmr[8] = 1 sdtest5 pmr[8] = 1 ag4 / c28 gpio9 pmr[8] = 0 dcd2# pmr[8] = 0 ide_iow1# pmr[8] = 1 sdtest2 pmr[8] = 1 aj1 / b29 gpio10 pmr[8] = 0 dsr2# pmr[8] = 0 ide_iordy1 pmr[8] = 1 sdtest1 pmr[8] = 1 h30 / aj8 gpio11 pmr[8] = 0 ri2# pmr[8] = 0 irq15 pmr[8] = 1 undefined pmr[8] = 1 17 sp2crsel (select sp2 flow control). selects ball functions. ball # 0: gpio, ide signals 1: serial port signals ebga / tepbga name add?l dependencies name add?l dependencies ah4 / c30 gpio7 pmr[8] = 0 rts2# pmr[8] = 0 ide_dack1# pmr[8] = 1 sdtest0 pmr[8] = 1 aj2 / c31 gpio8 pmr[8] = 0 cts2# pmr[8] = 0 ide_dreq1 pmr[8] = 1 sdtest4 pmr[8] = 1 16 sp1sel (select sp1 additional pin) . selects ball function. ball # 0: gpio signal 1: serial port signal ebga / tepbga name add?l dependencies name add?l dependencies a28 / ag1 gpio18 none dtr1#/bout1 none 15 rsvd (reserved). write to 0. 14 lpcsel (select lpc bus). selects ball functions. the lpc_rom strap (ebga ball e4 / tepbga ball d6) determines the power-on reset (por) state of pmr[14] and pmr[22]. ball # 0: gpio signals 1: lpc signals ebga / tepbga name add?l dependencies name add?l dependencies aj11 / m28 gpio32 pmr[22] = 0 lad0 pmr[22] = 1 al10 / l31 gpio33 pmr[22] = 0 lad1 pmr[22] = 1 ak10 / l30 gpio34 pmr[22] = 0 lad2 pmr[22] = 1 aj10 / l29 gpio35 pmr[22] = 0 lad3 pmr[22] = 1 al9 / l28 gpio36 pmr[22] = 0 ldrq# pmr[22] = 1 ak9 / k31 gpio37 pmr[22] = 0 lframe# pmr[22] = 1 aj9 / k28 gpio38/irrx2 pmr[22] = 0 lpcpd# pmr[22] = 1 al8 / j31 gpio39 pmr[22] = 0 serirq pmr[22] = 1 13 iocs1sel (select iocs1). selects ball functions for iocs1# or gpio1. works in conjunction with pmr[23], see pmr[23] for definition. table 4-2. multiplexing, interrupt selecti on, and base address registers (continued) bit description
92 amd geode? sc3200 processor data book general configuration block revision 5.1 12 trdesel (select trde#). selects ball function. ball # 0: sub-isa signal 1: gpio signal ebga / tepbga name add?l dependencies name add?l dependencies h1 / d11 trde# none gpio0 none 11 eide (enable ide outputs). this bit enables ide output signals. 0: ide signals are hiz. other signal s multiplexed on the same balls are hiz until this bit is set. (without regard to bit 24 of this register). this bit does not control ide channel 1 control signals selected by bit 8 of this register. 1: signals are enabled. 10 etft (enable tft outputs). this bit enables tft output signals, that are multiplexed with the parallel port and controlled by pmr[23]. 0: signals tftd[17:0], tftde and tftdck are set to 0. 1: signals tftd[17:0], tftde and tftdck are enabled. note: tftdck that is multiplexed on ide_rst# (ebga ball a22 / tepbga ball aa1) is also enabled by this bit. 9 iochrdy (select iochrdy). selects ball function. ball # 0: pci, gpio signal 1: sub-isa signal ebga / tepbga name add?l dependencies name add?l dependencies h4 / c9 gpio19 pmr[4] = 0 iochrdy pmr[4] = 1 intc# pmr[4] = 1 undefined pmr[4] = 0 8 ide1sel (select ide channel 1). selects ide channel 1 or gpio ball functi ons. works in conjunction with pmr[18] and pmr[17], see pmr[18] and pmr[17] for definitions. 7 doccssel (select doccs#). selects doccs# or gpio20 ball functions. works in conjunction with pmr[23], see pmr[23] for definition. 6 sp3sel (select uart3). selects ball functions. ball # 0: ir signals 1: serial port signals ebga / tepbga name add?l dependencies name add?l dependencies j28 / ak8 irrx1 none sin3 none j3 / c11 irtx none sout3 none 5 iocs0sel (select iocs0#). selects ball function. works in conjunction with pmr[23], see pmr[23] for definition. 4 intcsel (select intc#). selects ball function. works in conjunction with pmr[9], see pmr[9] for definition. 3 reserved. write as read. 2 docwrsel (select diskonchip and nand flash command lines ) . selects ball functions. works in conjunction with pmr[21], see pmr[21] for definition. 1 reserved. write as read. 0 pcbeepsel (select pc_beep) . selects ball function. ball # 0: gpio signal 1: audio signal ebga / tepbga name add?l dependencies name add?l dependencies al15 / v31 gpio16 fpci_mon = 0 pc_beep fpci_mon] = 0 f_devsel# fpci_mon = 1 f_devsel# fpci_mon = 1 offset 34h-37h miscellaneous configuratio n register - mcr (r/w) reset value: 0000001h power-on reset value: the boot16 strap pin selects "enable 16-bit wide boot memory". 31 did0 (ebga ball d4 / tepbga ball c5) strap status. (read only) represents the value of the strap that is latched after power-on reset. read in conjunction with bit 29. 30 fpci_mon (ebga ball d3 / tepbga ball a4) strap status. (read only) represents the value of the strap that is latched after power-on reset. indicates if fast-pci monitoring output signals (instead of parallel port and some audio sig- nals) are enabled. the state of this bit along with pmr[27] c ontrol the fast-pci monitoring function. see pmr[27] definition. 29 did1 (ebga ball d2 / tepbga ball c6) strap status. (read only) represents the value of the strap that is latched after power-on reset. read in conjunction with bit 31. 28:20 reserved. 19:18 reserved. write as 0. 17 hsync timing. hsync timing control for tft. 0: reserved. 1: hsync timing suited for tft. table 4-2. multiplexing, interrupt selecti on, and base address registers (continued) bit description
amd geode? sc3200 processor data book 93 general configuration block revision 5.1 16 delay hsync. hsync delay by two tft clock cycles. 0: there is no delay on hsync. 1: hysnc is delayed twice by rising edge of tft clock. enables delay between vsync and hsync suited for tft dis- play. 15 reserved. write as read. 14 ibus16 (invert bus16). this bit inverts the meaning of mc r[3] (bit 3 of this register). 0 : bus16 is as described for mcr[3]. 1: bus16 meaning is inverted: if mcr[3] = 0, romcs# access is 16 bits wide; if mcr[3] = 1, romcs# access is 8 bits wide. 13 reserved. must be set to 0. 12 io1zws (enable zws# for iocs1# access). this bit enables internal activation of zws# (zero wait states) control for iocs1# access. 0: zws# is not active for iocs1# access. 1: zws# is active for iocs1# access. 11 io0zws (enable zws# for iocs0# access). this bit enables internal activation of zws# (zero wait states) control for iocs0# access. 0: zws# is not active for iocs0# access. 1: zws# is active for iocs0# access. 10 doczws (enable zws# for doccs# access). this bit enables internal activation of zws# (zero wait states) control for doccs# access. 0: zws# is not active for doccs# access. 1: zws# is active for doccs# access. 9 romzws (enable zws# for romcs# access). this bit enables internal activation of zws# (zero wait states) control for romcs# access. 0: zws# is not active for romcs# access. 1: zws# is active for romcs# access. 8 io1_16 (enable 16-bit wide iocs1# access). this bit enables the16-line access to iocs1# in the sub-isa interface. 0: 8-bit wide iocs1# access is used. 1: 16-bit wide iocs1# access is used. 7 io0_16 (enable 16-bit wide iocs0# access). this bit enables the 16-line access to iocs0# in the sub-isa interface. 0: 8-bit wide iocs0# access is used. 1: 16-bit wide iocs0# access is used. 6 doc16 (enable 16-bit wide doccs# access). this bit enables the 16-line access to doccs# in the sub-isa interface. 0: 8-bit wide doccs# access is used. 1: 16-bit wide doccs# access is used. 5 reserved. write as read. 4 irtxen (infrared transmitter enable). this bit enables drive of infrared transmitter output. 0: irtx+sout3 line (ebga ball j3 / tepbga ball c11) is hiz. 1: irtx+sout3 line (ebga ball j3 / tepbga ball c11) is enabled. 3 bus16 (16-bit wide boot memory). (read only) this bit reports the status of t he boot16 strap (ebga ball g4 / tep- bga ball c8). if the boot16 strap is pulled high, at reset 16 -bit access to rom in the sub-isa interface is enabled. mcr[14] = 1 inverts the meaning of this register. 0 : 8-bit wide rom. 1: 16-bit wide rom. 2:1 reserved. write as read. table 4-2. multiplexing, interrupt selecti on, and base address registers (continued) bit description
94 amd geode? sc3200 processor data book general configuration block revision 5.1 0 sdbe0 (slave disconnect boundary enable). works in conjunction with the gx1 module?s pci control function 2 regis- ter (index 41h), bit 1 (sdbe1). sets boundaries for when the gx1 module is a pci slave. sdbe[1:0] 00: read and write disconnect on boundaries set by bits [3:2] of the gx1 module?s pci contro l function 2 register (index 41h). 01: write disconnects on boundaries set by bits [3:2] of t he gx1 module?s pci control function 2 register. read discon- nects on cache line boundary of 16 bytes. 1x: read and write disconnect on cache line boundary of 16 bytes. this bit is reset to 1. all pci bus masters (including sc3200?s on-c hip pci bus masters, e.g., the usb controller) must be disabled while modify- ing this bit. when accessing this regist er while any pci bus master is enabled, use read-modify-write to ensure these bit contents are unchanged. offset 38h interrupt selection regist er - intsel (r/w) reset value: 00h this register selects the irq signal of the combined watchdog and high-resolution timer interrupt. this interrupt is shareable with other interrupt sources. 7:4 reserved. write as read. 3:0 cbirq. configuration block interrupt. 0000: disable 0100: irq4 1000: irq8# 1100: irq12 0001: irq1 0101: irq5 1001: irq9 1101: reserved 0010: reserved 0110: irq6 1010: irq10 1110: irq14 0011: irq3 0111: irq7 1011: irq11 1111: irq15 offset 39h-3bh reserved - rsvd offset 3ch device identification number register - id (ro) reset value: xxh this register identifies the device. sc3200 = 04h. offset 3dh revision register - rev (ro) reset value: xxh this register identifies the device revision. see the amd geode? sc3200 specification update document for value. offset 3eh-3fh configuration base address register - cba (ro) reset value: xxh this register sets the base ad dress of the configuration block. 15:6 configuration base address. these bits are the high bits of the configuration base address. 5:0 configuration base address. these bits are the low bits of the configurat ion base address. these bits are set to 0. table 4-2. multiplexing, interrupt selecti on, and base address registers (continued) bit description
amd geode? sc3200 processor data book 95 general configuration block revision 5.1 4.3 watchdog the sc3200 includes a watchdog function to serve as a fail-safe mechanism in case the system becomes hung. when triggered, the watchdog mechanism returns the system to a known state by generating an interrupt, an smi, or a system reset (depending on configuration). 4.3.1 functional description watchdog is enabled when the watchdog timeout (wdto) register (offset 00h) is set to a non-zero value. the watchdog timer starts with this value and counts down until either the count reaches 0, or a trigger event restarts the count (with th e wdto register value). the watchdog timer is restarted in any of the following cases: the wdto register is set with a non-zero value. the watchdog timer reac hes 0 and the watchdog overflow bit, wdovf (offset 04h[0]), is 0. the watchdog function is disabled in any of the follow- ing cases: system reset occurs. the wdto register is set to 0. the wdovf bit is already 1 when the timer reaches 0. 4.3.1.1 watchdog timer the watchdog timer is a 16-bit down counter. its input clock is a 32 khz clock divided by a predefined value (see wdpres field, offset 02h[3:0]). the 32 khz input clock is enabled when either: the gx1 module?s internal suspa# signal is 1. or the gx1 module?s internal suspa# signal is 0 and the wd32kpd bit (offset 02h[8]) is 0. the 32 khz input clock is disabled, when: the gx1 module?s internal suspa# signal is 0 and the wd32kpd bit is 1. for more information about signal suspa#, refer to the amd geode? gx1 processor data book . when the watchdog timer reaches 0: if the wdovf bit in the wdsts register (offset 04h[0]) is 0, an interrupt, an smi or a system reset is generated, depending on the value of the wdtype1 field in the wdcnfg register (offset 02h[5:4]). if the wdovf bit in the wdsts register is already 1 when the watchdog timer reaches 0, an interrupt, an smi or a system reset is generated according to the wdtype2 field (off set 02h[7:6]), and the timer is disabled. the watchdog timer is re-enabled when a non-zero value is written to the wdto register (offset 00h). the interrupt or smi is de-asserted when the wdovf bit is set to 0. the reset generate d by the watchdog function is used to trigger a system reset via the co re logic mod- ule. the value of the wdovf bit, the wdtype1 field, and the wdtype2 field are not affected by a system reset (except when generated by power-on reset). the sc3200 also allows no action to be taken when the timer reaches 0 (according to wdtype1 field and wdtype2 field). in this case only the wdovf bit is set to 1. figure 4-1. watchdog block diagram wdpres wdto timer wdovf wdtype1 or wdtype2 internal fast-pci bus 32 khz por# watchdog reset irq smi suspa#
96 amd geode? sc3200 processor data book general configuration block revision 5.1 watchdog interrupt the watchdog interrupt (if configured and enabled) is routed to an irq signal. the irq signal is programmable via the intsel register (offset 38h, described in table 4-2 "multiplexing, interrupt selection, and base address regis- ters" on page 88). the wat chdog interrupt is a share- able, active low, level interrupt. watchdog smi the watchdog smi is recognized by the core logic module as internal input signal ext_smi0#. to use the watchdog smi, core logic registers must be configured appropriately. 4.3.2 watchdog registers table 4-3 describes the watchdog registers. 4.3.2.1 usage hints smm code should set bit 8 of the wdcnfg register to 1 when entering acpi c3 state, if the watchdog timer is to be suspended. if this is not done, the watchdog timer is functional during c3 state. smm code should set bit 8 of the wdcnfg register to 1, when entering acpi s1 and s2 states if the watchdog timer is to be suspended. if this is not done, the watchdog timer is functional during s1 and s2 states. table 4-3. watchdog registers bit description offset 00h-01h watchdog timeout register - wdto (r/w) reset value: 0000h this register specifies the pr ogrammed watchdog timeout period. 15:0 programmed timeout period. offset 02h-03h watchdog configuration re gister - wdcnfg (r/w) reset value: 0000h this register selects the signal to be generated when the timer reaches 0, whether or not to disable the 32 khz input clock dur ing low power states, and the prescaler value of the clock input. 15:9 reserved. write as read. 8 wd32kpd (watchdog 32 khz power down). 0: 32 khz clock is enabled. 1: 32 khz clock is disabled, when the gx1 module asserts its internal suspa# signal. this bit is cleared to 0, when por# is asserted or when the gx1 module de-asserts its internal suspa# signal (i.e., on suspa# rising edge). see section 4.3.2.1 "usage hints" on page 96. 7:6 wdtype2 (watchdog event type 2) . 00: no action 01: interrupt 10: smi 11: system reset this field is reset to 0 when por# is asserted. other system resets do not affect this field. 5:4 wdtype1 (watchdog event type 1). 00: no action 01: interrupt 10: smi 11: system reset this field is reset to 0 when por# is asserted. other system resets do not affect this field. 3:0 wdpres (watchdog timer prescaler). divide 32 khz by: 0000: 1 0100: 16 1000: 256 1100: 4096 0001: 2 0101: 32 1001: 512 1101: 8192 0010: 4 0110: 64 1010: 1024 1110: reserved 0011: 8 0111: 128 1011: 2048 1111: reserved
amd geode? sc3200 processor data book 97 general configuration block revision 5.1 4.4 high-resolution timer the sc3200 provides an accurate time value that can be used as a time stamp by system software. this time is called the high-resolution timer. the length of the timer value can be extended via software. it is normally enabled while the system is in the c0 and c1 states. optionally, software can be programmed to enable use of the high- resolution timer during c3 state and/or s1 state as well. in all other power states the high-resolution timer is dis- abled. 4.4.1 functional description the high-resolution timer is a 32-bit free-running count- up timer that uses the oscillator clock or the oscillator clock divided by 27. bit tmclksel of the tmcn fg register (offset 0dh[1]) can be set via software to determine which clock should be used for the high-resolution timer. when the most significant bit (bit 31) of the timer changes from 1 to 0, bit tmsts of the tmsts register (offset 0ch[0]) is set to 1. when both bit tmsts and bit tmen (offset 0dh[0]) are 1, an interrupt is asserted. otherwise, the interrupt is de-asserted. this interrupt enables software emulation of a larger timer. the high-resolution timer interrupt is routed to an irq signal. the irq signal is programmable via the intsel register (offset 38h). for more information about this regis- ter, see section section 4.2 "multiplexing, interrupt selec- tion, and base address registers" on page 88. system software uses the read-only tmvalue register (offset 08h[31:0]) to read the current value of the timer. the tmvalue register has no default value. the input clock (derived from the 27 mhz crystal oscillator) is enabled when: the gx1 module?s internal suspa# signal is 1. or the gx1 module?s internal suspa# signal is 0 and bit tm27mpd (offset 0dh[2]) is 0. the input clock is disabled, when the gx1 module?s inter- nal suspa# signal is 0 and the tm27mpd bit is 1. for more information about signal suspa# see section 4.4.2.1 "usage hints" on page 97 and the amd geode? gx1 processor data book . the high-resolution timer function resides on the internal fast-pci bus and its registers are in general configuration block address space. only one complete register should be accessed at-a-time (e.g., dword access should be used for dword wide registers and byte access should be used for byte-wide registers). 4.4.2 high-resolution timer registers table 4-4 on page 98 describes the registers for the high- resolution timer (timer). 4.4.2.1 usage hints smm code should set bit 2 of the tmcnfg register to 1 when entering acpi c3 state if the high-resolution timer should be disabled. if this is not done, the high- resolution timer is functional during c3 state. smm code should set bit 2 of the tmcnfg register to 1 when entering acpi s1 state if the high-resolution timer should be disabled. if this is not done, the high- resolution timer is functional during s1 state. offset 04h watchdog status regist er - wdsts (r/wc) reset value: 00h this register contains wa tchdog status information. 7:4 reserved. write as read. 3 wdrst (watchdog reset asserted). (read only) this bit is set to 1 when watchdo g reset is asserted. it is set to 0 when por# is asserted, or when the wdovf bit is set to 0. 2 wdsmi (watchdog smi asserted). (read only) this bit is set to 1 when watchdog smi is asserted. it is set to 0 when por# is asserted, or when the wdovf bit is set to 0. 1 wdint (watchdog interrupt asserted. (read only) this bit is set to 1 when the watchdog interrupt is asserted. it is set to 0 when por# is asserted, or when the wdovf bit is set to 0. 0 wdovf (watchdog overflow) . this bit is set to 1 when the watchdog ti mer reaches 0. it is set to 0 when por# is asserted, or when a 1 is written to this bit by softwa re. other system reset sources do not affect this bit. offset 05h-07h reserved - rsvd table 4-3. watchdog registers (continued) bit description
98 amd geode? sc3200 processor data book general configuration block revision 5.1 table 4-4. high-resolution timer registers bit description offset 08h-0bh timer value register - tmvalue (ro) reset value: xxxxxxxxh this register contains the current value of the high-resolution timer. 31:0 current timer value. offset 0ch timer status register - tmsts (r/w) reset value: 00h this register supplies the high-re solution timer status information. 7:1 reserved. 0 tmsts (timer status). this bit is set to 1 when the most significant bi t (bit 31) of the timer c hanges from 1 to 0. it is cleared to 0 upon system reset or when 1 is written by software to this bit. offset 0dh timer configuration register - tmcnfg (r/w) reset value: 00h this register enables the high-resolution timer interrupt; select s the timer clock; and disables the 27 mhz internal clock duri ng low power states. 7:3 reserved. 2 tm27mpd (timer 27 mhz power down) . this bit is cleared to 0 when por# is asserted or when the gx1 module de- asserts its internal suspa# signal (i.e., on suspa# rising edge). see section 4.4.2.1 "usage hints" on page 97. 0: 27 mhz input clock is enabled. 1: 27 mhz input clock is disabled when the gx 1 module asserts its internal suspa# signal. 1 tmclksel (timer clock select). 0: count-up timer uses the osci llator clock divided by 27. 1: count-up timer uses the oscillator clock, 27 mhz clock. 0 tmen (timer interrupt enable). 0: high-resolution timer interrupt is disabled. 1: high-resolution timer interrupt is enabled. offset 0eh-0fh reserved - rsvd
amd geode? sc3200 processor data book 99 general configuration block revision 5.1 4.5 clock generators and plls this section describes the r egisters for the clocks required by the gx1 module, core logic module, and the video processor, and how these clocks are generated. see fig- ure 4-2 for a clock generation diagram. the clock generators are based on 32.768 khz and 27.000 mhz crystal oscillators. the 32.768 khz crystal oscillator is described in section 5.5.2 "rtc clock generation" on page 121 (functional description of the rtc). figure 4-2. clock generation block diagram 32.768 khz crystal external pci clock pll5 internal fast-pci clock pll6 acpi clock (14.318 mhz) pll2 dot clock core clock adl pll4 usb clock (48 mhz) divider sdram clock 32.768 khz and i/o block clock real-time clock (rtc) 24.576 mhz pll3 ac97_clk divide by 4 divide by 2 (33.3 mhz) 48 mhz 33 mhz 66 mhz oscillator (24.576 mhz) to pa d disable disable disable shutdown shutdown shutdown shutdown shutdown 27 mhz crystal oscillator clk27m ball (acpi) (acpi) high-resolution timer clock shutdown clk shutdown 48 mhz 57.273 mhz 25-135 mhz 66.67 mhz 100-333 mhz note: v pll2 powers pll2 and pll5. v pll3 powers pll3, pll4, and pll6.
100 amd geode? sc3200 processor data book general configuration block revision 5.1 4.5.1 27 mhz crystal oscillator the internal oscillator employs an external crystal con- nected to the on-chip amplifie r. the on-chip amplifier is accessible on the x27i input and x27o output signals. see figure 4-3 for the recommended external circuit and table 4-5 for a list of the circuit components. choose c 1 and c 2 capacitors to matc h the crystal?s load capacitance. the load capacitance c l ?seen? by crystal y is comprised of c 1 in series with c 2 and in parallel with the parasitic capacitance of the ci rcuit. the parasitic capaci- tance is caused by the chip package, board layout and socket (if any), and can vary from 0 to 10 pf. the rule of thumb in choosing these capacitors is: c l = (c 1 * c 2 ) / (c 1 + c 2 ) + c parasitic example 1: crystal c l = 10 pf, c parasitic = 8.2 pf c 1 = 3.6 pf, c 2 = 3.6 pf example 2: crystal c l = 20 pf, c parasitic = 8 pf c 1 = 24 pf, c 2 = 24 pf figure 4-3. recommended oscillator external circuitry internal external r 2 x27i x27o c 1 c 2 r 1 y to other modules table 4-5. crystal oscillator circuit components component parameters values tolerance crystal resonance frequency 27.00 mhz parallel mode 50 ppm or better type at-cut or bt-cut serial resistance 40 ? max shunt capacitance 7 pf max load capacitance, c l 10-20 pf temperature coefficient user-defined resistor r 1 resistance 20 m ? 5% resistor r 2 1 resistance 100 ? 5% capacitor c 1 1 capacitance 3-24 pf 5% capacitor c 2 1 capacitance 3-24 pf 5% 1. the value of these components is re commended. it should be tuned accord ing to crystal and board parameters.
amd geode? sc3200 processor data book 101 general configuration block revision 5.1 4.5.2 gx1 module core clock the core clock is generated by an analog delay loop (adl) clock generator from the internal fast-pci clock. the clock can be any whole-number multiple of the input clock between 4 and 10. possible values are listed in table 4-6. at power-on reset, the core cl ock multiplier value is set according to the value of four strapped balls - clksel[3:0] (ebga balls al13, ak3, b27, f3 / tepbga balls p30, d29, af3, b8). these balls also select the clock which is used as input to the multiplier, as shown in table 4-7. 4.5.3 internal fast-pci clock the internal fast-pci clock can be configured to 33, 48, or 66 mhz via strap options on the clksel1 and clksel0 balls. these can be read in the internal fast-pci clock field in the ccfc register (gcb+i/o offset 1eh[9:8]). (see table 4-8 on page 103 details on the ccfc register.) note: not all speeds are supported. for information on supported speeds, see section a.1 "order information" on page 443. table 4-6. core clock frequency adl multiplier value internal fast-pci clock freq. (mhz) 33.33 48 66.67 4 133.3 192 266.7 5 166.7 240 --- 6 200 288 --- 7 233.3 --- --- 8 266.7 --- --- 9 --- --- --- 10 --- --- --- table 4-7. strapped core clock frequency clksel[3:0] straps internal fast-pci clock freq. (mhz) (gcb+i/o offset 1eh[9:8]) default adl multiplier maximum core clock freq. (mhz) multiply by multiplier value (gcb+i/o offset 1eh[3:0]) 0111 33.33 4 0100 133 1011 5 0101 167 1111 6 0110 200 0000 7 0111 233 0100 8 1000 266 1000 9 1001 reserved 1100 10 1010 reserved 0001 48 4 0100 192 0101 5 0101 240 1001 6 0110 288 1101 7 0111 reserved 0110 66.67 4 0100 266 1010 5 0101 reserved
102 amd geode? sc3200 processor data book general configuration block revision 5.1 4.5.4 superi/o clocks the superi/o module requires a 48 mhz input for fast infrared (fir), uart, and other functions. this clock is sup- plied by pll4 using a multiplier value of 576/(108x3) to generate 48 mhz. 4.5.5 core logic module clocks the core logic module requires the following clock sources: real-time clock (rtc) rtc requires a 32.768 khz clock which is supplied directly from an internal low-power crystal oscillator. this oscillator uses battery power and has very low current consumption. usb the usb requires a 48 mhz input which is supplied by pll4. the required total frequency accuracy and slow jitter for usb is 500 ppm; edge to edge jitter is 1.2%. acpi the acpi logic block uses a 14.32 mhz clock supplied by pll6. pll6 creates this clock from the 32.768 khz clock, with a multiplier value of 6992/4 to output a 57.278 mhz clock that is divided by 4. external pci the pci interface uses a 33.3 mhz clock that is created by pll5 and divided by 2. pll5 uses the 27 mhz clock, to output a 66.67 mhz clock. pll5 has a frequency accuracy of 0.1%. ac97 the sc3200 generates the 24.576 mhz clock required by the audio codec. therefore, no crystal need be included for the audio codec on the system board. pll3 uses the crystal oscillator clock, to generate a 24.576 mhz clock. this clock is driven on the ac97_clk ball. the accuracy of the clock supplied by the sc3200 is 50 ppm. 4.5.6 video processor clocks the video processor requires the following clock sources: dot the dot clock is generated by pll2. it is supplied to the display controller in the gx 1 module (dclk) that creates the pixel information, and is returned to the graphics block (pclk) with this information. pll2 uses the 27 mhz clock to generate the dot clock. video the video clock source depends on the source of the video data. if the video data is coming from the gx1 module (capture video mode), the video clock is generated by the display controller. if the video data is coming directly from the vip block (direct video mode), the video clock is generated by the vip block.
amd geode? sc3200 processor data book 103 general configuration block revision 5.1 4.5.7 clock registers table 4-8 describes the registers of the clock generator and pll. table 4-8. clock generator configuration bit description offset 10h maximum core clock multiplier regist er - mccm (ro) reset value: strapped value this register holds the maximum core clock multiplier value. the maximum clock frequency allowed by the core, is the fast-pci c lock multiplied by this value. 7:4 reserved. 3:0 mcm (maximum clock multiplier). this 4-bit value is the maximum multiplier value allowed for the core clock generator. it is derived from strap pins clksel[3:0] based on the multiplier value in table 4-7 on page 101. offset 11h reserved - rsvd offset 12h pll power control register - ppcr (r/w) reset value: 2fh this register controls operation of the plls. 7 reserved. 6 expcid (disable external pci clock). 0: external pci clock is enabled. 1: external pci clock is disabled. 5 gpd (disable graphic pixel reference clock). 0: pll2 input clock is enabled. 1: pll2 input clock is disabled. 4 reserved. 3 pll3sd (shut down pll3). ac97 codec clock. 0: pll3 is enabled. 1: pll3 is shutdown. 2 fm1sd (shut down pll4). 0: pll4 is enabled. 1: pll4 is shutdown, unless internal fast-pci clock is strapped to 48 mhz. 1 c48md (disable superi/o and usb clock). 0: usb and superi/o clock is enabled. 1: usb and superi/o clock is disabled. 0 reserved. write as read. offset 13h-17h reserved - rsvd offset 18h-1bh pll3 configuration regist er - pll3c (r/w) reset value: e1040005h 31:24 mffc (mff counter value). fvco = oscclk * mfbc / (mffc * moc) oscclk = 27 mhz 23:19 reserved. write as read. 18:8 mfbc (mfb counter value). fvco = oscclk * mfbc / (mffc * moc) oscclk = 27 mhz note: bits 18, 9, and 8 cannot be changed. bit 18 is always a 1; bits 9 and 8 are always 0. 7 reserved. write as read. 6 reserved. must be set to 0. 5:0 moc (mo counter value). fvco = oscclk * mfbc / (mffc * moc) oscclk = 27 mhz
104 amd geode? sc3200 processor data book general configuration block revision 5.1 offset 1eh-1fh core clock frequency control regi ster - ccfc (r/w) reset value: strapped value this register controls the configuration of the core clock multiplier and the reference clocks. 15:14 reserved. 13 reserved. must be set to 0. 12 reserved. must be set to 0. 11:10 reserved. 9:8 fpcick (internal fast-pci clock). (read only) reflects the internal fast-pci clock and is the input to the gx1 module that is used to generate the core clock. these bi ts reflect the value of strap pins clksel[1:0]. 00: 33.3 mhz 01: 48 mhz 10: 66.7 mhz 11: 33.3 mhz 7:4 reserved. 3:0 mval (multiplier value). this 4-bit value controls the multiplier in adl. the value is set according to the maximum clock multiplier bits of the mccm register (o ffset 10h). the multiplier value should never be written with a multiplier which is diff er- ent from the multiplier indicated in the mccm register. 0100: multiply by 4 0101: multiply by 5 0110: multiply by 6 0111: multiply by 7 1000: multiply by 8 1001: multiply by 9 1010: multiply by 10 other: reserved table 4-8. clock generator configuration (continued) bit description
amd geode? sc3200 processor data book 105 5 superi/o module revision 5.1 5.0 superi/o module the superi/o (sio) module is a pc98 and acpi compliant sio that offers a single-cell solution to the most commonly used isa peripherals. the sio module incorporates: two serial ports, an infrared communication port that supports fir, mir, hp-sir, sharp-ir, and consumer elec tronics-ir, a full ieee 1284 parallel port, two access.bus interface (acb) ports, sys- tem wakeup control (swc), and a real-time clock (rtc) that provides rtc timekeeping. outstanding features full compatibility with acpi revision 1.0 requirements. system wakeup control powered by v sb , generates power-up request and a pme (power management event) in response to sdata_in2 (an audio codec), irrx1 (a pre-programmed ceir), or a ri2# (serial port ring indicate) event. advanced rtc, y2k compliant. figure 5-1. sio block diagram wakeup events host interface isa interface ab2d pwureq ir comunication infrared /serial interface serial port 2 serial interface v sb v bat port/serial port 3 serial interface system wakeup control real-time clock ab2c access.bus 2 ab1d ab1c access.bus 1 ieee 1284 parallel port parallel port interface serial port 1
106 amd geode? sc3200 processor data book superi/o module revision 5.1 5.1 features pc98 and acpi compliant pnp configuration register structure flexible resource allocation for all logical devices: ? relocatable base address ? 9 parallel irq routing options ? 3 optional 8-bit dma channels (where applicable) parallel port software or hardware control enhanced parallel port (epp) compatible with version epp 1.9 and ieee 1284 compliant epp support for version epp 1.7 of the xircom specifi- cation epp support as mode 4 of the extended capabilities port (ecp) ieee 1284 compliant ecp, including level 2 selection of internal pull-up or pull-down resistor for paper end (pe) pin pci bus utilization reduction by supporting a demand dma mode mechanism and a dma fairness mechanism protection circuit that prevents damage to the parallel port when a printer connected to it powers up or is oper- ated at high voltages, even if the device is in power- down output buffers that can sink and source 14 ma serial port 1 16550a compatible (sin1, sout1, dtr1#/bout1 signals only) serial port 2 16550a compatible serial port 3 / infrared (ir) communication port serial port 3 ? sin and sout signals only ? data rate of up to 1.5-mbps ? software compatible with the 16550a and the 16450 ? shadow register support for write-only bit monitoring ? dma support ir communication port ? irda 1.1 and 1.0 compatible ? data rate of up to 115.2 kbps (hp-sir) ? data rate of 1.152 mbps (mir) ? data rate of 4.0 mbps (fir) ? selectable internal or external modulation/demodula- tion (ask-ir and dask-ir options of sharp-ir) ? consumer-ir (tv-remote) mode ? consumer remote control supports rc-5, rc-6, nec, rca and recs 80 ? dma support system wakeup control (swc) power-up request upon detection of ri2#, ceir, or sdata_in2 activity: ? optional routing of power-up request on irq line pre-programmed ceir address in a pre-selected standard (any nec, rca or rc-5) powered by v sb battery-backed wakeup setup power-fail recovery support real-time clock a modifiable address that is referenced by a 16-bit programmable register ds1287, mc146818 and pc87911 compatibility 242 bytes of battery backed up cmos ram in two banks selective lock mechanisms for the cmos ram battery backed up century calendar in days, day of the week, date of month, months, years and century, with automatic leap-year adjustment battery backed-up time of day in seconds, minutes and hours that allows a 12 or 24 hour format and adjust- ments for daylight savings time bcd or binary format for time keeping three different maskable interrupt flags: ? periodic interrupts - at intervals from 122 ms to 500 ms ? time-of-month alarm - at intervals from once per second to once per month ? update ended interrupt - once per second upon completion of update separate battery pin, 3.0v operation that includes an internal ul protection resistor 7 a typical power consumption during power down double-buffer time registers y2k compliant clock sources 48 mhz clock input on-chip low frequency clock generator for wakeup 32.768 khz crystal with an internal frequency multiplier to generate all required internal frequencies
amd geode? sc3200 processor data book 107 superi/o module revision 5.1 5.2 module architecture the sio module comprises a collection of generic func- tional blocks. each functional block is described in detail later in this chapter. the beginning of this chapter describes the sio structure and provides all device specific information, including specia l implementation of generic blocks, system interface and device configuration. the sio module is based on eight logical devices, the host interface, and a central configuration register set, all built around a central, internal 8-bit bus. the host interface serves as a bridge between the external isa interface and the internal bus. it supports 8-bit i/o read, 8-bit i/o write and 8-bit dma transactions, as defined in personal computer bus standard p996 . the central configuration register set supports acpi com- pliant pnp configuration. the configuration registers are structured as a subset of the plug and play standard reg- isters, defined in appendix a of the plug and play isa specification version 1.0a by intel and microsoft?. all sys- tem resources assigned to the functional blocks (i/o address space, dma channels and irq lines) are config- ured in, and managed by, the central configuration register set. in addition, some function-specific parameters are con- figurable through this unit and distributed to the functional blocks through special control signals. the source of the device internal clocks is the 48 mhz clock signal or through the 32.768 khz crystal with an internal frequency multiplier. rtc operates on a 32 khz clock. figure 5-2. detailed sio block diagram sin1 sout1 irrx1/sin3 irtx/sout3 pwureq parallel serial port 1 and control registers system wakeup port dack0-3 drq0-3 internal bus host control signals irq1-12,14-15 sin2 sout2 rts2# dtr2#/bout2 cts2 serial port 2 ri2# v bat v sb configuration tc infrared interface real-time clock (rtc) config clkin mr x1c/x1 x2c d[7:0] iochrdy iowr# iord# a[15:0] aen zws# alarm access. ab1c ab1d ab2c ab2d sdata_in2 ack# afd#/dstrb# busy/wait# err# init# pd[7:0] pe slct slin#/astrb# stb#/write# dtr#/bout1 internal internal internal signals internal ri2# dcd2# dsr2# bus 1 access. bus 2 signal communication port/serial port 3 signals
108 amd geode? sc3200 processor data book superi/o module revision 5.1 5.3 configuration st ructure / access this section describes the st ructure of the configuration register file, and the method of accessing the configuration registers. 5.3.1 index-data register pair the sio configuration access is performed via an index- data register pair, using only two system i/o byte locations. the base address of this register pair is determined according to the state of the io_siocfg_in bit field of the core logic module (f5bar0+i/o offset 00h[26:25]). table 5-1 shows the selected base addr esses as a function of the io_siocfg_in bit field. the index register is an 8-bit r/w register located at the selected base address (base+0). it is used as a pointer to the configuration register file, and holds the index of the configuration register that is currently accessible via the data register. reading the index register returns the last value written to it (or the default of 00h after reset). the data register is an 8-bit virtual register, used as a data path to any configuration register. accessing the data register results with physicall y accessing the configuration register that is currently po inted by the index register. 5.3.2 banked logical device registers each functional block is associated with a logical device number (ldn). the configuration registers are grouped into banks, where each bank holds the standard configura- tion registers of the corresponding logical device. table 5-2 shows the ldns of the device functional blocks. figure 5-3 shows the structure of the standard pnp config- uration register file. the sio control and configuration registers are not banked and are accessed by the index- data register pair only (as described above). however, the logical device control and configuration registers are duplicated over eight banks for eight logical devices. there- fore, accessing a specific register in a specific bank is per- formed by two-dimensional indexing, where the ldn register selects the bank (or logical device), and the index register selects the register within the bank. accessing the data register while the index register holds a value of 30h or higher results in a physical access to the logical device configuration registers currently pointed to by the index register, within the logical device bank currently selected by the ldn register. figure 5-3. structure of the standard configuration register file table 5-1. sio configuration options io_siocfg_in settings i/o address description index register data register 00 - - sio disabled 01 - - configuration access disabled 10 002eh 002fh base address 1 selected 11 015ch 015dh base address 2 selected table 5-2. ldn assignments ldn functional block reference 00h real-time clock (rtc) page 114 01h system wakeup control (swc) page 116 02h infrared communication port (ircp) or serial port 3 (sp3) page 117 03h serial port 1 (sp1) page 118 05h access.bus 1 (acb1) page 119 06h access.bus 2 (acb2) 07h parallel port (pp) page 120 08h serial port 2 (sp2) page 118 07h 20h 30h 60h 75h feh logical device number register sio configuration registers logical device control register standard logical device banks (one per logical device) 2fh f0h bank 63h 74h 70h 71h standard registers special (vendor-defined) configuration registers logical device select
amd geode? sc3200 processor data book 109 superi/o module revision 5.1 write accesses to unimplemented registers (i.e., accessing the data register while the i ndex register points to a non- existing register or the ldn is 07h or higher than 08h), are ignored and a read returns 00h on all addresses except for 74h and 75h (dma configuration registers) which returns 04h (indicating no dma channel is active). the configura- tion registers are accessible immediately after reset. 5.3.3 default configuration setup the device has four reset types: software reset this reset is generated by bi t 1 of the siocf1 register, which resets all logical de vices. a software reset also resets most bits in the sio configuration and control regis- ters (see section 5.4.1 on page 113 for the bits not affected). this reset does not af fect register bits that are locked for write access. hardware reset this reset is activated by the system reset signal. this resets all logical devices, with the exception of the rtc and the swc, and all sio configuration and control registers, with the exception of the siocf2 register. it also resets all superi/o control and configuration registers, except for those that are battery-backed. v pp power-up reset this reset is activated when either v sb or v bat is powered on after both have been off. v pp is an internal voltage which is a combination of v sb and v bat . v pp is taken from v sb if v sb is greater than the minimum (min) value defined in section 9.1.4 "operating co nditions" on page 370; oth- erwise, v bat is used as the v pp source. this reset resets all registers whose values are retained by v pp. v sb power-up reset this is an internally generated reset that resets the swc, excluding those swc registers whose values are retained by v pp . this reset is activated after v sb is powered up. the sio module wakes up with the default setup, as fol- lows: when a hardware reset occurs: ? the configuration base address is 2eh, 15ch or none, according to the io_siocfg_in bit values, as shown in table 5-1 on page 108. ? all logical devices are disabled, with the exception of the rtc and the swc, which remains functional but whose registers cannot be accessed. when either a hardware or a software reset occurs: ? the legacy devices are assigned with their legacy system resource allocation. ? the amd proprietary functions are not assigned with any default resources and the default values of their base addresses are all 00h. 5.3.4 address decoding a full 16-bit address decoding is applied when accessing the configuration i/o space, as well as the registers of the functional blocks. however, the number of configurable bits in the base address registers vary for each device. the lower 1, 2, 3 or 4 address bits are decoded within the functional block to determine the offset of the accessed register, within the device?s i/o range of 2, 4, 8 or 16 bytes, respectively. the rest of the bits are matched with the base address register to decode the entire i/o range allocated to the device. therefore the lower bits of the base address register are forced to 0 (ro), and the base address is forced to be 2, 4, 8 or 16 byte aligned, according to the size of the i/o range. the base address of the rtc, serial port 1, serial port 2, and the infrared communication port are limited to the i/o address range of 00h to 7fxh only (bits [15:11] are forced to 0). the parallel port base address is limited to the i/o address range of 00h to 3f8h. the addresses of the non- legacy devices are configurable within the full 16-bit address range (up to fffxh). in some special cases, other address bits are used for internal decoding (such as 10 in the parallel port). for more details, please see the detailed description of the base address register for each specific logical device.
110 amd geode? sc3200 processor data book superi/o module revision 5.1 5.4 standard configur ation registers as illustrated in figure 5-4, the standard configuration reg- isters are broadly divided into two categories: sio control and configuration registers and logical device control and configuration registers (one per logical device, some are optional). sio control and configuration registers the only pnp control register in the sio module is the log- ical device number register at index 07h. all other stan- dard pnp control registers are associated with pnp protocol for isa add-in cards, and are not supported by the sio module. the sio configuration registers at index 20h-27h are mainly used for part identification. (see section 5.4.1 "sio control and configuration registers" on page 113 for fur- ther details.) logical device control and configuration registers a subset of these registers is implemented for each logical device. (see table 5-2 on page 108 for ldn assignment and section 5.4.2 "logical device control and configura- tion" on page 114 for register details.) logical device control register (index 30h): the only implemented logical device control register is the activate register at index 30. bit 0 of the activate register and bit 0 of the sio configuration 1 register (global device enable bit) control the activation of the associated function block (except for the rtc and the swc). activation of the block enables access to the block?s registers, and attaches its system resources, which are unused as long as the block is not activated. activation of the block may also result in other effects (e.g., clock enable and active signaling), for certain functions. standard logical device configuration registers (index 60h-75h): these registers are used to manage the resource allocation to the functional blocks. the i/o port base address descriptor 0 is a pair of registers at index 60h-61h, holding the (first or only) 16-bit base address for the register set of the functional block. an optional second base-address (descriptor 1) at index 62h-63h is used for devices with more than one continuous register set. inter- rupt number select (index 70h) and interrupt type select (index 71h) allocate an irq line to the block and control its type. dma channel select 0 (index 74h) allocates a dma channel to the block, where applicable. dma channel select 1 (index 75h) allocates a second dma channel, where applicable. special logical device conf iguration registers (f0h- f3h): the vendor-defined registers, starting at index f0h are used to control function-specific parameters such as operation modes, power saving modes, pin tri-state, clock rate selection, and non-standard extensions to generic functions. figure 5-4. standard configuration registers map sio control and configuration registers logical device control and one per logical device configuration registers - index register name 07h logical device number 20h sio id 21h sio configuration 1 22h sio configuration 2 27h sio revision id 2eh reserved exclusively for amd use 30h logical device control (activate) 60h i/o port base address descriptor 0 bits [15:8] 61h i/o port base address descriptor 0 bits [7:0] 62h i/o port base address descriptor 1 bits [15:8] 63h i/o port base address descriptor 1 bits [7:0] 70h interrupt number select 71h interrupt type select 74h dma channel select 0 75h dma channel select 1 f0h device specific logical device configuration 1 f1h device specific logical device configuration 2 f2h device specific logical device configuration 3 f3h device specific logical device configuration 4 (some are optional)
amd geode? sc3200 processor data book 111 superi/o module revision 5.1 table 5-3 provides the bit definitions for the standard con- figuration registers. all reserved bits return 0 on reads, except where noted otherwise. they must not be m odified as such modifica- tion may cause unpredictable results. use read-modify- write to prevent the values of reserved bits from being changed during write. write only registers should not use read-modify-write during updates. table 5-3. standard configuration registers bit description index 07h logical device number (r/w) this register selects the current logi cal device. see table 5-2 for valid num bers. all other values are reserved. 7:0 logical device number. index 20h-2fh sio configuration (r/w) sio configuration and id registers. see se ction 5.4.1 "sio control and configuration registers" on page 113 for register/bit de tails. index 30h activate (r/w) 7:1 reserved. 0 logical device activation control. 0: disable 1: enable index 60h i/o port base address bits [15:8] descriptor 0 (r/w) 7:0 descriptor 0 a[15:8]. selects i/o lower limit address bits [15:8] for i/o descriptor 0. index 61h i/o port base address bits [7:0] descriptor 0 (r/w) 7:0 descriptor 0 a[7:0]. selects i/o lower limit address bits [7:0] for i/o descriptor 0. index 62h i/o port base address bits [15:8] descriptor 1 (r/w) 7:0 descriptor 1 a[15:8]. selects i/o lower limit address bits [15:8] for i/o descriptor 1. index 63h i/o port base address bits [7:0] descriptor 1 (r/w) 7:0 descriptor 1 a[7:0]. selects i/o lower limit address bits [7:0] for i/o descriptor 1. index 70h interrupt number (r/w) 7:4 reserved. 3:0 interrupt number. these bits select the interrupt number. a value of 1 selects irq1, a value of 2 selects irq2, etc. (up to irq12). note: irq0 is not a valid interrupt selection. index 71h interrupt request type select (r/w) selects the type and level of the interrupt reques t number selected in the previous register. 7:2 reserved. 1 interrupt level requested. level of interrupt request selected in previous register. 0: low polarity. 1: high polarity. this bit must be set to 1 (high polarity), except for irq8#, that must be low polarity. 0 interrupt type requested. type of interrupt request selected in previous register. 0: edge. 1: level. index 74h dma channel select 0 (r/w) selects selected dma channel for dma 0 of the logical device (0 - the first dma channel in case of using more than one dma chan nel). 7:3 reserved. 2:0 dma 0 channel select. this bit field selects the dma channel for dma 0. the valid choices are 0-3, where a value of 0 se lects dma channel 0, 1 selects channel 1, etc. a value of 4 indicates that no dma channel is active. values 5-7 are reserved.
112 amd geode? sc3200 processor data book superi/o module revision 5.1 index 75h dma channel select 1 (r/w) indicates selected dma channel for dma 1 of the logical device (1 - the second dma channel in case of using more than one dma channel). 7:3 reserved. 2:0 dma 1 channel select: this bit field selects the dma channel for dma 1. the valid choices are 0-3, where a value of 0 se lects dma channel 0, 1 selects channel 1, etc. a value of 4 indicates that no dma channel is active. values 5-7 are reserved. index f0h-feh logical device configuration (r/w) special (vendor-defined) configuration options. table 5-3. standard configuration registers (continued) bit description
amd geode? sc3200 processor data book 113 superi/o module revision 5.1 5.4.1 sio control and configuration registers table 5-4 lists the sio control and configuration regi sters and table 5-5 provides their bit formats. table 5-4. sio control and c onfiguration register map index type name power rail reset value 20h ro sid. sio id v core f5h 21h r/w siocf1. sio configuration 1 v core 01h 22h r/w siocf2. sio configuration 2 v pp 02h 27h ro srid. sio revision id v core 01h 2eh --- rsvd. reserved exclusively for amd use. --- --- table 5-5. sio control and configuration registers bit description index 20h sio id register - sid (ro) reset value: f5h 7:0 chip id. contains the identity number of the module. the sio module is identified by the value f5h. index 21h sio configuration 1 register - siocf1 (rw) reset value: 01h 7:6 general purpose scratch. when bit 5 is set to 1, these bits are ro. afte r reset, these bits can be read or write. once changed to ro, the bits can be changed back to r/w only by a hardware reset. 5 lock scratch. this bit controls bits 7 and 6 of this register. once th is bit is set to 1 by softwar e, it can be cleared to 0 only by a hardware reset. 0: bits 7 and 6 of this regi ster are r/w bits. (default) 1: bits 7 and 6 of this register are ro bits. 4:2 reserved. 1 sw reset . read always returns 0. 0: ignored. (default) 1: resets all devices that are reset by mr (with the exception of the lock bits) and the registers of the swc. 0 global device enable. this bit controls the function enable of all the logical devices in the sio module, except the swc and the rtc. it allows them to be disabled simultaneously by writing to a single bit. 0: all logical devices in the sio module are disabled, except the swc and the rtc. 1: each logical device is enabled according to its activate register at index 30h. (default) index 22h sio configuration 2 register - siocf2 (r/w) reset value: 02h note: this register is reset only when v pp is first applied. 7 reserved. 6:4 general purpose scratch. battery-backed. 3:2 reserved. 1 reserved. 0 reserved. (ro) index 27h sio revision id register - srid (ro) reset value: 01h 7:0 sio revision id. (ro) this ro register contains the i dentity number of the chip revision. srid is incremented on each revi- sion.
114 amd geode? sc3200 processor data book superi/o module revision 5.1 5.4.2 logical device control and configuration as described in section 5.3.2 "banked logical device reg- isters" on page 108, each functional block is associated with a logical device number (ldn). this section provides the register descriptions for each ldn. the register descriptions in this subsection use the follow- ing abbreviations for type: r/w = read/write r = read from a specific address returns the value of a specific register. write to the same address is to a different register. w =write ro = read only r/w1c = read/write 1 to clear. writing 1 to a bit clears it to 0. writing 0 has no effect. 5.4.2.1 ldn 00h - real-time clock table 5-6 lists the registers which are relevant to configura- tion of the real-time clock (rtc). only the last registers (f0h-f3h) are described here (table 5-7). see table 5-3 "standard configuration registers" on page 111 for descriptions of the other registers. table 5-6. relevant rtc configuration registers index type configuration register or action reset value 30h r/w activate. when bit 0 is cleared, the registers of this logical device are not accessible. 1 00h 60h r/w standard base address msb register. bits [7:3] (for a[15:11]) are ro, 00000b. 00h 61h r/w standard base address lsb register. bit 0 (for a0) is ro, 0b. 70h 62h r/w extended base address msb register. bits [7:3] (for a[15:11]) are ro, 00000b. 00h 63h r/w extended base address lsb register. bit 0 (for a0) is ro, 0b. 72h 70h r/w interrupt number. 08h 71h r/w interrupt type. bit 1 is r/w; other bits are ro. 00h 74h ro report no dma assignment. 04h 75h ro report no dma assignment. 04h f0h r/w ram lock register (rlr). 00h f1h r/w date of month alarm offset register (domao). sets index of date of month alarm register in the standard base address. 00h f2h r/w month alarm offset register (monao). sets index of month alarm register in the standard base address. 00h f3h r/w century offset register (ceno). sets index of century r egister in the standard base address. 00h 1. the logical device registers are maintained , and all rtc mechanisms are functional.
amd geode? sc3200 processor data book 115 superi/o module revision 5.1 table 5-7. rtc configuration registers bit description index f0h ram lock register - rlr (r/w) when any non-reserved bit in this register is set to 1, it c an be cleared only by hardware reset. 7 block standard ram. 0: no effect on standard ram access. (default) 1: read and write to locations 38h-3fh of the standard ram are blocked, writes ignored, and reads return ffh. 6 block ram write. 0: no effect on ram access. (default) 1: writes to ram (standard and extended) are ignored. 5 block extended ram write. this bit controls writes to bytes 00h-1fh of the extended ram. 0: no effect on the extended ram access. (default) 1: writes to bytes 00h-1fh of the extended ram are ignored. 4 block extended ram read. this bit controls read from bytes 00h-1fh of the extended ram. 0: no effect on extended ram access. (default) 1: reads to bytes 00h-1fh of the extended ram are ignored. 3 block extended ram. this bit controls access to the extended ram 128 bytes. 0: no effect on extended ram access. (default) 1: read and write to the extended ram are blocked: writes are ignored and reads return ffh. 2:0 reserved. index f1h date of month alarm regist er offset register - domao (r/w) 7 reserved. 6:0 date of month alarm register offset value. index f2h month alarm register offset register - manao (r/w) 7 reserved. 6:0 month alarm register offset value. index f3h century register of fset register - ceno (r/w) 7 reserved. 6:0 century register offset value.
116 amd geode? sc3200 processor data book superi/o module revision 5.1 5.4.2.2 ldn 01h - sy stem wakeup control table 5-8 lists registers that are relevant to the configura- tion of system wakeup control (swc). these registers are described earlier in table 5-3 "standard configuration registers" on page 111. table 5-8. relevant swc registers index type configuration register or action reset value 30h r/w activate. when bit 0 is cleared, the registers of this logical device are not accessible. 1 00h 60h r/w base address msb register. 00h 61h r/w base address lsb register. bits [3:0] (for a[3:0]) are ro, 0000b. 00h 70h r/w interrupt number. (for routing the internal pwureq signal.) 00h 71h r/w interrupt type. bit 1 is r/w. other bits are ro. 03h 74h ro report no dma assignment. 04h 75h ro report no dma assignment. 04h 1. the logical device registers are maintained, a nd all wakeup detection mechanisms are functional.
amd geode? sc3200 processor data book 117 superi/o module revision 5.1 5.4.2.3 ldn 02h - infrared communication port or serial port 3 table 5-9 lists the configurati on registers which affect the infrared communication port or serial port 3 (ircp/sp3). only the last register (f0h) is described here (table 5-10). see table 5-3 "standard configuration registers" on page 111 for descriptions of the other registers listed. table 5-9. relevant ircp/sp3 registers index type configuration register or action reset value 30h r/w activate. see also bit 0 of the siocf1 register. 00h 60h r/w base address msb register. bits [7:3] (for a[15:11]) are ro, 00000b. 03h 61h r/w base address lsb register. bit [2:0] (for a[2:0]) are ro, 000b. e8h 70h r/w interrupt number. 00h 71h r/w interrupt type. bit 1 is r/w; other bits are ro. 03h 74h r/w dma channel select 0 (rx_dma) .04h 75h r/w dma channel select 1 (tx_dma). 04h f0h r/w infrared communication port/seria l port 3 configuration register. 02h table 5-10. ircp/sp3 configuration register bit description index f0h infrared communication port/serial port 3 configuration register (r/w) reset value: 02h 7 bank select enable. enables bank switching. 0: all attempts to access the ext ended registers are ignored. (default) 1: enables bank switching. 6:3 reserved. 2 busy indicator. (ro) this bit can be used by power management so ftware to decide when to power-down the device. 0: no transfer in progress. (default) 1: transfer in progress. 1 power mode control. when the logical device is active in: 0: low power mode - clock disabled. the output signals are set to their default states. registers are maintained. (unlike active bit in index 30h that also pr events access to device registers.) 1: normal power mode - clock enabled. the device is f unctional when the logical de vice is active. (default) 0 tri-state control . when enabled and the device is inactive, the logica l device output pins are in tri-state. one excep- tion is the irtx/sout3 pin, which is driven to 0 when the infrar ed communication port or serial port 3 is inactive and is not affected by this bit. 0: disabled. (default) 1: enabled (when the device is inactive).
118 amd geode? sc3200 processor data book superi/o module revision 5.1 5.4.2.4 ldn 03h and 08h - serial ports 1 and 2 serial ports 1 and 2 are identical, except for their reset val- ues. serial port 1 is designated as ldn 03h and serial port 2 as ldn 08h. table 5-11 lists the configuration registers which affect serial ports 1 and 2. only the last register (f0h) is described here (table 5-12). see table 5-3 "standard configuration registers" on page 111 for descriptions of the others. table 5-11. relevant serial ports 1 and 2 registers index type configuration register or action reset value port 1 port 2 30h r/w activate. see also bit 0 of the siocf1 register. 00h 00h 60h r/w base address msb register. bits [7:3] (for a[15:11]) are ro, 00000b. 03h 02h 61h r/w base address lsb register . bit [2:0] (for a[2:0]) are ro, 000b. f8h f8h 70h r/w interrupt number. 04h 03h 71h r/w interrupt type. bit 1 is r/w; other bits are ro. 03h 03h 74h ro report no dma assignment .04h04h 75h ro report no dma assignment. 04h 04h f0h r/w serial ports 1 and 2 configuration register. 02h 02h table 5-12. serial ports 1 and 2 configuration register bit description index f0h serial ports 1 and 2 configuration register (r/w) reset value: 02h 7 bank select enable . enables bank switching for serial ports 1 and 2. 0: disabled. (default) 1: enabled. 6:3 reserved. 2 busy indicator. (ro) this bit can be used by power management software to decide when to power-down serial ports 1 and 2 logical devices. 0: no transfer in progress. (default) 1: transfer in progress. 1 power mode control. when the logical device is active in: 0: low power mode - serial ports 1 and 2 clock disabled. the out put signals are set to their default states. registers are maintained. (unlike active bit in i ndex 30h that also prevents access to serial ports 1 or 2 registers.) 1: normal power mode - serial ports 1 and 2 clock enabled. seri al ports 1 and 2 are functional when the respective logical devices are active. (default) 0 tri-state control . this bit controls the tri-state status of the de vice output pins when it is inactive (disabled). 0: disabled. (default) 1: enabled when device inactive.
amd geode? sc3200 processor data book 119 superi/o module revision 5.1 5.4.2.5 ldn 05h and 06h - access.bus ports 1 and 2 access.bus ports 1 and 2 (acb1 and acb2) are identi- cal. each acb is a two-wire synchronous serial interface compatible with the access.bus physical layer. acb1 and acb2 use a 24 mhz internal clock. six runtime registers for each access.bus are described in section 5.7 "access.bus interface" on page 137. acb1 is designated as ldn 05h and acb2 as ldn 06h. table 5-13 lists the configuration registers which affect the access.bus ports. only the last register (f0h) is described here (table 5-14). see table 5-3 "standard configuration registers" on page 111 for descriptions of the others. table 5-13. relevant acb1 and acb2 registers index type configuration register or action reset value 30h r/w activate. see also bit 0 of the siocf1 register 00h 60h r/w base address msb register. 00h 61h r/w base address lsb register. bits [2:0] (for a[2:0]) are ro, 000b. 00h 70h r/w interrupt number. 00h 71h r/w interrupt type. bit 1 is r/w. other bits are ro. 03h 74h ro report no dma assignment. 04h 75h ro report no dma assignment. 04h f0h r/w acb1 and acb2 configuration register. 00h table 5-14. acb1 and acb2 configuration register bit description index f0h acb1 and acb2 configuration register (r/w) this register is re set by hardware to 00h. 7:3 reserved. 2 internal pull-up enable. 0: no internal pull-up resistors on ab1c/ab2c and ab1d/ab2d. (default) 1: internal pull-up resistors on ab1c/ab2c and ab1d/ab2d. 1:0 reserved.
120 amd geode? sc3200 processor data book superi/o module revision 5.1 5.4.2.6 ldn 07h - parallel port the parallel port supports all ieee 1284 standard commu- nication modes: compatibility (known also as standard or spp), bidirectional (known also as ps/2), fifo, epp (known also as mode 4) and ecp (with an optional extended ecp mode). the parallel port includes two groups of runtime registers, as follows: a group of 21 registers at first level offset, sharing 14 entries. three of these regist ers (at offset 403h, 404h, and 405h) are used only in the extended ecp mode. a group of four registers, us ed only in the extended ecp mode, accessed by a second level offset. the desired mode is selected by the ecr runtime register (offset 402h). the selected mode determines which runt- ime registers are used and which address bits are used for the base address. (see section 5.8.1 on page 145 for fur- ther details regarding the runtime registers.) table 5-15 lists the configuration registers which affect the parallel port. only the last re gister (f0h) is described here (table 5-16). see table 5-3 "standard configuration reg- isters" on page 111 for descriptions of the others. table 5-15. relevant parallel port registers index type configuration register or action reset value 30h r/w activate. see also bit 0 of the siocf1 register. 00h 60h r/w base address msb register. bits [7:3] (for a[15:11]) are ro, 00000b. bit 2 (for a10) should be 0b. 02h 61h r/w base address lsb register. bits 1 and 0 (a1 and a0) are ro, 00b. for ecp mode 4 (epp) or when using the extended registers, bit 2 (a2) should also be 0b. 78h 70h r/w interrupt number. 07h 71h r/w interrupt type . bits [7:2] are ro. bit 1 is r/w. bit 0 is ro. it reflects the interrupt type di ctated by the parallel port operation mode. this bit is set to 1 (level interrupt) in extended mode and cleared (edge interrupt) in all other modes. 02h 74h r/w dma channel select. 04h 75h ro report no second dma assignment. 04h f0h r/w parallel port configuration register. (see table 5-16.) f2h table 5-16. parallel port configuration register bit description index f0h parallel port configuratio n register (r/w) reset value: f2h this register is rese t by hardware to f2h. 7:5 reserved. must be 11. 4 extended register access. 0: registers at base (address)+403h, base+404h and base+405h are not accessible (reads and writes are ignored). 1: registers at base (address)+403h, bas e+404h and base+405h are accessible. this option supports run-time configura- tion within the parallel port address space. 3:2 reserved. 1 power mode control. when the logical device is active: 0: parallel port clock disabled. ecp modes and epp timeout are not functional when the logical device is active. registers are maintained. 1: parallel port clock enabled. all operation modes are f unctional when the logical device is active. (default) 0 tri-state control. when enabled and the device is inactive, the l ogical device output pins are in tri-state. 0: disable. (default) 1: enable.
amd geode? sc3200 processor data book 121 superi/o module revision 5.1 5.5 real-time clock (rtc) the rtc provides timekeeping and calendar management capabilities. the rtc uses a 32.768 khz signal as the basic clock for timekeeping. it also includes 242 bytes of battery-backed ram for general-purpose use. the rtc provides the following functions: accurate timekeeping and calendar management alarm at a predetermined time and/or date three programmable interrupt sources valid timekeeping during power-down, by utilizing external battery backup 242 bytes of battery-backed ram ram lock schemes to protect its content internal oscillator circuit (the cr ystal itself is off-chip), or external clock supply for the 32.768 khz clock a century counter pnp support: ? relocatable index and data registers ? module access enable/disable option ? host interrupt enable/disable option additional low-power features such as: ? automatic switching from battery to v sb ? internal power monitoring on the vrt bit ? oscillator disabling to save battery during storage software compatible with the ds1287 and mc146818 5.5.1 bus interface the rtc function is initially mapped to the default superi/o locations at indexes 70h to 73h (two index/data pairs). these locations may be reassigned, in compliance with plug and play requirements. 5.5.2 rtc clock generation the rtc uses a 32.768 khz clock signal as the basic clock for timekeeping. the 32.768 khz clock can be sup- plied by the internal oscillator circuit, or by an external oscillator (see section 5.5.2.2 "external oscillator" on page 122). 5.5.2.1 internal oscillator the internal oscillator employs an external crystal con- nected to the on-chip amplifier. the on-chip amplifier is accessible on the x32i input and x32o output. see figure 5-5 for the recommended external circuit and table 5-17 for a listing of the circuit components. the oscillator may be disabled in certain conditions. see section 5.5.2.8 "oscilla- tor activity" on page 125 for more details. figure 5-5. recommended oscillator external circuitry v bat c f internal external r 2 x32i x32o c 1 c 2 r 1 y to other modules battery b 1 c f = 0.1 f table 5-17. crystal oscillator circuit components component parameters values tolerance crystal resonance frequency 32.768 khz parallel mode user-defined type n-cut or xy-bar serial resistance 40 k ? max quality factor, q 35000 min shunt capacitance 2 pf max load capacitance, c l 9-13 pf temperature coefficient user-defined resistor r 1 resistance 20 m ? 5% resistor r 2 resistance 120 k ? 5% capacitor c 1 capacitance 3 to 10 pf 5% capacitor c 2 capacitance 3 to 10 pf 5%
122 amd geode? sc3200 processor data book superi/o module revision 5.1 external elements choose c 1 and c 2 capacitors (see figure 5-5 on page 121) to match the crystal?s load capacitance. the load capacitance c l ?seen? by crystal y is comprised of c 1 in series with c 2 and in parallel with the parasitic capacitance of the circuit. the parasitic capacitance is caused by the chip package, board layout and socket (if any), and can vary from 0 to 10 pf. the rule of thumb in choosing these capacitors is: c l = (c 1 * c 2 ) / (c 1 + c 2 ) + c parasitic example: crystal c l = 10 pf, c parasitic = 8.2 pf c 1 = 3.6 pf, c 2 = 3.6 pf oscillator startup the oscillator starts to generate 32.768 khz pulses to the rtc after about 100 ms from when v bat is higher than v batmin (2.4v) or v sb is higher than v sbmin (3.0v). the oscillation amplitude on the x32o pin stabilizes to its final value (approximately 0.4v peak -to-peak around 0.7v dc) in about 1 s. c 1 can be trimmed to achieve precisely 32.768 khz. to achieve a high time accuracy, use crystal and capacitors with low tolerance and temperature coefficients. 5.5.2.2 external oscillator 32.768 khz can be applied from an external clock source, as shown in figure 5-6. connections connect the clock to the x32i ball, leaving the oscillator output, x32o, unconnected. signal parameters the signal levels should conform to the voltage level requirements for x32i, of squar e or sine wave of 0.0v to v core amplitude. the signal should have a duty cycle of approximately 50%. it should be sourced from a battery- backed source in order to oscillate during power-down. this assures that the rtc delivers updated time/calendar information. 5.5.2.3 timing generation the timing generation function divides the 32.768 khz clock by 2 15 to derive a 1 hz signal, which serves as the input for the seconds counter. this is performed by a divider chain composed of 15 divide-by-two latches, as shown in figure 5-7. bits [6:4] (dv[2:0]) of the cr a register control the follow- ing functions: normal operation of the divider chain (counting). divider chain reset to 0. oscillator activity when only v bat power is present (backup state). the divider chain can be activated by setting normal opera- tional mode (bits [6:4] of cra = 01x or 100). the first update occurs 500 ms after divider chain activation. bits [3:0] of cra select one the of fifteen taps from the divider chain to be used as a periodic interrupt. the peri- odic flag becomes active after half of the programmed period has elapsed, following divider chain activation. see table 5-20 on page 127 for more details. figure 5-6. external oscillator connections figure 5-7. divider chain control 32.768 khz clock generator internal external clkin x32o nc to other modules battery v bat b 1 c f c f out power c f = 0.1 f (x32i) r 1 r 2 r 2 = 30 k ? r 1 = 30 k ? 3.3v square wave 32.768 khz 2 1 2 2 2 3 2 13 2 14 2 15 1hz divider chain dv2 dv1 dv0 cra register oscillator enable x32i x32o to other reset 6 5 4 modules
amd geode? sc3200 processor data book 123 superi/o module revision 5.1 5.5.2.4 timekeeping data format time is kept in bcd or binary format, as determined by bit 2 (dm) of control register b (crb), and in either 12 or 24- hour format, as determined by bit 1 of this register. note: when changing the above formats, re-initialize all the time registers. daylight saving daylight saving time exceptions are handled automatically, as described in table 5-20 on page 127. leap years leap year exceptions are han dled automatically by the internal calendar function. every four years, february is extended to 29 days. updating the time and calendar registers are updated once per sec- ond regardless of bit 7 (set) of crb. since the time and calendar registers are updated serially, unpredictable results may occur if they are accessed during the update. therefore, you must ensure t hat reading or writing to the time storage locations does not coincide with a system update of these locations. there are several methods to avoid this contention. method 1 1) set bit 7 of crb to 1. this takes a ?snapshot? of the internal time registers and loads them into the user copy registers. the user copy registers are seen when accessing the rtc from outside, and are part of the double buffering mechanism. you may keep this bit set for up to 1 second, since the time/calendar chain con- tinue to be updated once per second. 2) read or write the required registers (since bit 1 is set, you are accessing the user copy registers). if you per- form a read operation, the information you read is cor- rect from the time when bit 1 was set. if you perform a write operation, you write only to the user copy regis- ters. 3) reset bit 1 to 0. during the transition, the user copy registers update the internal registers, using the dou- ble buffering mechanism to ensure that the update is performed between two time updates. this mecha- nism enables new time parameters to be loaded in the rtc. method 2 1) access the rtc registers after detection of an update ended interrupt. this implies that an update has just been completed and 999 ms remain until the next update. 2) to detect an update ended interrupt, you may either: ? poll bit 4 of crc. ? use the following interrupt routine: ? set bit 4 of crb. ? wait for an interrupt from interrupt pin. ? clear the irqf flag of crc before exiting the interrupt routine. method 3 poll bit 7 of cra. the update occurs 244 s after this bit goes high. therefore, if a 0 is read, the time registers remain stable for at least 244 s. method 4 use a periodic interrupt routine to determine if an update cycle is in progress, as follows: 1) set the periodic interrupt to the desired period. 2) set bit 6 of crb to enable the interrupt from periodic interrupt. 3) wait for the periodic interrupt appearance. this indi- cates that the period represented by the following expression remains until another update occurs: [(period of periodic interrupt / 2) + 244 s] 5.5.2.5 alarms the timekeeping function can be set to generate an alarm when the current time reaches a stored alarm time. after each rtc time update (every 1 second), the seconds, min- utes, hours, date of month and month counters are com- pared with their corresponding registers in the alarm settings. if equal, bit 5 of crc is set. if the alarm interrupt enable bit was previously set (crb bit 5), interrupt request pin is also active. any alarm register may be set to ?unconditional match? by setting bits [7:6] to 11. this combination, not used by any bcd or binary time codes, results in a periodic alarm. the rate of this periodic alarm is determined by the registers that were set to ?unconditional match?. for example, if all but the seconds and minutes alarm reg- isters are set to ?unconditional match?, an interrupt is gen- erated every hour at the specifi ed minute and second. if all but the seconds, minutes and hours alarm registers are set to ?unconditional match?, an interrupt is generated every day at the specified hour, minute and second.
124 amd geode? sc3200 processor data book superi/o module revision 5.1 5.5.2.6 power supply the device is supplied from two supply voltages, as shown in figure 5-8: system standby power supply voltage, v sb backup voltage, from low capacity lithium battery a standby voltage, v sb , from the external ac/dc power supply powers the rtc under normal conditions. figure 5-9 represents a typical battery configuration. no external diode is required to meet the ul standard, due to the internal switch and internal serial resistor r ul . figure 5-8. power supply connections figure 5-9. typical battery configuration the rtc is supplied from one of two power supplies, v sb or v bat , according to their levels. an internal voltage com- parator delivers the control signals to a pair of switches. battery backup voltage v bat maintains the correct time and saves the cmos memory when the v sb voltage is absent, due to power failure or disconnection of the external ac/dc input power supply or v sb main battery. to assure that the module uses power from v sb and not from v bat , the v sb voltage should be maintained above its minimum, as detailed in sect ion 9.0 "electrical specifica- tions" on page 369. the actual voltage point where the module switches from v bat to v sb is lower than the minimum workable battery voltage, but high enough to guarantee the correct function- ality of the oscillator and the cmos ram. figure 5-10 shows typical battery current consumption dur- ing battery-backed operation, and figure 5-11 during nor- mal operation. figure 5-10. typical battery current: battery backed power mode @ t c = 25c figure 5-11. typical battery current: normal operation mode rtc power backup v digital v sb v digital v sb v bat battery external ac power supply v digital sense v sb v bat v sb pc0 v bat onctl# onctl# acpi controller v bat 0.1 f v sb v sb c f c f bt 1 0.1 f v pp r ul v ref rtc note: place a 0.1 f capacitor on each v sb , v sbl power supply pin as close as possible to the pin, and also on v bat . v sbl c f 0.1 f v sbl i bat ( a) 10.0 7.5 5.0 2.5 2.4 3.0 3.6 v bat (v) i bat ( a) 0.75 0.50 0.25 3.0 3.3 3.6 v sb note: battery voltage in this test is 3.0v. (v)
amd geode? sc3200 processor data book 125 superi/o module revision 5.1 5.5.2.7 system power states the system power state may be no power, power on, power off or power failure. table 5-18 indicates the power-source combinations for each state. no other power-source combinations are valid. in addition, the power sources and distribution for the entire system are illustrated in figure 5-8 on page 124. no power this state exists when no external or battery power is con- nected to the device. this condition does not occur once a backup battery has been connected, except in the case of a malfunction. power on this is the normal state when the system is active. this state may be initiated by various events in addition to the normal physical switching on of the system. in this state, the system power supply is powered by external ac power and produces v digital and v sb . the system and the part are powered by v digital, with the exception of the rtc log- ical device, which is powered by v sb. power off (suspended) this is the normal state when the system has been switched off and is not required to be active, but is still con- nected to a live external ac input power source. this state may be initiated directly or by software. the system is pow- ered down. the rtc logical device remains active, pow- ered by v sb . power failure this state occurs when the external power source to the system stops supplying power, due to disconnection or power failure on the external ac input power source. the rtc continues to maintain timekeeping and ram data under battery power (v bat ), unless the oscillator stop bit was set in the rtc. in this ca se, the oscillator stops func- tioning if the system goes to battery power, and timekeep- ing data becomes invalid. system bus lockout during power on or power off, spurious bus transactions from the host may occur. to protect the rtc internal regis- ters from corruption, all inputs are automatically locked out. the lockout condition is asserted when v sb is lower than v sbon . power-up detection when system power is restored after a power failure or power off state (v sb = 0), the lockout condition continues for a delay of 62 ms (minimu m) to 125 ms (maximum) after the rtc switches from battery to system power. the lockout condition is switched off immediately in the fol- lowing situations: if the divider chain control bi ts, dv[2:0], (cra bits [6:4]) specify a normal operation mode (01x or 100), all input signals are enabled immediately upon detection of system voltage above v sbon . when battery voltage is below v batdct and hmr is 1, all input signals are enabled immediately upon detection of system voltage above v sbon . this also initializes registers at offsets 00h through 0dh. if bit 7 (vrt) of crd is 0, all input signals are enabled immediately upon detection of system voltage above v sbon . 5.5.2.8 oscillat or activity the rtc oscillator is active if: v sb power supply is higher than v sbon , independent of the battery voltage, v bat -or- v bat power supply is higher than v batmin , regardless if v sb is present or not. the rtc oscillator is disabled if: during power-down (v bat only), the battery voltage drops below v batmin . when this occurs, the oscillator may be disabled and its functionality cannot be guaran- teed. -or- software wrote 00x to dv[2:0] bits of the cra register and v sb is removed. this disables the oscillator and decreases the power consumption from the battery connected to v bat . when disabling the oscillator, the cmos ram is not affected as long as the battery is present at a correct voltage level. if the rtc oscillator becomes inactive, the following fea- tures are dysfunctional/disabled: timekeeping. periodic interrupt. alarm. table 5-18. system power states v digital v sb v bat power state ??? no power ?? + power failure ? + + or - power off + + + or - power on
126 amd geode? sc3200 processor data book superi/o module revision 5.1 5.5.2.9 interrupt handling the rtc has a single interrupt request line which handles the following three interrupt conditions: periodic interrupt. alarm interrupt. update end interrupt. the interrupts are generated if the respective enable bits in the crb register are set prior to an interrupt event occur- rence. reading the crc register clears all interrupt flags. thus, when multiple interrupts are enabled, the interrupt service routine should first read and store the crc regis- ter, and then deal with all pending interrupts by referring to this stored status. if an interrupt is not serviced before a second occurrence of the same interrupt condition, the second interrupt event is lost. figure 5-12 illustrates the interrupt timing in the rtc. figure 5-12. interrupt/status timing 5.5.2.10 battery-backe d rams and registers the rtc has two battery-backed rams and 17 registers, used by the logical units themselves. battery-backup power enables information retention during system power down. the rams are: standard ram extended ram the memory maps and register content of the rams is provided in section 5.5.4 "rtc general-purpose ram map" on page 131. the first 14 bytes and 3 programmable bytes of the stan- dard ram are overlaid by time, alarm data and control reg- isters. the remaining 111 bytes are general-purpose memory. registers with reserved bits should be written using the read-modify-write method. all register locations within th e device are accessed by the rtc index and data registers (at base address and base address+1). the index register points to the register loca- tion being accessed, and the data register contains the data to be transferred to or from the location. an additional 128 bytes of battery-backed ram (also called extended ram) may be accessed via a second pair of index and data registers. access to the two rams may be locked. for details see table 5-7 on page 115. 244 s bit 7 bit 4 bit 6 bit 5 a c of cra of crc of crc of crc p/2 p/2 30.5 s b p flags (and irq) are reset at the conclusion of crc read or by reset. a = update in progress bit high before update occurs = 244 s b = periodic interrupt to update = period (periodic int) / 2 + 244 s c = update to alarm interrupt = 30.5 s p = period is programmed by rs[3:0] of cra
amd geode? sc3200 processor data book 127 superi/o module revision 5.1 5.5.3 rtc registers the rtc registers can be acce ssed (see section 5.4.2.1 "ldn 00h - real-time clock" on page 114) at any time dur- ing normal operation mode (i.e.,when v sb is within the rec- ommended operation range). this access is disabled during battery-backed operation. the write operation to these registers is also disabled if bit 7 of the crd register is 0. note: before attempting to perform any start-up proce- dures, read about bit 7 (vrt) of the crd register. this section describes the rtc timing and control regis- ters that control basic rtc functionality. table 5-19. rtc register map index type name reset type 00h r/w sec. seconds register v pp pur 01h r/w seca. seconds alarm register v pp pur 02h r/w min. minutes register v pp pur 03h r/w mina. minutes alarm register v pp pur 04h r/w hor. hours register v pp pur 05h r/w hora. hours alarm register v pp pur 06h r/w dow. day of week register v pp pur 07h r/w dom. date of month register v pp pur 08h r/w mon. month register v pp pur 09h r/w yer. year register v pp pur 0ah r/w cra. rtc control register a bit specific 0bh r/w crb. rtc control register b bit specific 0ch ro crc. rtc control register c bit specific 0dh ro crd. rtc control register d v pp pur programmable 1 r/w doma. date of month alarm register v pp pur programmable 1 r/w mona. month alarm register v pp pur programmable 1 r/w cen. century register v pp pur 1. overlaid on ram bytes in range 0eh-7fh. see se ction 5.4.2.1 "ldn 00h - real-time clock" on page 114. table 5-20. rtc registers bit description index 00h seconds register - sec (r/w) reset type: v pp pur 7:0 seconds data. values may be 00 to 59 in bcd format or 00 to 3b in binary format. index 01h seconds alarm register - seca (r/w) reset type: v pp pur 7:0 seconds alarm data. values may be 00 to 59 in bcd format or 00 to 3b in binary format. when bits 7 and 6 are both set to one (? 11?), unconditional match is selected. index 02h minutes register - min (r/w) reset type: v pp pur 7:0 minutes data. values can be 00 to 59 in bcd format, or 00 to 3b in binary format.
128 amd geode? sc3200 processor data book superi/o module revision 5.1 index 03h minutes alarm register - mina (r/w) reset type: v pp pur 7:0 minutes alarm data. values can be 00 to 59 in bcd format, or 00 to 3b in binary format. when bits 7 and 6 are both set to 1, unconditional match is selected. see section 5.5.2.5 "alarms" on page 123 for more information about ?unconditional? matches. index 04h hours register - hor (r/w) reset type: v pp pur 7:0 hours data. for 12-hour mode, values can be 01 to 12 (am) and 81 to 92 (pm) in bcd format, or 01 to 0c (am) and 81 to 8c (pm) in binary format. for 24-hour mode, values can be 0- to 23 in bcd format or 00 to 17 in binary format. index 05h hours alarm register - hora (r/w) reset type: v pp pur 7:0 hours alarm data. for 12-hour mode, values may be 01 to 12 (am) and 81 to 92 (pm) in bcd format or 01 to 0c (am) and 81 to 8c (pm) in binary format. for 24-hour mode, values may be 0- to 23 in bcd format or 00 to 17 in binary format. when bits 7 and 6 are both set to one (? 11?), unconditional match is selected. index 06h day of week register - dow (r/w) reset type: v pp pur 7:0 day of week data. values may be 01 to 07 in bcd format or 01 to 07 in binary format. index 07h date of month regist er - dom (r/w) reset type: v pp pur 7:0 date of month data. values may be 01 to 31 in bcd format or 01 to 1f in binary format. index 08h month register - mon (r/w) reset type: v pp pur width: byte 7-0 month data. values may be 01 to 12 in bcd format or 01 to 0c in binary format. index 09h year register - yer (r/w) reset type: v pp pur 7:0 year data. values may be 00 to 99 in bcd format or 00 to 63 in binary format. index 0ah rtc control register a - cra (r/w) reset type: bit specific this register controls test selection, among other functions. this regist er cannot be written before reading bit 7 of crd. 7 update in progress. (ro) this bit is not affected by reset. this bit reads 0 when bit 7 of the crb register is 1. 0: timing registers not updated within 244 s. 1: timing registers updated within 244 s. 6:4 divider chain control. these bits control the configuration of the di vider chain for timing generation and register bank selection. see table 5-21 on page 130. they are cl eared to 000 as long as bit 7 of crd is 0. 3:0 periodic interrupt rate select. these bits select one of fifteen output taps from the clock divider chain to control the rate of the periodic interrupt. see table 5-22 on page 130 and figure 5- 7 on page 122. they are cleared to 000 as long as bit 7 of crd is 0. index 0bh rtc control register b - crb (r/w) reset type: bit specific 7 set mode. this bit is reset at v pp power-up reset only. 0: timing updates occur normally. 1: user copy of time is ?frozen?, allowing the time r egisters to be accessed whether or not an update occurs. 6 periodic interrupt. bits [3:0] of the cra register determine the rate at which this interrupt is generated. it is cleared to 0 on rtc reset (i.e., hardware or software reset) or when rtc is disable. 0: disable. 1: enable. 5 alarm interrupt. this interrupt is generated immediately after a time update in which the seconds, minutes, hours, date and month time equal their respective alarm c ounterparts. it is cleared to 0 as long as bit 7 of the crd register is reads 0. 0: disable. 1: enable. 4 update ended interrupt. this interrupt is generated when an update occurs. it is cleared to 0 on rtc reset (i.e., hardware or software reset) or when the rtc is disable. 0: disable. 1: enable. table 5-20. rtc registers (continued) bit description
amd geode? sc3200 processor data book 129 superi/o module revision 5.1 3 reserved. this bit is defined as ?square wave enable? by the mc146818 and is not supported by the rtc. this bit is always read as 0. 2 data mode. this bit is reset at v pp power-up reset only. 0: enable bcd format. 1: enable binary format. 1 hour mode. this bit is reset at v pp power-up reset only. 0: enable 12-hour format. 1: enable 24-hour format. 0 daylight saving. this bit is reset at v pp power-up reset only. 0: disable. 1: enable: - in the spring, time advances from1:59:59 am to 3:00:00 am on the first sunday in april. - in the fall, time returns from 1:59:59 am to 1:00:00 am on the last sunday in october. index 0ch rtc control register c - crc (ro) reset type: bit specific 7 irq flag. mirrors the value on the interrupt output signal. when interrupt is active, irqf is 1. to clear this bit (and deacti- vate the interrupt pin), read the crc register as the flag bi ts uf, af and pf are cleared after reading this register. 0: irq inactive. 1: logic equation is true: ((uie and uf) or (aie and af) or (pie and pf)). 6 periodic interrupt flag. cleared to 0 on rtc reset (i.e., hardware or softwa re reset) or the rtc disabled. in addition, this bit is cleared to 0 when this register is read. 0: no transition occurred on the selected tap since the last read. 1: transition occurred on the selected tap of the divider chain. 5 alarm interrupt flag. cleared to 0 as long as bit 7 of the crd register is reads 0. in addition, this bit is cleared to 0 when this register is read. 0: no alarm detected since the last read. 1: alarm condition detected. 4 update ended interrupt flag. cleared to 0 on rtc reset (i.e., hardware or so ftware reset) or the rtc disabled. in addi- tion, this bit is cleared to 0 when this register is read. 0: no update occurred since the last read. 1: time registers updated. 3:0 reserved. index 0dh rtc control register d - crd (ro) reset type: v pp pur 7 valid ram and time. this bit senses the voltage that feeds the rtc (v sb or vbat) and indicates whether or not it was too low since the last time this bit was read. if it was too lo w, the rtc contents (time/cal endar registers and cmos ram) is not valid. 0: the voltage that feeds the rtc was too low. 1: rtc contents (time/calendar regi sters and cmos ram) are valid. 6:0 reserved. index programmable date of month alarm register - doma (r/w) reset type: v pp pur 7:0 date of month alarm data . values may be 01 to 31 in bcd format or 01 to 1f in binary format. when bits 7 and 6 are both set to one (?11?), unconditional match is selected. (default) index programmable month alarm re gister - mona (r/w) reset type: v pp pur 7:0 month alarm data. values may be 01 to 12 in bcd format or 01 to 0c in binary format. when bits 7 and 6 are both set to one (?11?), unconditional match is selected. (default) index programmable century regi ster - cen (r/w) reset type: v pp pur 7:0 century data. values may be 00 to 99 in bcd format or 00 to 63 in binary format. table 5-20. rtc registers (continued) bit description
130 amd geode? sc3200 processor data book superi/o module revision 5.1 table 5-21. divider chain control / test selection dv2 dv1 dv0 configuration cra6 cra5 cra4 0 0 x oscillator disabled 0 1 0 normal operation 011test 10x 1 1 x divider chain reset table 5-22. periodic interrupt rate encoding rate select 3 2 1 0 periodic interrupt rate (ms) divider chain output 0 0 0 0 no interrupts 0 0 0 1 3.906250 7 0 0 1 0 7.812500 8 0 0 1 1 0.122070 2 0 1 0 0 0.244141 3 0 1 0 1 0.488281 4 0 1 1 0 0.976562 5 0 1 1 1 1.953125 6 1 0 0 0 3.906250 7 1 0 0 1 7.812500 8 1 0 1 0 15.625000 9 1 0 1 1 31.250000 10 1 1 0 0 62.500000 11 1 1 0 1 125.000000 12 1 1 1 0 250.000000 13 1 1 1 1 500.000000 14 table 5-23. bcd and binary formats parameter bcd format binary format seconds 00 to 59 00 to 3b minutes 00 to 59 00 to 3b hours 12-hour mode: 01 to 12 (am) 81 to 92 (pm) 24-hour mode: 00 to 23 12-hour mode: 01 to 0c (am) 81 to 8c (pm) 24-hour mode: 00 to 17 day 01 to 07 (sunday = 01) 01 to 07 date 01 to 31 01 to 1f month 01 to 12 (january = 01) 01 to 0c year 00 to 99 00 to 63 century 00 to 99 00 to 63
amd geode? sc3200 processor data book 131 superi/o module revision 5.1 5.5.3.1 usage hints 1) read bit 7 of crd at each system power-up to vali- date the contents of the rtc registers and the cmos ram. when this bit is 0, the contents of these regis- ters and the cmos ram are questionable. this bit is reset when the backup battery voltage is too low. the voltage level at which this bit is reset is below the mini- mum recommended battery voltage, 2.4v. although the rtc oscillator may function properly and the regis- ter contents may be correct at lower than 2.4v, this bit is reset since correct functionality cannot be guaran- teed. system bios may use a checksum method to revalidate the contents of the cmos-ram. the check- sum byte should be stored in the same cmos ram. 2) change the backup battery while normal operating power is present, and not in backup mode, to maintain valid time and register information. if a low leakage capacitor is connected to v bat , the battery may be changed in backup mode. 3) a rechargeable nicd battery may be used instead of a non-rechargeable lithium battery. this is a preferred solution for portable systems, where small size com- ponents is essential. 4) a supercap capacitor may be used instead of the nor- mal lithium battery. in a portable system usually the v sb voltage is always present since the power man- agement stops the system before its voltage falls to low. the supercap capacitor in the range of 0.047- 0.47 f should supply the power during the battery replacement. 5.5.4 rtc general-purpose ram map table 5-24. standard ram map index description 0eh - 7fh battery-backed general-purpose 111- byte ram. table 5-25. extended ram map index description 00h - 7fh battery-backed general-purpose 128- byte ram.
132 amd geode? sc3200 processor data book superi/o module revision 5.1 5.6 system wakeup control (swc) the swc wakes up the system by sending a power-up request to the acpi controller in response to the following maskable system events: modem ring (ri2#) audio codec event (sdata_in2) programmable consumer electronics ir (ceir) address each system event that is moni tored by the swc is fed into a dedicated detector that decides when the event is active, according to predetermined (either fixed or programmable) criteria. a set of dedicated registers is used to determine the wakeup criteria, including the ceir address. a wakeup events status register (wksr) and a wakeup events control register (wkcr) hold a status bit and enable bit, respectively, for each possible wakeup event. upon detection of an active event, the corresponding sta- tus bit is set to 1. if the even t is enabled (the corresponding enable bit is set to 1), a power-up request is issued to the acpi controller. in addition, detection of an active wakeup event may be also routed to an arbitrary irq. disabling an event prevents it from issuing power-up requests, but does not affect the status bits. a power-up reset is issued to the acpi controller when both the status and enable bits are set to 1 for at least one event type. swc logic is powered by v sb . the swc control and con- figuration registers are battery backed, powered by v pp . the setup of the wakeup events, including programmable sequences, is retained throughout power failures (no v sb ) as long as the battery is connected. v pp is taken from v sb if v sb > 2.0; otherwise, v bat is used as the v pp source. hardware reset does not affe ct the swc registers. they are reset only by a sio software reset or power-up of v pp . 5.6.1 event detection 5.6.1.1 audio codec event a low-to-high transition on sdata_in2 indicates the detec- tion of an audio codec event and can be used as a wakeup event. 5.6.1.2 ceir address a ceir transmission received on irrx1 in a pre-selected standard (nec, rca or rc-5) is matched against a pro- grammable ceir address. detection of matching can be used as a wakeup event. the ceir address detection operates independently of the serial port with the ir (which is powered down with the rest of the system). whenever an ir signal is detected, the receiver immedi- ately enters the active state. when this happens, the receiver keeps sampling the ir input signal and generates a bit string where a logic 1 indicates an idle condition and a logic 0 indicates the presence of ir energy. the received bit string is de-serialized and assembled into 8-bit charac- ters. the expected ceir protocol of the received signal should be configured through bits [5:4] of the ceir wakeup con- trol register (irwcr) (see table 5-30 on page 135). the ceir wakeup address register (irwad) holds the unique address to be compared with the address contained in the incoming ceir message. if ceir is enabled (irwcr[0] = 1) and an address match occurs, then the ceir event status bit of wksr is set to 1. the ceir address shift register (adsr) holds the received address which is compared with the address con- tained in the irwad. the comparison is affected also by the ceir wakeup address mask register (irwam) in which each bit determines whether to ignore the corre- sponding bit in the irwad. if ceir routing to interrupt request is enabled, the assigned swc interrupt request can be used to indicate that a com- plete address has been received. to get this interrupt when the address is completely received, irwam should be writ- ten with ffh. once the interrupt is received, the value of the address can be read from adsr. another parameter that is us ed to determine whether a ceir signal is to be considered valid is the bit cell time width. there are four time ranges for the different protocols and carrier frequencies. four pairs of registers (irwtrxl and irwtrxh) define the low and high limits of each time range. table 5-26 lists the recommended time ranges lim- its for the different protocols and their applicable ranges. the values are represented in hexadecimal code where the units are of 0.1 ms. table 5-26. time range limits for ceir protocols time range rc-5 nec rca low limit high limit low limit high limit low limit high limit 0 10h 14h 09h 0dh 0ch 12h 1 07h 0bh 14h 19h 16h 1ch 2 - - 50h 64h b4h dch 3 - - 28h 32h 23h 2dh
amd geode? sc3200 processor data book 133 superi/o module revision 5.1 5.6.2 swc registers the swc registers are organized in two banks. the offsets are related to a base address that is determined by the swc base address register in the logical device configu- ration. the lower three registers are common to the two banks while the upper registers (03h-0fh) are divided as follows: bank 0 holds reserved registers. bank 1 holds the ceir control registers. the active bank is selected through the configuration bank select field (bits [1:0]) in the wakeup configuration regis- ter (wkcfg). see table 5-29 on page 134. the tables that follow provide register maps and bit defini- tions for banks 0 and 1. table 5-27. banks 0 and 1 - common control and status register map offset type name reset value 00h r/w1c wksr. wakeup events status register 00h 01h r/w wkcr. wakeup events control register 03h 02h r/w wkcfg. wakeup configuration register 00h table 5-28. bank 1 - ceir wakeup configuration and control register map offset type name reset value 03h r/w irwcr. ceir wakeup control register 00h 04h --- rsvd. reserved --- 05h r/w irwad. ceir wakeup address register 00h 06h r/w irwam. ceir wakeup address mask register e0h 07h ro adsr. ceir address shift register 00h 08h r/w irwtr0l. ceir wakeup, range 0, low limit register 10h 09h r/w irwtr0h. ceir wakeup, range 0, high limit register 14h 0ah r/w irwtr1l. ceir wakeup, range 1, low limit register 07h 0bh r/w irwtr1h. ceir wakeup, range 1, high limit register 0bh 0ch r/w irwtr2l. ceir wakeup, range 2, low limit register 50h 0dh r/w irwtr2h. ceir wakeup, range 2, high limit register 64h 0eh r/w irwtr3l. ceir wakeup, range 3, low limit register 28h 0fh r/w irwtr3h. ceir wakeup, range 3, high limit register 32h
134 amd geode? sc3200 processor data book superi/o module revision 5.1 table 5-29. banks 0 and 1 - common control and status registers bit description offset 00h wakeup events status regist er - wksr (r/w1c) reset value: 00h this register is set to 00h on power-up of v pp or software reset. it indicates which wakeup event and/or pme occurred. (see section 6.2.9.4 "power management events" on page 176.) 7 reserved. 6 reserved. must be set to 0. 5 irrx1 (ceir) event status. this sticky bit shows the status of the ceir event detection. 0: event not detected. (default) 1: event detected. 4:2 reserved. 1 ri2# event status. this sticky bit shows the status of ri2# event detection. 0: event not detected. (default) 1: event detected. 0 sdata_in2 event status. this sticky bit shows the status of audio codec event detection. 0: event not detected. (default) 1: event detected. offset 01h wakeup events control register - wkcr (r/w) reset value: 03h this register is set to 03h on power-up of v pp or software reset. detected wakeup events that are enabled issue a power-up request the acpi controller and/or a pme to the core logic module. (see section 6.2.9.4 "power management events" on page 176.) 7 reserved. 6 reserved. must be set to 0. 5 irrx1 (ceir) event enable. 0: disable. (default) 1: enable. 4:2 reserved. 1 ri2# event enable. 0: disable. 1: enable. (default) 0 sdata_in2 event enable. 0: disable. 1: enable. (default) offset 02h wakeup configuration regist er - wkcfg (r/w) reset value: 00h this register is set to 00h on power-up of v pp or software reset. it enables access to ceir registers. 7:5 reserved. 4 reserved. must be set to 0. 3 reserved. must be set to 0. 2 reserved. 1:0 configuration bank select bits. 00: only shared regist ers are accessible. 01: shared registers and bank 1 (c eir) registers are accessible. 10: bank selected. 11: reserved.
amd geode? sc3200 processor data book 135 superi/o module revision 5.1 table 5-30. bank 1 - ceir wakeup configuration and control registers bit description bank 1, offset 03h ceir wakeup control register - irwcr (r/w) reset value: 00h this register is set to 00h on power-up of v pp or software reset. 7:6 reserved. 5:4 ceir protocol select. 00: rc5 01: nec/rca 1x: reserved 3 reserved. 2 invert irrx input. 0: not inverted. (default) 1: inverted. 1 reserved. 0 ceir enable. 0: disable. (default) 1: enable. bank 1, offset 04h reserved bank 1, offset 05h ceir wakeup address register - irwad (r/w) reset value: 00h this register defines the station address to be compared with the address contained in the incoming ceir message. if ceir is en abled (bit 0 of the irwcr register is 1) and an address match occurs, then bit 5 of the wksr register is set to 1. this register is set to 00h on power-up of v pp or software reset. 7:0 ceir wakeup address bank 1, offset 06h ceir wakeup mask register - irwam (r/w) reset value: e0h each bit in this register determines whether the corresponding bi t in the irwad register takes part in the address comparison. bits 5, 6, and 7 must be set to 1 if the rc-5 protocol is selected. this register is set to e0h on power-up of v pp or software reset. 7:0 ceir wakeup address mask. if the corresponding bit is 0, the address bit is not masked (enabled for compare). if the corresponding bit is 1, the addres s bit is masked (ignored during compare). bank 1, offset 07h ceir address shift register - adsr (ro) reset value: 00h this register holds the received address to be compar ed with the address contained in the irwad register. this register is set to 00h on power-up of v pp or software reset. 7:0 ceir address. ceir wakeup range 0 registers these two registers (irwtr0l and irwtr0h) define the low and high limits of time range 0 (see table 5-26 on page 132). the value s are represented in units of 0.1 ms. rc-5 protocol: the bit cell width must fall within this rang e for the cell to be considered valid. the nominal cell width is 1. 778 ms for a 36 khz carrier. irwtr0l and irwtr0h should be set to 10h and 14h, respectively. (default) nec protocol: the time distance between two consecutive ceir pulse s that encodes a bit value of 0 must fall within this range. the nominal distance for a 0 is 1.125 ms for a 38 khz carrier. irwtr0l and irwtr0h should be set to 09h and 0dh, respectively. bank 1, offset 08h irwtr0l register (r/w) reset value: 10h this register is set to 10h on power-up of v pp or software reset. 7:5 reserved. 4:0 ceir pulse change, range 0, low limit. bank 1, offset 09h irwtr0h register (r/w) reset value: 14h this register is set to 14h on power-up of v pp or software reset. 7:5 reserved. 4:0 ceir pulse change, range 0, high limit.
136 amd geode? sc3200 processor data book superi/o module revision 5.1 ceir wakeup range 1 registers these two registers (irwtr1l and irwtr1h) define the low and high limits of time range 1 (see table 5-26 on page 132). the valu es are represented in units of 0.1 ms. rc-5 protocol: the pulse width defining a half-bit cell must fall within this range in order for the cell to be considered vali d. the nominal pulse width is 0.889 for a 38 khz carrier. irwtr1l and irwtr1h should be set to 07h and 0bh, respectively. (default) nec protocol: the time between two consecutive ceir pulses that encodes a bit value of 1 must fall within this range. the nomin al time for a 1 is 2.25 ms for a 36 khz carrier. irwtr 1l and irwtr1h should be set to 14h and 19h, respectively. bank 1, offset 0ah irwtr1l register (r/w) reset value: 07h this register is set to 07h on power-up of v pp or software reset. 7:5 reserved. 4:0 ceir pulse change, range 1, low limit. bank 1, offset 0bh irwtr1h register (r/w) reset value: 0bh this register is set to 0bh on power-up of v pp or software reset. 7:5 reserved. 4:0 ceir pulse change, range 1, high limit. ceir wakeup range 2 registers these two registers (irwtr2l and irwtr2h) define the low and high limits of time range 2 (see table 5-26 on page 132). the valu es are represented in units of 0.1 ms. rc-5 protocol: these registers are not used when the rc-5 protocol is selected. nec protocol: the header pulse width must fall within this r ange in order for the header to be considered valid. the nominal va lue is 9 ms for a 38 khz carrier. irwtr2l and irwtr2h should be set to 50h and 64h, respectively. (default) bank 1, offset 0ch irwtr2l register (r/w) reset value: 50h this register is set to 50h on power-up of v pp or software reset. 7:0 ceir pulse change, range 2, low limit. bank 1, offset 0dh irwtr2h register (r/w) reset value: 64h this register is set to 64h on power-up of v pp or software reset. 7:0 ceir pulse change, range 2, high limit. ceir wakeup range 3 registers these two registers (irwtr3l and irwtr3h) define the low and high limits of time range 3 (see table 5-26 on page 132). the valu es are represented in units of 0.1 ms. rc-5 protocol: these registers are not used when the rc-5 protocol is selected. nec protocol: the post header gap width must fa ll within this range in order for the gap to be considered valid. the nominal va lue is 4.5 ms for a 36 khz carrier. irwtr3l and irwtr3h should be set to 28h and 32h, respectively. (default) bank 1, offset 0eh irwtr3l re gister (r/w) reset value: 28h this register is set to 28h on power-up of v pp or software reset. 7:0 ceir pulse change, range 3, low limit. bank 1, offset 0fh irwtr3h register (r/w) reset value: 32h this register is set to 32h on power-up of v pp or software reset. 7:0 ceir pulse change, range 3, high limit. table 5-30. bank 1 - ceir wakeup configuration and control registers (continued) bit description
amd geode? sc3200 processor data book 137 superi/o module revision 5.1 5.7 access.bus interface the sc3200 has two access.bus (acb) controllers. acb is a two-wire synchronous serial interface compatible with the access.bus physical layer, intel's smbus, and philips? i 2 c?. the acb can be configured as a bus master or slave, and can maintain bidirectional communication with both multiple master and slave devices. as a slave device, the acb may issue a request to become the bus master. the acb allows easy interfacing to a wide range of low- cost memories and i/o devices, including: eeproms, srams, timers, adc, dac, clock chips and peripheral driv- ers. the access.bus protocol uses a two-wire interface for bidirectional communication between the ics connected to the bus. the two interface lines are the serial data line (ab1d and ab2d) and the serial clock line (ab1c and ab2c). (here after referred to as abd and abc unless oth- erwise specified.) these lines should be connected to a positive supply via an internal or external pull-up resistor, and remain high even when the bus is idle. each ic has a unique address and can operate as a trans- mitter or a receiver (though some peripherals are only receivers). during data transactions, the master device initiates the transaction, generates the clock signal and terminates the transaction. for example, when the acb initiates a data transaction with an attached access.bus compliant peripheral, the acb becomes the master. when the periph- eral responds and transmits dat a to the acb, their master/ slave (data transaction initiator and clock generator) rela- tionship is unchanged, even though their transmitter/ receiver functions are reversed. this section describes the general acb functional block. a device may include a different implementation. for device specific implementation, s ee section 5.4.2.5 "ldn 05h and 06h - access.bus ports 1 and 2" on page 119. 5.7.1 data transactions one data bit is transferred during each clock pulse. data is sampled during the high state of the serial clock (abc). consequently, throughout the clock?s high period, the data should remain stable (see figure 5-13). any changes on the abd line during the high state of the abc and in the middle of a transaction aborts the current transaction. new data should be sent during the low abc state. this protocol permits a single data line to transfer both command/control information and data, using the synchronous serial clock. each data transaction is composed of a start condition, a number of byte transfers (set by the software) and a stop condition to terminate the transaction. each byte is trans- ferred with the most significant bit first, and after each byte (8 bits), an acknowledge signal must follow. the following sections provide further details of this process. during each clock cycle, the slave can stall the master while it handles the previous data or prepares new data. this can be done for each bit transferred, or on a byte boundary, by the slave holding abc low to extend the clock-low period. typically, slaves extend the first clock cycle of a transfer if a byte read has not yet been stored, or if the next byte to be transmitted is not yet ready. some microcontrollers, with limited hardware support for access.bus, extend the access after each bit, thus allow- ing the software to handle this bit. figure 5-13. bit transfer 5.7.2 start and stop conditions the access.bus master generates start and stop condi- tions (control codes). after a start condition is generated, the bus is considered busy and retains this status for a cer- tain time after a stop condition is generated. a high-to-low transition of the data line (abd) while the clock (abc) is high indicates a start condition. a low-to-high transition of the abd line while the abc is high indicates a stop condi- tion (figure 5-14). in addition to the first start condition, a repeated start condition can be generated in the middle of a transaction. this allows another device to be accessed, or a change in the direction of data transfer. figure 5-14. start and stop conditions abd abc data line stable: data valid change of data allowed abd abc s p start condition stop condition
138 amd geode? sc3200 processor data book superi/o module revision 5.1 5.7.3 acknowledge (ack) cycle the ack cycle consists of two signals: the ack clock pulse sent by the master with each byte transferred, and the ack signal sent by the receiving device (see figure 5-15). the master generates the ack clock pulse on the ninth clock pulse of the byte transfer. the transmitter releases the abd line (permits it to go high) to allow the receiver to send the ack signal. the receiver must pull down the abd line during the ack clock pulse, signalling that it has cor- rectly received the last data by te and is ready to receive the next byte. figure 5-16 illustrates the ack cycle. figure 5-15. access.bus data transaction figure 5-16. access.bus acknowledge cycle s p start condition stop condition abd abc msb ack ack 12 3 - 6 7 8 9 1 23 - 8 9 acknowledge signal from receiver byte complete interrupt within receiver clock line held low by receiver while interrupt is serviced s start condition abc 12 3 - 6 7 8 9 transmitter stays off bus during acknowledge clock acknowledge signal from receiver data output by transmitter data output by receiver
amd geode? sc3200 processor data book 139 superi/o module revision 5.1 5.7.4 acknowledge after every byte rule according to this rule, the master generates an acknowl- edge clock pulse after each byte transfer, and the receiver sends an acknowledge signal after every byte received. there are two exceptions to this rule: when the master is the receiver, it must indicate to the transmitter the end of data by not acknowledging (nega- tive acknowledge) the last byte clocked out of the slave. this negative acknowledge still includes the acknowl- edge clock pulse (generated by the master), but the abd line is not pulled down. when the receiver is full, otherwise occupied, or a problem has occurred, it sends a negative acknowledge to indicate that it cannot accept additional data bytes. 5.7.5 addressing transfer formats each device on the bus has a unique address. before any data is transmitted, the master transmits the address of the slave being addressed. the slave device should send an acknowledge signal on the abd line, once it recognizes its address. the address consists of the first 7 bits after a start condi- tion. the direction of the data transfer (r/w#) depends on the bit sent after the address, the eighth bit. a low-to-high transition during a abc high period indicates the stop con- dition, and ends the transaction of abd (see figure 5-17). when the address is sent, eac h device in the system com- pares this address with its own. if there is a match, the device considers itself addressed and sends an acknowl- edge signal. depending on the state of the r/w# bit (1 = read, 0 = write), the device acts either as a transmitter or a receiver. the i 2 c bus protocol allows a general call address to be sent to all slaves connected to the bus. the first byte sent specifies the general call address (00h) and the second byte specifies the meaning of the general call (for example, write slave address by softwa re only). those slaves that require data acknowledge the call, and become slave receivers; other slaves ignore the call. 5.7.6 arbitration on the bus multiple master devices on the bus require arbitration between their conflicting bus access demands. control of the bus is initially determined according to address bits and clock cycle. if the masters are trying to address the same slave, data comparisons determine the outcome of this arbitration. in master mode, the device immediately aborts a transaction if the value sampled on the abd line differs from the value driven by the device. (an exception to this rule is abd while receiving data. the lines may be driven low by the slave without causing an abort.) the abc signal is monitored for clock synchronization and to allow the slave to stall the bus. the actual clock period is set by the master with the longest clock period, or by the slave stall period. the clock high period is determined by the master with the shortest clock high period. when an abort occurs during the address transmission, a master that identifies the conflict should give up the bus, switch to slave mode and cont inue to sample abd to check if it is being addressed by the winning master on the bus. 5.7.7 master mode requesting bus mastership an access.bus transaction starts with a master device requesting bus mastership. it asserts a start condition, fol- lowed by the address of the device it wants to access. if this transaction is successful ly completed, the software may assume that the device has become the bus master. for the device to become the bus master, the software should perform the following steps: 1) configure acbctl1[2] to the desired operation mode. (polling or interrupt) and set the acbctl1[0]. this causes the acb to issue a start condition on the access.bus when the access.bus becomes free (acbcst[1] is cleared, or other conditions that can delay start). it then stalls the bus by holding abc low. 2) if a bus conflict is detected (i.e., another device pulls down the abc signal), the acbst[5] is set. 3) if there is no bus conflic t, acbst[1] and acbst[6] are set. 4) if the acbctl1[2] is set and either acbst[5] or acbst[6] is set, an interrupt is issued. figure 5-17. a complete ac cess.bus data transaction s p start condition stop condition abd abc 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 address r/w ack data ack data ack
140 amd geode? sc3200 processor data book superi/o module revision 5.1 sending the address byte when the device is the active master of the access.bus (acbst[1] is set), it can send the address on the bus. the address sent should not be the device?s own address, as defined by acbaddr[6:0] if acbaddr[7] is set, nor should it be the global call address if acbst[3] is set. to send the address byte, use the following sequence: 1) for a receive transaction where the software wants only one byte of data, it should set acbctl1[4]. if only an address needs to be sent or if the device requires stall for some other reason, set acbctl1[7]. 2) write the address byte (7-bit target device address) and the direction bit to the acbsda register. this causes the acb to generate a transaction. at the end of this transaction, the acknowledge bit received is copied to acbst[4]. during the transaction, the abd and abc lines are continuously checked for conflict with other devices. if a confli ct is detected, the transac- tion is aborted, acbst[5] is set and acbst[1] is cleared. 3) if acbctl1[7] is set and the transaction was success- fully completed (i.e., both acbst[5] and acbst[4] are cleared), acbst[3] is set. in this case, the acb stalls any further access.bus operations (i.e., holds abc low). if acbctl1[2] is set, it also sends an interrupt request to the host. 4) if the requested direction is transmit and the start transaction was completed su ccessfully (i.e., neither acbst[5] nor acbst[4] is set, and no other master has accessed the device), acbst[6] is set to indicate that the acb awaits attention. 5) if the requested direction is receive, the start transac- tion was completed successfully and acbctl1[7] is cleared, the acb starts receiving the first byte auto- matically. 6) check that both acbst[5] and acbst[4] are cleared. if acbctl1[2] is set, an interrupt is generated when acbst[5] or acbst[4] is set. master transmit after becoming the bus master, the device can start trans- mitting data on the access.bus. to transmit a byte in an interrupt or polling controlled oper- ation, the software should: 1) check that both acbst[5] and acbst[4] are cleared, and that acbst[6] is set. if acbctl1[7] is set, also check that acbst[3] is cleared (and clear it if required). 2) write the data byte to be transmitted to the acbsda. when either acbst[5] or acbst [4] is set, an interrupt is generated. when the slave responds with a negative acknowledge, acbst[4] register is set and acbst[6] remains cleared. in this case, if acbctl1[2] register is set, an interrupt is issued. master receive after becoming the bus master, the device can start receiv- ing data on the access.bus. to receive a byte in an interrupt or polling operation, the software should: 1) check that acbst[6] is set and that acbst[5] is cleared. if acbctl1[7] is set, also check that the acbst[3] is cleared (and clear it if required). 2) set acbctl1[4] to 1, if the next byte is the last byte that should be read. this causes a negative acknowl- edge to be sent. 3) read the data byte from the acbsda. before receiving the last by te of data, set acbctl1[4]. 5.7.7.1 master stop to end a transaction, set the acbctl1[1] before clearing the current stall flag (i.e., acbst[6], acbst[4], or acbst[3]). this causes t he acb to send a stop condition immediately, and to clear acbctl1[1]. a stop condition may be issued only when the device is the active bus mas- ter (i.e., acbst[1] is set). master bus stall the acb can stall the access.bus between transfers while waiting for the host response. the access.bus is stalled by holding the ab1c signal low after the acknowl- edge cycle. note that this is interpreted as the beginning of the following bus operation. the user must make sure that the next operation is prepar ed before the flag that causes the bus stall is cleared. the flags that can cause a bus stall in master mode are: negative acknowledge after sending a byte (acbst[4] = 1). acbst[6] bit is set. acbctl1[7] = 1, after a successful start (acbst[3] = 1). repeated start a repeated start is performed when the device is already the bus master (acbst[1] is set). in this case, the access.bus is stalled and the acb awaits host handling due to: negative acknowledge (acbst[4] = 1), empty buffer (acbst[6] = 1) and/or a stall after start (acbst[3] 1). for a repeated start: 1) set \acbctl1[0] to 1. 2) in master receive mode, read the last data item from acbsda. 3) follow the address send sequence, as described pre- viously in "sending the address byte". if the acb was awaiting handling due to acbst[3] = 1, clear it only after writing the requested address and direction to acbsda.
amd geode? sc3200 processor data book 141 superi/o module revision 5.1 master error detection the acb detects illegal start or stop conditions (i.e., a start or stop condition within the data transfer, or the acknowledge cycle) and a conflict on the data lines of the access.bus. if an illegal condition is detected, acbst[5] is set, and master mode is exited (acbst[1] is cleared). bus idle error recovery when a request to become the active bus master or a restart operation fails, acbst[5] is set to indicate the error. in some cases, both the device and the other device may identify the failure and leave the bus idle. in this case, the start sequence may be incomplete and the access.bus may remain deadlocked. to recover from deadlock, use the following sequence: 1) clear acbst[5] and acbcst[1]. 2) wait for a timeout period to check that there is no other active master on the bus (i.e., acbcst[1] remains cleared). 3) disable, and re-enable the acb to put it in the non- addressed slave mode. this completely resets the functional block. at this point, some of the slaves may not identify the bus error. to recover, the acb becomes the bus master: it asserts a start condition, sends an address byte, then asserts a stop condition which synchronizes all the slaves. 5.7.8 slave mode a slave device waits in idle mo de for a master to initiate a bus transaction. whenever the acb is enabled and it is not acting as a master (i.e., acbst[1] is cleared), it acts as a slave device. once a start condition on the bus is detected, the device checks whether the address sent by the current master matches either: the acbaddr[6:0] value if acbaddr[7] = 1. or the general call address if acbctl1[5] 1. this match is checked even when acbst[1] is set. if a bus conflict (on abd or abc) is detected, acbst[5] is set, acbst[1] is cleared and the device continues to search the received message for a match. if an address match or a global match is detected: 1) the device asserts its abd pin during the acknowl- edge cycle. 2) acbcst[2] and acbst[2] are set. if acbst[0] = 1 (i.e., slave transmit mode) acbst[6] is set to indicate that the buffer is empty. 3) if acbctl1[2] is set, an interrupt is generated if both acbctl1[2] and acbctl16 are set. 4) the software then reads acbst[0] to identify the direction requested by the master device. it clears acbst[2] so future byte transfers are identified as data bytes. slave receive and transmit slave receive and transmit are performed after a match is detected and the data transfer direction is identified. after a byte transfer, the acb extends the acknowledge clock until the software reads or writes acbsda. the receive and transmit sequences are identical to those used in the mas- ter routine. slave bus stall when operating as a slave, the device stalls the access.bus by extending the first clock cycle of a trans- action in the following cases: acbst[6] is set. acbst[2] and acbctl1[6] are set. slave error detection the acb detects illegal start and stop conditions on the access.bus (i.e., a start or stop condition within the data transfer or the acknowledge cycle). when this occurs, acbst[5] is set and acbcst[3:2] are cleared, setting the acb as an unaddressed slave. 5.7.9 configuration abd and abc signals the abd and abc are open-drain signals. the device per- mits the user to define whether to enable or disable the internal pull-up of each of these signals. acb clock frequency the acb permits the user to set the clock frequency for the access.bus clock. the clock is set by the acbctl2[7:1], which determines the abc clock period used by the device. this clock low period may be extended by stall periods initi- ated by the acb or by another access.bus device. in case of a conflict with another bus master, a shorter clock high period may be forced by the other bus master until the conflict is resolved.
142 amd geode? sc3200 processor data book superi/o module revision 5.1 5.7.10 acb registers each functional block is associated with a logical device number (ldn) (see section 5.3.2 "banked logical device registers" on page 108). access.bus port 1 is assigned as ldn 05h and access.bus port 2 as ldn 06h. in addi- tion to the registers listed here, there are additional config- uration registers listed in se ction 5.4.2.5 "ldn 05h and 06h - access.bus ports 1 and 2" on page 119. table 5-31. acb register map offset type name reset value 00h r/w acbsda. acb serial data xxh 01h r/w acbst. acb status 00h 02h r/w acbcst. acb control status 00h 03h r/w acbctl1. acb control 1 00h 04h r/w acbaddr. acb own address xxh 05h r/w acbctl2. acb control 2 00h table 5-32. acb registers bit description offset 00h acb serial data register - acbsda (r/w) reset value: xxh 7:0 acb serial data. this shift register is used to transmit and receive data. the most significant bi t is transmitted (received) first, and the least significant bit is transmitted last. readi ng or writing to acbsda is allowed only when acbst[6] is set, or for repeated starts after setting the acbctl1[0]. an attempt to access the register in other cases may produce unpredict- able results. offset 01h acb status register - acbst (r/w) reset value: 00h this is a read register with a special clear. some of its bits may be cleared by software, as described below. this register ma intains the current acb status. on reset, and when the acb is disabled, acbst is cleared (00h). 7 slvstp (slave stop). (r/w1c) writing 0 to slvstp is ignored. 0: writing 1 or acb disabled. 1: stop condition detected after a slave transfer in which acbcst[2] or acbcst[3] was set. 6 sdast (sda status). (ro) 0: reading from acbsda during a receive, or when writing to it during a transmit. when acbctl1[0] is set, reading acb- sda does not clear sdast. this enables acb to send a repeated start in master receive mode. 1: sda data register awaiting data (transmit - master or slav e) or holds data that should be read (receive - master or slave). 5 ber (bus error). (r/w1c) writing 0 to this bit is ignored. 0: writing 1 or acb disabled. 1: start or stop condition detected during data transfer (i.e., st art or stop condition during the transfer of bits [8:2] and acknowledge cycle), or when an arbitration problem detected. 4 negack (negative acknowledge). (r/w1c) writing 0 to this bit is ignored. 0: writing 1 or acb disabled. 1: transmission not acknowledged on the ninth clock (i n this case, sdast (bit 6) is not set). 3 stastr (stall after start). (r/w1c) writing 0 to this bit is ignored. 0: writing 1 or acb disabled. 1: address sent successfully (i.e., a star t condition sent without a bus error, or negative acknowledge), if acbctl1[7] is set. this bit is ignored in slave mode. when stastr is set, it stalls the access.bus by pulling down the abc line, and suspends any further action on the bus (e.g., receive of first by te in master receive mode). in addition, if acbctl1[1] is set, it also causes the acb to send an interrupt.
amd geode? sc3200 processor data book 143 superi/o module revision 5.1 2 nmatch (new match). (r/w1c) writing 0 to this bit is ignored. if acbctl1[2] is set, an interrupt is sent when this bit is set. 0: software writes 1 to this bit. 1: address byte follows a start condition or a repeat ed start, causing a match or a global-call match. 1 master. (ro) 0: arbitration loss (ber, bit 5, is set) or recognition of a stop condition. 1: bus master request succeeded and master mode active. 0 xmit (transmit). (ro) direction bit. 0: master/slave transmit mode not active. 1: master/slave transmit mode active. offset 02h acb control status register - acbcst (r/w) reset value: 00h this register configures and co ntrols the acb functional block. it maintains the current acb status and controls several acb fu nctions. on reset and when the acb is disabled, the non-reserved bits of acbcst are cleared. 7:6 reserved. 5 tgabc (toggle abc line). (r/w) enables toggling the abc line during error recovery. 0: clock toggle completed. 1: when the abd line is low, writing 1 to this bit toggles the abc line for one cycle. writing 1 to tgabc while abd is high is ignored. 4 tsda (test abd line). (ro) reads the current value of the abd line. it c an be used while recovering from an error condi- tion in which the abd line is constantly pulled low by an out-of-sync slave. data written to this bit is ignored. 3 gcmtch (global call match). (ro) 0: start condition or repeated start and a stop conditi on (including illegal st art or stop condition). 1: in slave mode, acbctl1.gcmen is set and the address byte (the first byte transferred after a start condition) is 00h. 2 match (address match). (ro) 0: start condition or repeated start and a stop conditi on (including illegal st art or stop condition). 1: acbaddr[7] is set and the first 7 bits of the address byte (t he first byte transferred after a start condition) match the 7- bit address in acbaddr. 1 bb (bus busy). (r/w1c) 0: writing 1, acb disabled, or stop condition detected. 1: bus active (a low level on either abd or abc), or start condition. 0 busy. (ro) this bit should always be written 0. this bit indi cates the period between detecting a start condition and com- pleting receipt of the address byte. after this, the acb is either free or enters slave mode. 0: completion of any state below or acb disabled. 1: acb is in one of the following states: -generating a start condition -master mode (acbst[1] is set) -slave mode (acbcst[2] or acbcst[3] set). offset 03h acb control register 1 - acbctl1 (r/w) reset value: 00h 7 stastre (stall after start enable). 0: when cleared, acbst[3] can not be set. however, if acbst[3] is set, clearing stastre does not clear acbst[3]. 1: stall after start mechanism enabled, and ac b stalls the bus after the address byte. 6 nminte (new match interrupt enable). 0: no interrupt issued on a new match. 1: interrupt issued on a new match only if acbctl1[2] set. 5 gcmen (global call match enable). 0: global call match disabled. 1: global call match enabled. table 5-32. acb registers (continued) bit description
144 amd geode? sc3200 processor data book superi/o module revision 5.1 4 ack (acknowledge). this bit is ignored in transmit mode . when the device acts as a receiv er (slave or master), this bit holds the stop transmitting instruction that is transmitted during the next acknowledge cycle. 0: cleared after acknowledge cycle. 1: negative acknowledge issued on next received byte. 3 reserved. 2 inten (interrupt enable). 0: acb interrupt disabled. 1: acb interrupt enabled. an interrupt is generated in response to one of the following events: -detection of an address match (acbst[2] = 1) and acbctl1[6] = 1. -receipt of bus error (acbst[5] = 1). -receipt of negative acknowledge after sending a byte (acbst[4] = 1). -acknowledge of each transaction (same as the hardware set of the acbst[6]). -in master mode if acbctl1[7] = 1, after a successful start (acbst[3] = 1). -detection of a stop condition while in slave mode (acbst[7] = 1). 1 stop (stop). 0: automatically clear ed after stop issued. 1: setting this bit in master mode generates a stop c ondition to complete or abort current message transfer. 0 start (start). set this bit only when in master mode or when requesting master mode. 0: cleared after start condition sent or bus error (acbst[5] = 1) detected. 1: single or repeated start condition generated on the access.bus . if the device is not the active master of the bus (acbst[1] = 0), setting start generates a start condition when the access.bus becomes free (acbcst[1] = 0). an address transmission sequence should then be performed. if the device is the active master of the bus (acbst [1] = 1), setting start and then writing to acbsda generates a start condition. if a transmission is alr eady in progress, a repeated start condition is generated. this condition can be used to switch the direction of the data flow between the mast er and the slave, or to choos e another slave device without separating them with a stop condition. offset 04h acb own address register - acbaddr (r/w) reset value: xxh 7 saen (slave address enable). 0: acb does not check for an address match with acbaddr[6:0]. 1: acbaddr[6:0] holds a valid address and enables the match of addr to an incoming address byte. 6:0 addr (address). these bits hold the 7-bit device address of the sc 3200. when in slave mode, the first 7 bits received after a start condition are compared with this field (first bit received is compared wi th bit 6, and the last bit with bit 0). if the address field matches the received data and acbaddr[7] is 1, a match is declared. offset 05h acb control register 2 - acbctl2 (r/w) reset value: 00h this register enables/disables the functional block and determines the acb clock rate. 7:1 abcfrq (abc frequency). this field defines the abc period (low and high time) when the device serves as a bus mas- ter. the clock low and high times are defined as follows: tabcl = tabch = 2*abcfrq*tclk where tclk is the module input clock cycle, as defined in the section 5.2 "module architecture" on page 107. abcfrq can be programmed to values in the range of 0001000b through 1111111b. using any other value has unpredict- able results. 0 en (enable). 0: acb is disabled, acbctl1, acbst and acbcst registers are cleared, and clocks are halted. 1: acb is enabled. table 5-32. acb registers (continued) bit description
amd geode? sc3200 processor data book 145 superi/o module revision 5.1 5.8 legacy functional blocks this section briefly describes the following blocks that pro- vide legacy device functions: parallel port. (similar to parallel port in the national semiconductor pc87338.) serial port 1 and serial port 2 (sp1 and sp2), uart functionality for both sp1 and sp2. (similar to scc1 in the national semiconductor pc87338.) infrared communications port / serial port 3 function- ality. (similar to scc2 in the national semiconductor pc87338.) the description of each legacy block includes a general description, register maps, and bit maps. 5.8.1 parallel port the parallel port supports all ieee1284 standard commu- nication modes: compatibility (known also as standard or spp), bidirectional (known also as ps/2), fifo, epp (known also as mode 4) and ecp (with an optional extended ecp mode). 5.8.1.1 parallel port register and bit maps the parallel port register maps (table 5-33 and table 5- 34) are grouped according to first and second level offsets. epp and second level offset re gisters are available only when the base address is 8-byte aligned. parallel port functional block bit maps are shown in table 5-35 and table 5-36. table 5-33. parallel port register map for first level offset first level offset type name modes (ecr bits) 7 6 5 000h r/w datar. pp data 000 or 001 000h w afifo. ecp address fifo 011 001h ro dsr. status all modes 002h r/w dcr. control all modes 003h r/w addr. epp address 100 004h r/w data0. epp data port 0 100 005h r/w data1. epp data port 1 100 006h r/w data2. epp data port 2 100 007h r/w data3. epp data port 3 100 400h w cfifo. pp data fifo 010 400h r/w dfifo. ecp data fifo 011 400h r/w tfifo. test fifo 110 400h ro cnfga. configuration a 111 401h ro cnfgb. configuration b 111 402h r/w ecr. extended control all modes 403h r/w eir. extended index all modes 404h r/w edr. extended data all modes 405h r/w ear. extended auxiliary status all modes table 5-34. parallel port register map for second level offset second level offset type name 00h r/w control0. control register 0 02h r/w control2. control register 2 04h r/w control4. control register 4 05h r/w pp confg0. parallel port configuration register 0
146 amd geode? sc3200 processor data book superi/o module revision 5.1 table 5-35. parallel port bit map for first level offset offset name bits 76543210 000h datar data bits afifo address bits 001h dsr printer status ack# status pe status slct status err# status rsvd epp timeout status 002h dcr rsvd direction control interrupt enable pp input control printer ini- tialization control automatic line feed control data strobe control 003h addr epp device or register selection address bits 004h data0 epp device or r/w data 005h data1 epp device or r/w data 006h data2 epp device or r/w data 007h data3 epp device or r/w data 400h cfifo data bits 400h dfifo data bits 400h tfifo data bits 400h cnfga rsvd bit 7 of pp confg0 rsvd 401h cnfgb rsvd interrupt request value interrupt select rsvd dma channel select 402h ecr ecp mode control ecp inter- rupt mask ecp dma enable ecp inter- rupt ser- vice fifo full fifo empty 403h eir rsvd second level offset 404h edr data bits 405h ear fifo tag rsvd table 5-36. parallel port bit map for second level offset offset name bits 76543210 00h control0 rsvd dcr reg- ister live freeze bit rsvd epp time- out inter- rupt mask 02h control2 spp com- patibility channel address enable rsvd revision 1.7 or 1.9 select rsvd 04h control4 rsvd pp dma request inactive time rsvd pp dma request active time 05h pp confg0 bit 3 of cnfga demand dma enable ecp irq channel number pe inter- nal pu or pd ecp dma channel number
amd geode? sc3200 processor data book 147 superi/o module revision 5.1 5.8.2 uart functionality (sp1 and sp2) both sp1 and sp2 provide uart functionality. the generic sp1 and sp2 support serial data communication with remote peripheral device or modem using a wired inter- face. the functional blocks can function as a standard 16450, 16550, or as an extended uart. 5.8.2.1 uart mode register bank overview four register banks, each containing eight registers, control uart operation. all registers use the same 8-byte address space to indicate offsets 00h through 07h. the bsr regis- ter selects the active bank and is common to all banks. see figure 5-18. 5.8.2.2 sp1 and sp2 register and bit maps for uart functionality the tables in this subsection provide register and bit maps for banks 0 through 3. figure 5-18. uart mode register bank architecture bank 0 bank 1 bank 2 bank 3 offset 07h offset 06h offset 05h offset 04h lcr/bsr offset 02h offset 01h offset 00h common register throughout all banks 16550 banks table 5-37. bank 0 register map offset type name 00h ro rxd. receiver data port w txd. transmitter data port 01h r/w ier. interrupt enable 02h ro eir. event identification (read cycles) r/w fcr. fifo control (write cycles) 03h w lcr 1 . line control r/w bsr 1 . bank select 04h r/w mcr. modem/mode control 05h r/w lsr. link status 06h r/w msr. modem status 07h r/w spr. scratchpad r/w ascr. auxiliary status and control 1. when bit 7 of this register is set to 1, bits [6 :0] of bsr select the bank, as shown in table 5-38.
148 amd geode? sc3200 processor data book superi/o module revision 5.1 table 5-38. bank selection encoding bsr bits bank selected 76543210 0xxxxxxx 0 10xxxxxx 1 11xxxx1x 1 11xxxxx1 1 11100000 2 11100100 3 table 5-39. bank 1 register map offset type name 00h r/w lbgd(l). legacy baud generator divisor port (low byte) 01h r/w lbgd(h). legacy baud generator divisor port (high byte) 02h --- rsvd. reserved 03h w lcr 1 . line control r/w bsr 1 . bank select 04h-07h --- rsvd. reserved 1. when bit 7 of this register is set to 1, bits [6:0] of bsr select the bank, as shown in table 5-38 on page 148. table 5-40. bank 2 register map offset type name 00h r/w bgd(l). baud generator divisor port (low byte) 01h r/w bgd(h). baud generator divisor port (high byte) 02h r/w excr1. extended control1 03h r/w bsr. bank select 04h r/w excr2. extended control 2 05h --- rsvd. reserved 06h ro rxflv. rx_fifo level 07h ro txflv. tx_fifo level table 5-41. bank 3 register map offset type name 00h ro mrid. module and revision id 01h ro sh_lcr. shadow of lcr 02h ro sh_fcr. shadow of fifo control 03h r/w bsr. bank select 04h-07h --- rsvd. reserved
amd geode? sc3200 processor data book 149 superi/o module revision 5.1 table 5-42. bank 0 bit map register bits offsetname76543210 00h rxd rxd[7:0] (receiver data bits) txd txd[7:0] (transmitter data bits) 01h ier 1 rsvd ms_ie ls_ie txldl_ie rxhdl_ie ier 2 rsvd txemp_ie rsvd 3 / dma_ie 4 ms_ie ls_ie txldl_ie rxhdl_ie 02h eir 1 fen[1:0] rsvd rxft ipr1 ipr0 ipf eir 2 rsvd txemp_ev rsvd 3 / dma_ev 4 ms_ev ls_ev or txhlt_ev txldl_ev rxhdl_ev fcr rxfth[1:0] txfth[1:0] rsvd txsr rxsr fifo_en 03h lcr 5 bkse sbrk stkp eps pen stb wls[1:0] bsr 5 bkse bsr[6:0] (bank select) 04h mcr 1 rsvd loop isen or dcdlp rilp rts dtr mcr 2 rsvd tx_dfr rsvd rts dtr 05h lsr er_inf txemp txrdy brk fe pe oe rxda 06h msr dcd ri dsr cts ddcd teri ddsr dcts 07h spr 1 scratch data ascr 2 rsvd txur 4 rxact 4 rxwdg 4 rsvd s_oet 4 rsvd rxf_tout 1. non-extended mode. 2. extended mode. 3. in sp1 only. 4. in sp2 only. 5. when bit 7 of this register is se t to 1, bits [6:0] of bsr select the bank, as shown in table 5-38 on page 148. table 5-43. bank 1 bit map register bits offsetname76543210 00h lbgd(l) lbgd[7:0] (low byte) 01h lbgd(h) lbgd[15:8] (high byte) 02h rsvd reserved 03h lcr 1 bkse sbrk stkp eps pen stb wls[1:0] bsr 1 bkse bsr[6:0] (bank select) 04h-07h rsvd reserved 1. when bit 7 of this register is se t to 1, bits [6:0] of bsr select the bank, as shown in table 5-38 on page 148.
150 amd geode? sc3200 processor data book superi/o module revision 5.1 table 5-44. bank 2 bit map register bits offsetname7654321 0 00h bgd(l) bgd[7:0] (low byte) 01h bgd(h) bgd [15:8] (high byte) 02h excr1 btest rsvd etdlbk loop rsvd ext_sl 03h bsr bkse bsr[6:0] (bank select) 04h excr2 lock rsvd presl[1:0] rsvd 05h rsvd reserved 06h rxflv rsvd rfl[4:0] 07h txflv rsvd tfl[4:0] table 5-45. bank 3 bit map register bits offsetname7654321 0 00h mrid mid[3:0] rid[3:0] 01h sh_lcr bkse sbrk stkp eps pen stb wls[1:0] 02h sh_fcr rxfth[1:0] txfht[1:0] rsvd txsr rxsr fifo_en 03h bsr bkse bsr[6:0] (bank select) 04h-07h rsvd rsvd
amd geode? sc3200 processor data book 151 superi/o module revision 5.1 5.8.3 ir communications port (ircp) / serial port 3 (sp3) functionality this section describes the ircp/sp3 support registers. the ircp/sp3 functional block provides advanced, versa- tile serial communications features with ir capabilities. the ircp/sp3 also supports two dma channels; the func- tional block can use either one or both of them. one chan- nel is required for ir-based applications, since ir communication works in half duplex fashion. two channels would normally be needed to handle high-speed full duplex ir based applications. the ircp or serial port 3 is chosen via bit 6 of the pmr register (see section 4.2 "multiplexing, interrupt selection, and base address registers" on page 88). 5.8.3.1 ir/sp3 mode re gister bank overview eight register banks, each containing eight registers, con- trol ir/sp3 operation. all registers use the same 8-byte address space to indicate offsets 00h through 07h. the bsr register selects the active bank and is common to all banks. see figure 5-19. 5.8.3.2 ircp/sp3 register and bit maps the tables in this subsection provide register and bit maps for banks 0 through 7. figure 5-19. ircp/sp3 register bank architecture bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 offset 07h offset 06h offset 05h offset 04h lcr/bsr offset 02h offset 01h offset 00h common register throughout all banks table 5-46. bank 0 register map offset type name 00h ro rxd. receive data port w txd. transmit data port 01h r/w ier. interrupt enable 02h ro eir. event identification r/w fcr. fifo control 03h w lcr 1 . link control r/w bsr 1 . bank select 04h r/w mcr. modem/mode control 05h r/w lsr. link status 06h r/w msr. modem status 07h r/w spr. scratchpad r/w ascr. auxiliary status and control 1. when bit 7 of this register is set to 1, bits [6 :0] of bsr select the bank, as shown in table 5-47.
152 amd geode? sc3200 processor data book superi/o module revision 5.1 table 5-47. bank selection encoding bsr bits bank selected functionality 76543210 0xxxxxxx 0 uart + ir 10xxxxxx 1 11xxxx1x 1 11xxxxx1 1 11100000 2 11100100 3 11101000 4 ir only 11101100 5 11110000 6 11110100 7 table 5-48. bank 1 register map offset type name 00h r/w lbgd(l). legacy baud generator divisor port (low byte) 01h r/w lbgd(h). legacy baud generator divisor port (high byte) 02h --- rsvd. reserved 03h w lcr 1 . link control r/w bsr 1 . bank select 04h-07h --- rsvd. reserved 1. when bit 7 of this register is set to 1, bits [6 :0] of bsr select the bank, as shown in table 5-47. table 5-49. bank 2 register map offset type name 00h r/w bgd(l). baud generator divisor port (low byte) 01h r/w bgd(h). baud generator divisor port (high byte) 02h r/w excr1. extended control 1 03h r/w bsr. bank select 04h r/w excr2. extended control 2 05h --- rsvd. reserved 06h ro txflv. tx fifo level 07h ro rxflv. rx fifo level
amd geode? sc3200 processor data book 153 superi/o module revision 5.1 table 5-50. bank 3 register map offset type name 00h ro mid. module and revision identification 01h ro sh_lcr. link control shadow 02h ro sh_fcr. fifo control shadow 03h r/w bsr. bank select 04h-07h --- rsvd. reserved table 5-51. bank 4 register map offset type name 00h ro tmr(l). timer (low byte) 01h ro tmr(h). timer (high byte) 02h r/w ircr1. ir control 1 03h r/w bsr. bank select 04h r/w tfrl(l). transmission frame length (low byte) ro tfrcc(l). transmission current count (low byte) 05h r/w tfrl(h). transmission frame length (high byte) ro tfrcc(h). transmission current count (high byte) 06h r/w rfrml(l). reception frame maximum length (low byte) ro rfrcc(l). reception frame current count (low byte) 07h r/w rfrml(h). reception frame maximum length (high byte) ro rfrcc(h). reception frame current count (high byte) table 5-52. bank 5 register map offset type name 00h r/w spr3. scratchpad 2 01h r/w spr3. scratchpad 3 02h r/w rsvd. reserved 03h r/w bsr. bank select 04h r/w ircr2. ir control 2 05h ro frm_st. frame status 06h ro rfrl(l). received frame length (low byte) ro lstfrc. lost frame count 07h ro rfrl(h). received frame length (high byte)
154 amd geode? sc3200 processor data book superi/o module revision 5.1 table 5-53. bank 6 register map offset type name 00h r/w ircr3. ir control 3 01h r/w mir_pw. mir pulse width 02h r/w sir_pw. sir pulse width 03h r/w bsr. bank select 04h r/w bfpl. beginning flags/preamble length 05h-07h --- rsvd. reserved table 5-54. bank 7 register map offset type name 00h r/w irrxdc. ir receiver demodulator control 01h r/w irtxmc. ir transmitter modulator control 02h r/w rccfg. consumer ir (ceir) configuration 03h r/w bsr. bank select 04h r/w ircfg1. ir interface configuration 1 05h-06h --- rsvd. reserved 07h r/w ircfg4. ir interface configuration 4 table 5-55. bank 0 bit map register bits offsetname76543210 00h rxd rxd[7:0] (receive data) txd txd[7:0] (transmit data) 01h ier 1 rsvd ms_ie ls_ie txldl_ie rxhdl_ie ier 2 tmr_ie sfif_ie txemp_ ie/pld_ie dma_ie ms_ie ls_ie txldl_ie rxhdl_ie 02h eir 1 fen[1:0] rsvd rxft ipr[1:0] ipf eir 2 tmr_ev sfif_ev txemp_ev/ pld_ev dma_ev ms_ev ls_ev/ txhlt_ev txldl_ev rxhdl_ev fcr rxfth[1:0] txfth[1:0] rsvd txsr rxsr fifo_en 03h lcr bkse sbrk stkp eps pen stb wls[1:0] bsr bkse bsr[6:0] (bank select) 04h mcr 1 rsvd loop isen/ dcdlp rilp rts dtr mcr 2 mdsl[2:0] ir_pls tx_dfr dma_en rts dtr 05h lsr er_inf/ fr_end txemp txrdy brk/ max_len fe/ phy_err pe/ bad_crc oe rxda 06h msr dcd ri dsr cts ddcd teri ddsr dcts 07h spr 1 scratch data ascr 2 cte/pld txur rxact/ rxbsy rxwdg/ lost_fr txhfe s_eot fend_inf rxf_tout 1. non-extended mode. 2. extended mode.
amd geode? sc3200 processor data book 155 superi/o module revision 5.1 table 5-56. bank 1 bit map register bits offsetname76543210 00h lbgd(l) lbgd[7:0] (low byte data) 01h lbgd(h) lbgd[15:8] (high byte data) 02h rsvd rsvd 03h lcr bkse sbrk stkp eps pen stb wls[1:0] bsr bkse bsr[6:0] (bank select) 04h-07h rsvd rsvd table 5-57. bank 2 bit map register bits offsetname76543210 00h bgd(l) bgd[7:0] (low byte data) 01h bgd(h) bgd[15:8] (high byte data) 02h excr1 btest rsvd etdlbk loop dmaswp dmath dmanf ext_sl 03h bsr bkse bsr[6:0] (bank select) 04h excr2 lock rsvd presl[1:0] rf_siz[1:0] tf_siz[1:0] 05h rsvd rsvd 06h txflv rsvd tfl[5:0] 07h rxflv rsvd rfl[5:0] table 5-58. bank 3 bit map register bits offsetname76543210 00h mid mid[3:0] rid[3:0] 01h sh_lcr 1 rsvd sbrk stkp eps pen stb wls[1:0] 02h sh_fcr 2 rxfth[1:0] txfth[1:0] rsvd txsr rxsr fifo_en 03h bsr bkse bsr[6:0] (bank select) 04h-07h rsvd reserved 1. lcr register value 2. fcr register value table 5-59. bank 4 bit map register bits offsetname76543210 00h tmr(l) tmr[7:0] (low byte data) 01h tmr(h) rsvd tmr[11:8] (high byte data) 02h ircr1 rsvd ir_sl[1:0] ctest tmr_en 03h bsr bkse bsr[6:0] (bank select) 04h tfrl(l)/ tfrcc(l) tfrl[7:0] / tfrcc[7:0] (low byte data) 05h tfrl(h)/ tfrcc(h) rsvd tfrl[12:8] / tfrcc[12:8] (high byte data)
156 amd geode? sc3200 processor data book superi/o module revision 5.1 06h rfrml(l)/ rfrcc(l) rfrml[7:0] / rfrcc[7:0] (low byte data) 07h rfrml(h)/ rfrcc(h) rsvd rfrml[12:8] / rfrcc[12:8] (high byte data) table 5-59. bank 4 bit map (continued) register bits offsetname76543210 table 5-60. bank 5 bit map register bits offsetname76543210 00h spr2 scratchpad 2 01h spr3 scratchpad 2 02h rsvd rsvd 03h bsr bkse bsr[6:0] (bank select) 04h ircr2 rsvd sftsl fend_md aux_irrx tx_ms mdrs irmssl ir_fdplx 05h frm_st vld lost_fr rsvd max_len phy_err bad_crc ovr1 ovr2 06h rfrl(l)/ lstfrc rfrl[7:0] (low byte data) / lstfrc[7:0] 07h rfrl(h) rfrl[15:8] (high byte data) table 5-61. bank 6 bit map register bits offsetname76543210 00h ircr3 shdm_ds shmd_ds fir_crc mir_crc rsvd txcrc_inv txcrc_ds rsvd 01h mir_pw rsvd mpw[3:0] 02h sir_pw rsvd spw[3:0] 03h bsr bkse bsr[6:0] (bank select) 04h bfpl mbf[3:0] fpl[3:0] 05h-07h rsvd rsvd table 5-62. bank 7 bit map register bits offsetname76543210 00h irrxdc dbw[2:0] dfr[4:0] 01h irtxmc mcpw[2:0] mcfr[4:0] 02h rccfg r_len t_ov rxhsc rcdm_ds rsvd txhsc rc_mmd[1:0] 03h bsr bkse bsr[6:0] (bank select) 04h ircfg1 strv_ms sirc[2:0] irid3 iric[2:0] 05h-06h rsvd rsvd 07h ircfg4 rsvd irrx_md irsl0_ds rxinv irsl21_ds rsvd
amd geode? sc3200 processor data book 157 6 core logic module revision 5.1 6.0 core logic module the core logic module is an enhanced pci-to-sub-isa bridge (south bridge), this module is acpi-compliant, and provides at/sub-isa functionality. the core logic module also contains state-of-the-a rt power management. two bus mastering ide controllers are included for support of up to four ata-compliant devices. a three-port universal serial bus (usb) provides high speed, and plug & play expan- sion for a variety of new consumer peripheral devices. 6.1 feature list internal fast-pci interface the internal fast-pci bus interface is used to connect the core logic and gx1 modules of the sc3200. this inter- face includes the following features: pci protocol for transfers on fast-pci bus up to 66 mhz operation subtractive decode handled internally in conjunction with external pci bus bus mastering ide controllers two controllers with support for up to four ide devices independent timing for master and slave devices for both channels pci bus master burst reads and writes multiword dma support programmed i/o (pio) modes 0-4 support universal serial bus three independent usb interfaces open host controller interface (openhci) specification compliant pci interface pci 2.1 compliant pci master for ac97 and ide controllers subtractive agent for unclaimed transactions supports pci initiator-to-sub-isa cycle translations pci-to-sub-isa interrup t mapper/translator external pci bus ? devices internal to the core logic module (ide, audio, usb, sub-isa, etc.) cannot master to memory through the external pci bus. ? legacy dma is not supported to memory located on external pci bus. ? the core logic module does not transfer subtrac- tively decoded i/o cycles originating from the external pci bus. at compatibility 8259a-equivalent interrupt controllers 8254-equivalent timer 8237-equivalent dma controllers port a, b, and nmi logic positive decode for at i/o space sub-isa interface boot rom chip select extended rom to 16 mb two general-purpose chip selects nand flash support m-systems diskonchip support is not the subtractive decode agent power management automated cpu 0v suspend modulation i/o traps and idle timers for peripheral power manage- ment software smi and stop clock for apm support acpi-compliant time r and register set up to 22 gpios of which all can generate power management interrupts (pmes) three dedicated gpwios powered by v sbl and v sb shadow register support for legacy controllers for 0v suspend
158 amd geode? sc3200 processor data book core logic module revision 5.1 integrated audio ac97 version 2.0 compliant interface to audio codecs secondary codec support amc97 codec support video processor interface synchronous serial interface to the video processor translates video and clock control register accesses from pci to serial interface supports both reads and writes of video processor registers retries fast-pci bus accesses until core logic completes the transfer over the serial interface low pin count (lpc) interface based on intel lpc interface specification revision 1.0 serial irq support 6.2 module architecture the core logic architecture provides the internal functional blocks shown in figure 6-1. fast-pci interface to external pci bus ide controllers (udma-33) usb controllers sub-isa bus interface at compatibility logic (legacy) acpi compliant power management (includes gpio interfaces, such as joystick) integrated audio controller low pin count (lpc) interface figure 6-1. core logic module block diagram ide config. pw lpc legacy acpi/pm audio udma33 usb lpc sub-isa fast x-bus controller fast-pci pci interface x-bus ac97 pci isa/pic/pit/dma usb 33-66 mhz 33 mhz reg. gpios gpios
amd geode? sc3200 processor data book 159 core logic module revision 5.1 6.2.1 fast-pci interface to external pci bus the core logic module provides a pci bus interface that is both a slave for pci cycles init iated by the gx1 module or other pci master devices, and a non-preemptive master for dma transfer cycles. it is also a standard pci master for the ide controllers and audio i/o logic. the core logic supports positive decode for configurable memory and i/o regions, and implements a s ubtractive decode option for unclaimed pci accesses. it also generates address and data parity, and performs parity checking. the arbiter for the fast-pci interface is located in the gx1 module. configuration registers are accessed through the pci inter- face using the pci bus type 1 configuration mechanism as described in the pci specification. 6.2.1.1 processor mastered cycles the core logic module acts on all processor initiated cycles according to pci rules for active/subtractive decode using devsel#. memory writes are automatically posted. reads are retried if they are not destined for actively decoded (i.e., positive decode) devices on the high speed x-bus or the 33 mhz x-bus. this means that reads to external pci, lpc, or sub-isa devices are automatically treated as delayed transactions through the pci retry mechanism. this allows the high bandwidth devices access to the fast-pci interf ace while the response from a slow device is accumulated. bursting from the host is not supported. all types of confi guration cycles are su pported and handled appropriately according to the pci specification. 6.2.1.2 external pc i mastered cycles memory cycles mastered by external pci devices on the external pci bus are actively taken if they are to the system memory address range. memory cycles to system memory are forwarded to the fast-pci interface. burst transfers are stopped on every cache line boundary to allow efficient buffering in the fast-pci interface block. i/o and configuration cycles mastered by external pci devices which are subtractively decoded by the core logic module, are not handled. 6.2.1.3 core logic internal or sub-isa mastered cycles only memory cycles (not i/o cycles) are supported by the internal sub-isa or legacy dma masters. these memory cycles are always forwarded to the fast-pci interface. 6.2.1.4 external pci bus the external pci bus is a fully-compliant pci bus. pci slots are connected to this bus. support for up to two bus mas- ters is provided. the arbiter is in the core logic module. 6.2.1.5 bus master request priority the fast-pci bus supports seven bus masters. the requests (reqs) are fixed in priority. the seven bus mas- ters in order of priority are: 1) vip 2) ide channel 0 3) ide channel 1 4) audio 5) usb 6) external req0# 7) external req1# 6.2.2 pserial interface the majority of the system power management logic is implemented in the core logic module, but a minimal amount of logic is contained within the gx1 module to pro- vide information that is not externally visible (e.g., graphics controller). the gx1 module implements a simple serial communica- tions mechanism to transmit the cpu status to the core logic module via internal signal pserial. the gx1 mod- ule accumulates cpu events in an 8-bit register which it transmits serially every 1 to 10 s. the packet transmitter holds the serial output internal sig- nal (pserial) low until the transmission interval counter has elapsed. once the coun ter has elapsed, the pserial signal is held high for two clocks to indicate the start of packet transmission. the cont ents of the serial packet reg- ister are then shifted out starting from bit 7 down to bit 0. the pserial signal is held high for one clock to indicate the end of packet transmission and then remains low until the next transmission interval. after the packet transmis- sion is complete, the gx1 module?s serial packet register?s contents are cleared. the gx1 module?s input clock is used as the clock refer- ence for the serial packet transmitter. once a bit in the register is se t, it remains set until the com- pletion of the next packet transmission. successive events of the same type that occur between packet transmissions are ignored. multiple unique events between packet trans- missions accumulate in this register. the gx1 module transmits the contents of the serial packet only when a bit in the serial packet register is set and the interval counter has elapsed. the core logic module decodes the serial packet after each transmission and performs the power management tasks related to video retrace. for more information on the serial packet register refer to the amd geode? gx1 processor data book .
160 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.2.1 video re trace interrupt bit 7 of the ?serial packet? can be used to generate an smi whenever a video retrace occurs within the gx1 module. this function is normally not used for power management but for softvga routines. setting f0 index 83h[2] = 1 enables this function. a read on ly status register located at f1bar0+i/o offset 00h[5] ca n be read to see if the smi was caused by a video retrace event. 6.2.3 ide controller the core logic module integrates a pci bus mastering, ata-4 compatible ide controller. this controller supports ultradma, multiword dma a nd programmed i/o (pio) modes. two devices are supported on the ide controller. the data-transfer speed for each device can be indepen- dently programmed. this allows high-speed ide peripher- als to coexist on the same channel as lower speed devices. the core logic module supports two ide channels, a pri- mary channel and a secondary channel. the ide interface provides a va riety of features to optimize system performance, including 32-bit disk access, post write buffers, bus master, multiword dma, look-ahead read buffer, and prefetch mechanism for each channel respec- tively. the ide interface timing is completely programmable. tim- ing control covers the command active and recover pulse widths, and command block register accesses. the ide data-transfer speed for each device on each channel can be independently programmed allowing high-speed ide peripherals to coexist on the same channel as older, com- patible devices. the core logic module also provides a software accessi- ble buffered reset signal to the ide drive, f0 index 44h[2]. the ide_rst# signal can be driven low or high as needed for device-power-off conditions. ide_rst# is not driven low by por# (power-on reset). 6.2.3.1 ide configuration registers registers for configuring channels 0 and 1 are located in the pci register space designated as function 2 (f2 index 40h-5ch). table 6-35 on page 273 provides the bit formats for these registers. the ide bus master configuration regis- ters are accessed via f2 index 20h which is base address register 4 in function 2 (f2bar4). see table 6-36 on page 277 for register/bit formats. the following subsections discuss core logic operational/ programming details concerning pio, bus master, and ultradma/33 modes. 6.2.3.2 pio mode the ide data port transaction latency consists of address latency, asserted latency and recovery latency. address latency occurs when a pci master cycle targeting the ide data port is decoded, and the ide_addr[2:0] and ide_cs# lines are not set up. address latency provides the setup time for the ide_addr[2:0] and ide_cs# lines prior to i de_ior# and ide_iow#. asserted latency consists of the i/o command strobe assertion length and recovery time. recovery time is pro- vided so that transactions may occur back-to-back on the ide interface without violating minimum cycle periods for the ide interface. if ide_iordy is asserted when the initial sample point is reached, no wait states ar e added to the command strobe assertion length. if ide_iordy is negated when the initial sample point is reached, additional wait states are added. recovery latency occurs after the ide data port transac- tions have completed. it provides hold time on the ide_addr[2:0] and ide_cs# lines with respect to the read and write strobes (ide_ior# and ide_iow#). the pio portion of the ide registers is enabled through: channel 0 drive 0 programmed i/o register (f2 index 40h) channel 0 drive 1 programmed i/o register (f2 index 48h) channel 1 drive 0 programmed i/o register (f2 index 50h) channel 1 drive 1 programmed i/o register (f2 index 58h) the ide channels and devices can be individually pro- grammed to select the proper address setup time, asserted time, and recovery time. the bit formats for these registers are shown in table 6-35 on page 273. note that there are different bit formats for each of the pio programming registers depending on the operating format selected: format 0 or format 1: f2 index 44h[31] (channel 0 drive 0 ? dma control register) sets the format of the pio register. ? if bit 31 = 0, format 0 is used and it selects the slowest pio mode (bits [19:16]) per channel for commands. ? if bit 31 = 1, format 1 is used and it allows indepen- dent control of command and data. also listed in the bit formats are recommended values for the different pio modes. note that these are only recom- mended settings and are not 100% tested. when using independent control of command and data cycles the following algorithm should be used when two ide devices are sharin g the same channel: 1) the pio data cycle timing for a particular device can be the timing value for the maximum pio mode which that device reports it supports. 2) the pio command cycle timi ng for a particular device must be the timing value for the lowest pio mode for both devices on the channel.
amd geode? sc3200 processor data book 161 core logic module revision 5.1 for example, if a channel had one mode 4 device and one mode 0 device, then the mode 4 device would have com- mand timings for mode 0 and data timing for mode 4. the mode 0 device would have both command and data timings for mode 0. note that for the mode 0 case, the 32-bit timing value is listed because both data and command timings are the same mode. however, the actual timing value for the mode 4 device would be constructed out of the mode 4 data timing 16-bit value and the mode 0 16-bit command timing value. both 16-bit values are shown in the register description but not assembled together as they are mixed modes. 6.2.3.3 bus master mode two ide bus masters are provided to perform the data transfers for the primary and secondary channels. the ide controller of the core logic module off-loads the cpu and improves system performance in multitasking environ- ments. the bus master mode programming interface is an exten- sion of the standard ide programming model. this means that devices can always be dealt with using the standard ide programming model, with th e master mode functional- ity used when the appropriate driver and devices are present. master operation is designed to work with any ide device that supports dma transfers on the ide bus. devices that work in pio mode can only use the standard ide programming model. the ide bus masters use a simple scatter/gather mecha- nism allowing large transfer blocks to be scattered to or gathered from memory. this cuts down on the number of interrupts to and interactions with the cpu. physical region descriptor table address before the controller starts a master transfer it is given a pointer to a physical region descriptor table. this pointer sets the starting memory location of the physical region descriptors (prds). the prds describe the areas of mem- ory that are used in the data transfer. the prds must be aligned on a 4-byte boundary and the table cannot cross a 64 kb boundary in memory. primary and secondary id e bus master registers the ide bus master registers for each channel (primary and secondary) have an ide bus master command regis- ter and bus master status regi ster. these registers and bit formats are described in table 6-36 on page 277. physical region descriptor format each physical memory region to be transferred is described by a physical region descriptor (prd) as illus- trated in table 6-1. when the bus master is enabled (com- mand register bit 0 = 1), dat a transfer proceeds until each prd in the prd table has been transferred. the bus mas- ter does not cache prds. the prd table consists of two dwords. the first dword contains a 32-bit pointer to a buffer to be transferred. the second dword contains the si ze (16 bits) of the buffer and the eot flag. the eot bit (bit 31) must be set to indi- cate the last prd in the prd table. programming model the following steps explain how to initiate and maintain a bus master transfer between memory and an ide device. 1) software creates a prd table in system memory. each prd entry is 8 bytes long, consisting of a base address pointer and buffer size. the maximum data that can be transferred from a prd entry is 64 kb. a prd table must be aligned on a 4-byte boundary. the last prd in a prd table must have the eot bit set. 2) software loads the starting address of the prd table by programming the prd table address register. 3) software must fill the buffers pointed to by the prds with ide data. 4) write 1 to the bus master interrupt bit and bus master error (status register bits 2 and 1) to clear the bits. 5) set the correct direction to the read or write control bit (command register bit 3). engage the bus master by writing a ?1? to the bus master control bit (command register bit 0). the bus master reads the prd entry pointed to by the prd table address register and increments the address by 08h to point to the next prd. the transfer begins. 6) the bus master transfers data to/from memory responding to bus master requests from the ide device. at the completion of each prd, the bus mas- ter?s next response depends on the settings of the eot flag in the prd. if the eot bit is set, then the ide bus master clears the bus master active bit (status register bit 0) and stop. if any errors occurred during the transfer, the bus master sets the bus master error bit status register bit 1). table 6-1. physical region descriptor format dword byte 3 byte 2 byte 1 byte 0 31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 memory region physical base address [31:1] (ide data buffer) 0 1e o t reserved size [15:1] 0
162 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.3.4 ultradma/33 mode the ide controller of the core logic module supports ultradma/33. it utilizes the standard ide bus master func- tionality to interface, initiate and control the transfer. ultradma/33 definition also incorporates a cyclic redun- dancy checking (crc) error checking protocol to detect errors. the ultradma/33 protocol requires no extra signal pins on the ide connector. the ide controller redefines three stan- dard ide control signals when in ultradma/33 mode. these definitions are shown in table 6-2. all other signals on the ide connector retain their func- tional definitions during the ultradma/33 operation. ide_iow# is defined as stop for both read and write transfers to request to stop a transaction. ide_ior# is redefined as dmardy# for transferring data from the ide device to the ide controller. it is used by the ide controller to signal when it is ready to transfer data and to add wait states to the current transaction. ide_ior# sig- nal is defined as strobe for transferring data from the ide controller to the ide device. it is the data strobe signal driven by the ide controller on which data is transferred during each rising and falling edge transition. ide_iordy is redefined as strobe for transferring data from the ide device to the ide controller during a read cycle. it is the data strobe signal driven by the ide device on which data is transferred during each rising and falling edge transition. ide_iordy is defined as dmardy# dur- ing a write cycle for transferring data from the ide control- ler to the ide device. it is used by the ide device to signal when it is ready to transfer data and to add wait states to the current transaction. ultradma/33 data transfer consis ts of three phases, a star- tup phase, a data transfer phase and a burst termination phase. the ide device begins the startup phase by asserting ide_dreq. when ready to begin the transfer, the ide con- troller asserts ide_dack#. when ide_dack# is asserted, the ide controller drives ide_cs0# and ide_cs1# asserted, and ide_addr[2:0] low. for write cycles, the ide controller negates stop, waits for the ide device to assert dmardy#, and then drives the first data word and strobe signal. for read cycles, the ide controller negates stop, and asserts dmardy#. the ide device then sends the first data word and asserts strobe. the data transfer phase continues the burst transfers with the core logic and the ide via providing data, toggling strobe and dmardy#. the id e_data[15:0] is latched by receiver on each rising and falling edge of strobe. the transmitter can pause the burst cycle by holding strobe high or low, and resume the burst cycle by again toggling strobe. the receiver can pause the burst cycle by negating dmardy# and resumes the burst cycle by asserting dmardy#. the current burst cycle can be terminated by either the transmitter or the receiver. a burst cycle must first be paused as described above before it can be terminated. the ide controller can then stop the burst cycle by assert- ing stop, with the ide device acknowledging by negating ide_dreq. the ide device then stops the burst cycle by negating ide_dreq and the ide controller acknowledges by asserting stop. the transmitter then drives the strobe signal to a high level. the ide controller then puts the result of the crc calculation onto the ide_data[15:0] while de-asserting ide_dack#. the ide device latches the crc value on the rising edge of ide_dack#. the crc value is used for error checking on ultradma/33 transfers. the crc value is calculated for all data by both the ide controller and the ide device during the ultradma/ 33 burst transfer cycles. this re sult of the crc calculation is defined as all data transferred with a valid strobe edge while ide_dack# is asserted. at the end of the burst transfer, the ide controller drives the result of the crc cal- culation onto ide_data[15:0] which is then strobed by the de-assertion of ide_dack#. the ide device compares the crc result of the ide controller to its own and reports an error if there is a mismatch. the timings for ultradma/33 are programmed into the dma control registers: channel 0 drive 0 dma control register (f2 index 44h) channel 0 drive 1 dma control register (f2 index 4ch) channel 1 drive 0 dma control register (f2 index 54h) channel 1 drive 1 dma control register (f2 index 5ch) the bit formats for these registers are described in table 6- 35 on page 273. note that f2 index 44h[20] is used to select either multiword or ultradma mode. bit 20 = 0 selects multiword dma mode. if bit 20 = 1, then ultradma/ 33 mode is selected. once mode selection is made using this bit, the remaining dma control registers also operate in the selected mode. also listed in the bit formats are recommended values for both multiword dma modes 0-2 and ultradma/33 modes 0-2. note that these are only recommended settings and are not 100% tested. table 6-2. ultradma/33 signal definitions ide controller channel signal ultradma/33 read cycle ultradma/33 write cycle ide_iow# stop stop ide_ior# dmardy# strobe ide_iordy strobe dmardy#
amd geode? sc3200 processor data book 163 core logic module revision 5.1 6.2.4 universal serial bus the core logic module provides three complete, indepen- dent usb ports. each port has a data "negative" and a data "positive" signal. the usb ports are open host controller interface (open- hci) compliant. the openhci specification provides a reg- ister-level description for a host controller, as well as common industry hardware/software interface and drivers. 6.2.5 sub-isa bus interface the sub-isa interface of the core logic module is an isa- like bus interface that is used by sc3200 to interface with boot flash, m-systems diskonchip or nand eeprom and other i/o devices. the core logic module is the default subtractive decoding agent and forwards all unclaimed memory and i/o cycles to the isa bus. however, the core logic module can be configured to ignore either i/ o, memory, or all unclaime d cycles (subtractive decode disabled). note: the external sub-isa bus is a positive decode bus. unclaimed memory and i/o cycles will not appear on the sub-isa interface. the core logic module does not support sub-isa refresh cycles. the refresh toggle bit in port b still exists for soft- ware compatibility reasons. the sub-isa interface includes the followings signals in addition to the signals used for an isa interface: iocs0#/iocs1# ? asserted on i/o read/write transactions from/to a programmable address range. doccs# ? asserted on memory read/write transactions from/to a programmable window. romcs# ? asserted on memory read/write to upper 16 mb of address space. configurable via the rom mask register (f0 index 6ch). docr# ? docr# is asserted on memory read transactions from doccs# window (i.e., when both doccs# and memr# are active, docr# is active; otherwise, it is inactive). docw ? docw# is asserted on memory write transactions to doccs# window (i.e., when both doccs# and memw# are active, docw# is active; otherwise, it is inactive). rd#, wr# ? the signals ior#, iow#, memr#, and memw# are combined into two signals: rd# is asserted on i/o read or memory read; wr# is asserted on i/o write or memory write. memory devices that use romcs# or doccs# as their chip select signal can be configured to support an 8-bit or 16-bit data bus via bits 3 an d 6 of the mcr register. such devices can also be configured as zero wait states devices (regardless of the data bus width) via bits 9 and 10 of the mcr register. for mcr register bit descriptions, see table 4-2 on page 88. i/o peripherals that use iocs0# or iocs1# as their chip select signal can be configured to support an 8-bit or 16-bit data bus via bits 7 and 8 of the mcr register. such devices can also be configured as zero wait state devices (for 8-bit peripherals) via bits 11 and 12 of the mcr register. for mcr register bit descriptions, see table 4-2 on page 88. other memory devices and i/o peripherals must be 8-bit devices; their transactions can not be with zero wait states the boot flash supported by the sc3200 can be up to 16 mb. it is supported with the romcs# signal. all unclaimed memory and i/o cycles are forwarded to the internal isa bus if subtractive decode is enabled. the diskonchip chip select signal (doccs#) is asserted on any memory read or memory write transaction from/to a programmable address range. the address range is pro- grammable via the doccs# base address and control registers (f0 index 78h and 7ch). the base address must be on an address boundary, the size of the range. signal doccs# can also be used to interface to nand flash devices together with signals docw# and docr#. see application note amd geode? sc1200/sc2200/ sc3200 processors: external nand flash memory circuit for details.
164 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.5.1 sub-isa bus cycles the isa bus controller issues multiple isa cycles to satisfy pci transactions that are larger than 16 bits. a full 32-bit read or write results in two 16-bit isa transactions or four 8- bit isa transactions. the isa controller gathers the data from multiple isa read cycles and returns trdy# to the pci bus. sa[23:0] are a concatenation of isa la[23:17] and sa[19:0] and perform equivalent functionality at a reduced pin count. figure 6-2 shows the relation ship between a pci cycle and the corresponding isa cycle generated. note: not all signals described in figure 6-2 are avail- able externally. see section 3.4.7 "sub-isa inter- face signals" on page 73 for more information about which sub-isa signals are externally avail- able on the sc3200. 6.2.5.2 sub-isa support of delayed pci transactions multiple pci cycles occur for every slower isa cycle. this prevents slow pci cycles fr om occupying too much band- width and allows access to other pci traffic. figure 6-3 on page 165 shows the relationshi p of pci cycles to an isa cycle with pci delayed transactions enabled. figure 6-2. non-posted fast-pci to isa access fast-pci_clk isaclk frame# irdy# trdy# ad[31:0] (read) rd#,wr#,ior#,iow# ad[31:0] (write) bale stop# memr#,memw#
amd geode? sc3200 processor data book 165 core logic module revision 5.1 figure 6-3. pci to isa cycles with delayed transaction enabled 6.2.5.3 sub-isa bu s data steering the core logic module performs all of the required data steering from sd[7:0] to sd[15:0] during normal 8-bit isa cycles, as well as during dma and isa master cycles. it handles data transfers between the 32-bit pci data bus and the isa bus. 8/16-bit devices can reside on the isa bus. various pc-compatible i/o registers, dma controller registers, interrupt controller registers, and counter/timer registers lie on the on-chip i/ o data bus. either the pci bus master or the dma controllers can become the bus owner. when the pci bus master is the bus owner, the core logic module data steering logic provides data conversion nec- essary for 8/16/32-bit transfers to and from 8/16-bit devices on either the sub-isa bus or the 8-bit registers on the on- chip i/o data bus. when pci data bus drivers of the core logic module are in tri-state, data transfers between the pci bus master and pci bus devices are handled directly via the pci data bus. when the dma requestor is the bus owner, the core logic module allows 8/16-bit data transfer between the sub-isa bus and the pci data bus. 6.2.5.4 i/o recovery delays in normal operation, the core logic module inserts a delay between back-to-back isa i/o cycl es that originate on the pci bus. the default delay is four isaclk cycles. thus, the second of consecutive i/o cycl es is held in the isa bus controller until this delay count has expired. the delay is measured between the rising edge of ior#/iow# and the falling edge of bale. this delay can be adjusted to a greater delay through the isa i/o recovery control register (f0 index 51h). note: this delay is not inserted for a 16-bit sub-isa i/o access that is split into two 8-bit i/o accesses. req# gnt# frame# irdy# trdy# stop# rd#, ior# bale fast-pci 1 1 1 1 1 - gx1 transaction 2 3 2 - ide bus master - starts and completes 3 - end of isa cycle isa
166 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.5.5 isa dma dma transfers occur between isa i/o peripherals and sys- tem memory (i.e., not availabl e externally). the data width can be either 8 or 16 bits. out of the seven dma channels available, four are used for 8-bit transfers while the remain- ing three are used for 16-bit transfers. one byte or word is transferred in each dma cycle. note: the core logic module does not support dma transfers to isa memory. the isa dma device initiates a dma request by asserting one of the drq[7:5, 3:0] signals. when the core logic module receives this request, it sends a bus grant request to the pci arbiter. after the pci bus has been granted, the respective dack# is driven active. the core logic module generates pci memory read or write cycles in response to a dma cycle. figure 6-4 and figure 6-5 are examples of dma memory read and mem- ory write cycles. upon detection of the dma controller?s memr# or memw# active, the core logic module starts the pci cycle, asserts frame#, and negates an internal iochrdy. this assures the dm a cycle does not complete before the pci cycle has provid ed or accepted the data. iochrdy is internally asserted when irdy# and trdy# are sampled active. figure 6-4. isa dma read from pci memory figure 6-5. isa dma write to pci memory pciclk isaclk memr# iow# frame# ad[31:0] irdy# trdy# sd[15:0] iochrdy pciclk isaclk memw# ior# frame# ad[31:0] irdy# trdy# sd[15:0] iochrdy
amd geode? sc3200 processor data book 167 core logic module revision 5.1 6.2.5.6 rom interface the core logic module positively decodes memory addresses 000f0000h-000fffffh (64 kb) and fffc0000h-ffffffffh (256 kb) at reset. these memory cycles cause the core logic module to claim the cycle, and generate an isa bus memory cycle with romcs# asserted. the core logic module can also be configured to respond to memory addresses ff000000h-ffffffffh (16 mb) and 000e0000h-000 fffffh (128 kb). 8- or 16-bit wide rom is supp orted. boot16 strap deter- mines the width after reset. mcr[14,3] (offset 34h) in the general configuration block (see table 4-2 on page 88 for bit details) allows program control of the width. flash rom is supported in the core logic module by enabling the romcs# signal on write accesses to the rom region. normally only read cycles are passed to the isa bus, and the romcs# signal is suppressed for write cycles. when the rom write enable bit (f0 index 52h[1]) is set, a write access to the rom address region causes a write cycle to occur with memw#, wr# and romcs# asserted. 6.2.5.7 pci and sub-isa si gnal cycle multiplexing the sc3200 multiplexes most pci and sub-isa signals on the balls listed in table 6-3, in order to reduce the number of balls on the device. cycle multiplexing is on a bus-cycle by bus-cycle basis (see figure 6-6 on page 168), where the internal core logic pci bridge arbitrates between pci cycles and sub-isa cycles. other pci and sub-isa signals remain non-shared, however, some sub-isa signals may be muxed with gpio. sub-isa cycles are only generated as a result of gx1 mod- ule accesses to the following addresses or conditions: romcs# address range. doccs# address range. iocs0# address range. iocs1# address range. an i/o write to address 80h or to 84h. internal isa is programmed to be the subtractive decode agent and no other ag ents claim the cycle. if the sub-isa and pci bus have more than four compo- nents, the sub-isa components can be buffered using 74hct245 or 74fct245 type transceivers. the rd# (an and of ior#, memr#) signal can be used as dir control while trde# is used as enable control. table 6-3. cycle multiplexed pci / sub-isa balls pci sub-isa ball no. ebga tepbga ad0 a0 a17 u1 ad1 a1 d16 p3 ad2 a2 a18 u3 ad3 a3 a15 n1 ad4 a4 a16 p1 ad5 a5 a14 n3 ad6 a6 c15 n2 ad7 a7 b14 m2 ad8 a8 c14 m4 ad9 a9 b13 l2 ad10 a10 c13 l3 ad11 a11 c12 k1 ad12 a12 a12 l4 ad13 a13 c11 j1 ad14 a14 a11 k4 ad15 a15 b10 j3 ad16 a16 a7 e1 ad17 a17 c7 f4 ad18 a18 d7 e3 ad19 a19 a6 e2 ad20 a20 d6 d3 ad21 a21 c6 d1 ad22 a22 a5 d2 ad23 a23 f4 b6 ad24 d0 c5 c2 ad25 d1 d5 c4 ad26 d2 a4 c1 ad27 d3 b4 d4 ad28 d4 c4 b4 ad29 d5 a3 b3 ad30 d6 c2 a3 ad31 d7 b3 d5 c/be0# d8 a13 l1 c/be1# d9 a10 j2 c/be2# d10 d8 f3 c/be3# d11 a8 h4 pa r d 1 2 c 1 0 j 4 trdy# d13 b8 f1 irdy# d14 c8 f2 stop# d15 d9 g1 devsel# bhe# b5 e4
168 amd geode? sc3200 processor data book core logic module revision 5.1 figure 6-6. pci change to sub-isa and back 6.2.6 at compatibility logic the core logic module integrates: two 8237-equivalent dma controllers with full 32-bit addressing two 8259a-equivalent interrupt controllers providing 13 individually programmable external interrupts an 8254-equivalent timer for refresh, timer, and speaker logic nmi control and gener ation for pci system errors and all parity errors support for standard at keyboard controllers positive decode for the at i/o register space reset control 6.2.6.1 dma controller the core logic module supports industry standard dma architecture using two 8237-compatible dma controllers in cascaded configuration. the dma functions supported by the core logic module include: standard seven-channel dma support (channels 5 through 7 are not supported) 32-bit address range support via high page registers iochrdy extended cycles for compatible timing trans- fers internal sub-isa bus master device support using cascade mode nmi control and generation for pci system errors and all parity errors. note: dma interface signals are not available externally. dma channels the core logic module supports seven dma channels using two standard 8237-equivalent controllers. dma con- troller 1 contains channels 0 through 3 and supports 8-bit i/o adapters. these channels are used to transfer data between 8-bit peripherals and pci memory or 8/16-bit isa memory. using the high and low page address registers, a full 32-bit pci address is output for each channel so they can all transfer data throughout the entire 4 gb system address space. each channel can transfer data in 64 kb pages. software initiated dma requests are not supported. dma controller 2 contains channels 4 through 7. channel 4 is used to cascade dma controller 1, so it is not available externally. channels 5 through 7 support 16-bit i/o adapt- ers to transfer data between 16-bit i/o adapters and 16-bit system memory. using the high and low page address reg- isters, a full 32-bit pci address is output for each channel so they can all transfer data throughout the entire 4 gb system address space. each channel can transfer data in 128 kb pages. channels 5, 6, and 7 transfer 16-bit words on even byte boundaries only. channels 5 through 7 are not supported. frame# trdy#, irdy# gnt[x] romcs#, doccs#, pci sub-isa t cs t cp devsel#,stop# pa r , pci ad[31:0], c/be[3:0]# pull-up iocs0#, iocs1#
amd geode? sc3200 processor data book 169 core logic module revision 5.1 dma transfer modes each dma channel can be programmed for single , block , demand or cascade transfer modes. in the most commonly used mode, single transfer mode, one dma cycle occurs per drq and the pci bus is released after every cycle. this allows the core logic module to timeshare the pci bus with the gx1 module. this is imperative, especially in cases involving large data transfers, because the gx1 module gets locked out for too long. in block transfer mode, the dma controller executes all of its transfers consecutively without releasing the pci bus. in demand transfer mode, dma transfer cycles continue to occur as long as drq is high or terminal count is not reached. in this mode, the dma controller continues to exe- cute transfer cycles until the i/ o device drops drq to indi- cate its inability to continue providing data. for this case, the pci bus is held by the core logic module until a break in the transfers occurs. in cascade mode, the channel is connected to another dma controller or to an isa bus master, rather than to an i/ o device. in the core logic module, one of the 8237 con- trollers is designated as the master and the other as the slave. the hold output of the slave is tied to the drq0 input of the master (channel 4), and the master?s dack0# output is tied to the slave?s hlda input. in each of these modes, the dma controller can be pro- grammed for read , write, or verify transfers. both dma controllers are rese t at power-on reset (por) to fixed priority. since master channel 0 is actually connected to the slave dma controller, the slave?s four dma channels have the highest priority, with channel 0 as highest and channel 3 as the lowest. immediately following slave channel 3, master channel 1 (c hannel 5) is the next high- est, followed by channels 6 and 7. dma controller registers the dma controller can be programmed with standard i/o cycles to the standard regist er space for dma. the i/o addresses for the dma controller registers are listed table 6-43 on page 313. when writing to a channel's address or word count reg- ister, the data is written into both the base register and the current register simultaneously. when reading a channel address or word count register, only the current address or word count can be read. the base address and base word count are not accessible for reading. dma transfer types each of the seven dma channels may be programmed to perform one of three types of transfers: read, write, or ver- ify . the transfer type selected defines the method used to transfer a byte or word during one dma bus cycle. for read transfer types, the core logic module reads data from memory and write it to the i/o device associated with the dma channel. for write transfer types, the core logic module reads data from the i/o device associated with the dma channel and write to the memory. the verify transfer type causes the core logic module to execute dma transfer bus cycl es, including generation of memory addresses, but neither the read nor write com- mand lines are activated. this transfer type was used by dma channel 0 to implement dram refresh in the original ibm pc and xt. dma priority the dma controller may be programmed for two types of priority schemes: fixed and rotate (i/o ports 008h[4] and 0d0h[4] - see table 6-43 on page 313). in fixed priority, the channels are fixed in priority order based on the descending values of their numbers. thus, channel 0 has the highest priority. in rotate priority, the last channel to get service becomes the lowest-priority channel with the priority of the others rotating accordingly. this pre- vents a channel from dominating the system. the address and word count registers for each channel are 16-bit registers. the value on the data bus is written into the upper byte or lower byte, depending on the state of the internal addressing byte pointer. this pointer can be cleared by the clear byte pointer command. after this com- mand, the first read/write to an address or word-count register reads or writes to t he low byte of the 16-bit register and the byte pointer points to the high byte. the next read/ write to an address or word-count register reads or writes to the high byte of the 16-bit register and the byte pointer points back to the low byte. when programming the 16-bit channels (channels 5, 6, and 7), the address which is written to the base address register must be the real address divided by two. also, the base word count for the 16-bit channels is the number of 16-bit words to be transferred, not the number of bytes as is the case for the 8-bit channels. the dma controller allows t he user to program the active level (low or high) of the drq and dack# signals. since the two controllers are cascaded together internally on the chip, these signals should always be programmed with the drq signal active high and the dack# signal active low. dma shadow registers the core logic module contains a shadow register located at f0 index b8h (table 6-29 on page 206) for reading the configuration of the dma contro llers. this read only regis- ter can sequence to read thro ugh all of the dma registers.
170 amd geode? sc3200 processor data book core logic module revision 5.1 dma addressing capability dma transfers occur over the entire 32-bit address range of the pci bus. this is accomplished by using the dma con- troller?s 16-bit memory address registers in conjunction with an 8-bit dma low page register and an 8-bit dma high page register. these registers, associated with each channel, provide the 32-bit memory address capability. a write to the low page register clears the high page regis- ter, for backward compatib ility with the pc/at standard. the starting address for the dma transfer must be pro- grammed into the dma controller registers and the chan- nel?s respective low and high page registers prior to beginning the dma transfer. dma page registers and extended addressing the dma page registers provide the upper address bits during dma cycles. dma addre sses do not increment or decrement across page boundaries. page boundaries for the 8-bit channels (channels 0 through 3) are every 64 kb and page boundaries for the 16-bit channels (channels 5, 6, and 7) are every 128 kb. before any dma operations are performed, the page regis- ters must be written at the i/o port addresses in the dma controller registers to select the correct page for each dma channel. the other address locations between 080h and 08fh and 480h and 48fh are not used by the dma chan- nels, but can be read or written by a pci bus master. these registers are reset to zero at por. a write to the low page register clears the high pa ge register, for backward com- patibility with the pc/at standard. for most dma transfers, the high page register is set to zeros and is driven onto pci address bits ad[31:24] during dma cycles. this mode is ba ckward compatible with the pc/at standard. for dma extended transfers, the high page register is programmed and the values are driven onto the pci addresses ad[ 31:24] during dma cycles to allow access to the full 4 gb pci address space. dma address generation the dma addresses are formed such that there is an upper address, a middle address, and a lower address por- tion. the upper address portion, which selects a specific page, is generated by the page registers. the page registers for each channel must be set up by the system before a dma operation. the dma page register values are driven on pci address bits ad[31:16] for 8-bit channels and ad[31:17] for 16-bit channels. the middle address portion, which selects a block within the page, is generated by t he dma controller at the begin- ning of a dma operation and any time the dma address increments or decrements through a block boundary. block sizes are 256 bytes for 8-bit channels (channels 0 through 3) and 512 bytes for 16-bit channels (channels 5, 6, and 7). the middle address bits are is driven on pci address bits ad[15:8] for 8-bit channels and ad[16:9] for 16-bit channels. the lower address portion is generated directly by the dma controller during dma operations. the lower address bits are output on pci address bits ad[7:0] for 8-bit channels and ad[8:1] for 16-bit channels. bhe# is configured as an output during all dma opera- tions. it is driven as the inversion of ad0 during 8-bit dma cycles and forced low for all 16-bit dma cycles. 6.2.6.2 programmable interval timer the core logic module contains an 8254-equivalent pro- grammable interval timer (pit) configured as shown in figure 6-7. the pit has thr ee timers/counters, each with an input frequency of 1.19318 mhz (osc divided by 12), and individually programmable to different modes. the gates of counter 0 and 1 are usually enabled, how- ever, they can be controlled via f0 index 50h. the gate of counter 2 is connected to i/o port 061h[0]. the output of counter 0 is connected internally to irq0. this timer is typ- ically configured in mode 3 (square wave output), and used to generate irq0 at a periodic rate to be used as a system timer function. the output of counter 1 is connected to i/o port 061h[4]. the reset state of i/o port 061h[4] is 0 and every falling edge of counter 1 output causes i/o port 061h[4] to flip states. the output of counter 2 is brought out to the pc_beep output. th is output is gated with i/o port 061h[1]. figure 6-7. pit timer pit shadow register the pit registers are shadowed to allow for 0v suspend to save/restore the pit state by reading the pit?s counter and write only registers. the read sequence for the shadow register is listed in f0 index bah (see table 6-29 on page 206). clk0 clk1 clk2 gate0 gate1 gate2 xd[7:0] a[1:0] iow# ior# i/o port 061h[1] i/o port 061h[0] irq0 i/o port pc_beep 1.19318 mhz wr# rd# out0 out1 out2 f0 index 50h[4] f0 index 50h[6] f0 index 50h[3] f0 index 50h[5] 061h[4]
amd geode? sc3200 processor data book 171 core logic module revision 5.1 6.2.6.3 programmable interrupt controller the core logic module contains two 8259a-equivalent programmable interrupt controllers, with eight interrupt request lines each, for a total of 16 interrupts. the pci device supports all x86 modes of operation except special fully nested mode. the two controllers are cascaded inter- nally, and two of the interrupt request inputs are connected to the internal circuitry. this allows a total of 13 externally available interrupt requests. see figure 6-9. each core logic irq signal can be individually selected to as edge- or level-sensitive. the four pci interrupt signals may be routed internally to any pic irq. . figure 6-8. pic interrupt controllers three interrupts are available externally depending upon selected ball multiplexing: 1) irq15 (muxed with gpio11+ri2#), 2) irq14 (muxed with tftd1), and 3) irq9 (muxed with ide_data6) more of the irqs are available through the use of serirq (muxed with gpio39) function. see table 6-4. the core logic module allows pci interrupt signals inta#, intb#, intc# (muxed with gpio19+iochrdy) and intd# (muxed with ide_data7) to be routed internally to any irq signal. the routing can be modified through core logic module?s configuration registers. if this is done, the irq input must be configured to be level- rather than edge- sensitive. irq inputs may be individually programmed to be level-sensitive with the interrupt sensitivity configuration registers at i/o address space 4d0h and 4d1h. pci inter- rupt configuration is discussed in further detail in ?pci compatible interrupts? on page 172. ir0 ir1 ir2 ir3 ir4 ir5 ir6 ir7 irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 internal fpu 8254 timer 0 rtc_irq# ir0 ir1 ir2 ir3 ir4 ir5 ir6 ir7 irq8# irq9 irq10 irq11 irq12 irq13 irq14 irq15 intr table 6-4. pic interrupt mapping master irq mapping irq0 connected to the out0 (system timer) of the internal 8254 pit. irq2 connected to the slave?s intr for a cas- caded configuration. irq8# connected to internal rtc. irq13 connected to the fpu interface of the gx1 module. irq15 interrupts available to other functions irq14 irq12 irq11 irq10 irq9 irq7 irq6 irq5 irq4 irq3 irq1
172 amd geode? sc3200 processor data book core logic module revision 5.1 pic interrupt sequence a typical at-compatible interrupt sequence is as follows. any unmasked interrupt generates the internal intr signal to the cpu. the interrupt controller then responds to the interrupt acknowledge (inta) cycles from the cpu. on the first inta cycle the cascading pr iority is resolved to deter- mine which of the two 8259a c ontrollers output the inter- rupt vector onto the data bus. on the second inta cycle the appropriate 8259a controller drives the data bus with the correct interrupt vector for the highest priority interrupt. by default, the core logic module responds to pci inta cycles because the system inte rrupt controller is located within the core logic module. this may be disabled with f0 index 40h[0]. when the core logic module responds to a pci inta cycle, it holds the pci bus and internally gener- ates the two inta cycles to obt ain the correct interrupt vec- tor. it then asserts trdy# and returns the interrupt vector. pic i/o registers each pic contains registers located in the standard i/o address locations, as shown in table 6-46 "programmable interrupt controller registers" on page 321. an initialization sequence must be followed to program the interrupt controllers. the sequence is started by writing ini- tialization command word 1 (icw1). after icw1 has been written, the controller expects the next writes to follow in the sequence icw2, icw3, and icw4 if it is needed. the operation control words (ocw) can be written after initial- ization. the pic must be programmed before operation begins. since the controllers are operating in cascade mode, icw3 of the master controller should be programmed with a value indicating that the irq2 input of the master interrupt controller is connected to the slave interrupt controller rather than an i/o device as pa rt of the system initialization code. in addition, icw3 of the slave interrupt controller should be programmed with the value 02h (slave id) and corresponds to the input on the master controller. pic shadow register the pic registers are shadowed to allow for 0v suspend to save/restore the pic state by reading the pics write only registers. a write to this register resets the read sequence to the first register. the read sequence for the shadow reg- ister is listed in f0 index b9h. pci compatible interrupts the core logic module allows the pci interrupt signals inta#, intb#, intc#, and intd# (also known in industry terms as pirqx#) to be mapped internally to any irq sig- nal with the pci interrupt steering registers 1 and 2, f0 index 5ch and 5dh. pci interrupts are low-level sensitive, whereas pc/at inter- rupts are positive-edge sensitive; therefore, the pci inter- rupts are inverted before being connected to the 8259a. although the controllers default to the pc/at-compatible mode (positive-edge sensitive), each irq may be individu- ally programmed to be edge or level sensitive using the interrupt edge/level sensitivity registers in i/o port 4d0h and 4d1h. however, if the controllers are programmed to be level-sensitive via icw1, all interrupts must be level- sensitive. figure 6-9 shows the pci interrupt mapping for the master/slave 8259a interrupt controller. figure 6-9. pci and irq interrupt mapping 6.2.7 i/o ports 092h and 061h system control the core logic module supports control functions of i/o ports 092h (port a) and 061h (port b) for ps/2 compatibil- ity. i/o port 092h allows a fast assertion of the a20m# or cpu_rst. (cpu_rst is an internal signal that resets the cpu. it is asserted for 100 s after the negation of por#.) i/o port 061h controls nmi generation and reports system status.the core logic module generates an smi for every internal change of the a20m# state and the smi handler sets the a20m# state inside the gx1 module. this method is used for both the port 092h (ps/2) and port 061h (key- board) methods of controlling a20m#. pci inta#-intd# irq[15:14,12:9,7:3,1] steering registers f0 index 5ch,5dh icw1 4d0h/4d1h 16 1 12 12 4 master/slave 8259a pic intr irq[13,8#,0] 3 level/edge irq3 irq4 irq15 sensitivity
amd geode? sc3200 processor data book 173 core logic module revision 5.1 6.2.7.1 i/o port 092h system control i/o port 092h allows for a fast keyboard assertion of an a20# smi and a fast keyboard cpu reset. decoding for this register may be disabled via f0 index 52h[3]. the assertion of a fast keyboard a20# smi is controlled by either i/o port 092h or by monitoring for the keyboard com- mand sequence (see section 6. 2.8.1 "fast keyboard gate address 20 and cpu reset" on page 173). if bit 1 of i/o port 092h is cleared, the core logic module internally asserts an a20m# , which in turn causes an smi to the gx1 module. if bit 1 is set, a20m# is internally de- asserted, again causing an smi. the assertion of a fast keyb oard reset (wm_rst smi) is controlled by bit 0 in i/o port 092h or by monitoring for the keyboard command sequence (write data = feh to i/o port 64h). if bit 0 is changed from 0 to 1, the core logic module generates a reset to the gx1 module by generating a wm_rst smi. when the wm_rst smi occurs, the bios jumps to the warm reset vector. note that warm reset is not a pin, it is under smi control. 6.2.7.2 i/o port 061h system control through i/o port 061h, the speaker output can be enabled, the status of iochk# and serr# can be read, and the state of the speaker data (timer2 output) and refresh tog- gle (timer1 output) can be re ad back. note that nmi is under smi control. even though the hardware is present, the iochk# ball does not exist. therefore, an nmi from iochk# can not happen. 6.2.7.3 smi generation for nmi figure 6-10 shows how the core logic module can gener- ate an smi for an nmi. note that nmi is not a ball. 6.2.8 keyboard support the core logic module can actively decode the keyboard controller i/o ports 060h, 062h, 064h and 066h, and gener- ate an lpc bus cycle. keyboard positive decoding can be disabled if f0 index 5ah[1] is cleared (i.e., subtractive decoding enabled). 6.2.8.1 fast keyboard gate address 20 and cpu reset the core logic module monitors the keyboard i/o ports 064h and 060h for the fast keyboard a20m# and cpu reset control sequences. if a write to i/o port 060h[1] = 1 after a write takes place to i/o port 064h with data of d1h, then the core logic module asserts the a20m# signal. a20m# remains asserted until cleared by any one of the following: a write to bit 1 of i/o port 092h. a cpu reset of some kind. a write to i/o port 060h[1] = 0 following a write to i/o port 064h with data of d1h. the fast keyboard a20m# and cpu reset can be disabled through f0 index 52h[7]. by default, bit 7 is set, and the fast keyboard a20m# and cpu reset monitor logic is active. if bit 7 is clear, the core logic module forwards the commands to the keyboard controller. by default, the core logic module forces the de-assertion of a20m# during a warm reset. this action may be dis- abled if f0 index 52h[4] is cleared. figure 6-10. smi generation for nmi perr# iochk# f0 index 04h[6] serr# f0 index 04h[8] f0 index 40h[1] i/o port 061h[2] i/o port 061h[3] i/o port 070h[7] parity errors and system errors nmi smi f0 index 04h: pci command register bit 6 = pe (perr# enable) bit 8 = se (serr# enable) f0 index 40h: pci function control register 1 bit 1 = pes (perr# signals serr#) i/o port 061h: port b bit 2 = err_en (perr#/serr# enable) bit 3 = iochk_en (iochk enable) and and and and or and or i/o port 070h: rtc index register (wo) bit 72 = nmi (nmi enable) nmi (no external connection)
174 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.9 power management logic the core logic module integrates advanced power man- agement features including idle timers for common system peripherals, address trap registers for programmable address ranges for i/o or memory accesses, four program- mable general purpose external inputs, clock throttling with automatic speedup for the gx1 clock, software gx1 stop clock, 0v suspend/resume with peripheral shadow regis- ters, and a dedicated serial bus to/from the gx1 module providing power management status. the core logic module is acpi (advanced configuration power interface) compliant. an acpi-compliant system is one whose underlying bios, device drivers, chipset and peripherals conform to revision 1.0 of the acpi specifica- tion. the core logic also supports advanced power man- agement (apm). the sc3200 provides the following support of acpi states: cpu states: c0, c1, and c3. sleep states: ? sl1/sl2 - acpi s1 equivalent. ? sl3 - acpi s3 equivalent. ? sl4 - acpi s4 equivalent. ? sl5 - acpi s5 equivalent. general purpose events: fully programmable gpe0 event block registers. wakeup events: supported through gpwio[2:0] which are powered by standby voltage and generate smis. see registers at f1bar1+i/o offset 0ah and f1bar1+i/o offset 12h. also see section 5.6 "system wakeup control (swc)" on page 132 and table 6-5 "wakeup events capability" on page 175. sc3200 device power management is highly tuned for low power systems. it allows the system designer to implement a wide range of power saving modes using a wide range of capabilities and configuration options. sc3200 controls the following functions directly: the system clocks. core processor power states. wakeup/resume event detection, including general purpose events. power supply and power planes. it also supports systems with an external micro controller that is used as a power management controller. 6.2.9.1 cpu states the sc3200 supports three cpu states: c0, c1 and c3 (the core logic c2 cpu state is not supported). these states are fully compliant with the acpi specification, revi- sion 1.0. these states occur in the working state only (s0/ g0). they have no meani ng when the syst em transitions into a sleep state. for details on the various sleep states, see section 6.2.9.2 "sleep states" on page 175. c0 power state - on in this state the gx1 module executes code. this state has two sub-states: full speed or throttling; selected via the tht_en bit (f1bar1+i/o offset 00h[4]). c1 power state - active idle the sc3200 enters the c1 state, when the halt instruction (hlt) is executed. it exits th is state back to the c0 state upon an nmi, an unmasked interrupt, or an smi. the halt instruction stops program ex ecution and generates a spe- cial halt bus cycle. (see ?usage hints? on page 177.) bus masters are supported in the c1 state and the sc3200 will temporarily exit c1 to perform a bus master transac- tion. c2 power state the sc3200 does not support t he c2 power state. all rele- vant registers and bit fields in the core logic are reserved. c3 power state the sc3200 enters the c3 state, when the p_lvl3 regis- ter (f1bar1+i/o offset 05h) is read. it exits this state back to the c0 state (full speed or throttling, depending on the tht_en bit) upon: an nmi, an unmasked interrupt, or an smi. a bus master request, if enabled via the bm_rld bit (f1bar1+i/o offset 0ch[1]). in this state, the gx1 module is in suspend refresh mode (for details, see the power management section of the amd geode? gx1 processor data book , and section 6.2.9.5 "usage hints" on page 177). pci arbitration should be disabled prior entering the c3 state via the arb_dis bit in the pm2_cnt register (f1bar1+i/o offset 20h[0]) because a pci arbitration event could start after p_lvl3 has been read. after wakeup arb_dis needs to be cleared.
amd geode? sc3200 processor data book 175 core logic module revision 5.1 6.2.9.2 sleep states the sc3200 supports four sleep states (sl1-sl3) and the soft off state (g2/s5). thes e states are fully compliant with the acpi specific ation, revision 1.0. when the slp_en bit (f1bar1+i/o offset 0ch[13]) is set to 1, the sc3200 enters an slx state according to the slp_typx field (f1bar1+i/o o ffset 0ch[12:10]). it exits the sleep state back to the s0 state (c0 state - full speed or throttling, depending on the tht_en bit) upon an enabled power management event. table 6-5 on page 175 lists wakeup events from the various sleep states. sl1 sleep state (acpi s1) in this state the core processor is in 3v suspend mode (all its clocks are stopped, including the memory controller and the display controller). the sdram is placed in self-refresh mode. all other sc3200 system clocks and plls are run- ning. all devices are powered up (pwrcnt[2:1] and onctl# are all asserted). see section 6.2.9.5 "usage hints" on page 177. no reset is performed, when exiting this state. the sc3200 keeps all context in this state. this state corresponds to acpi sleep state s1. sl2 sleep state (acpi s1) in this state, all of the sc3200 clocks are stopped including the plls. selected clocks from the plls can be kept run- ning under program control (f0 index 60h). an exception to this is the clk32 output signal which keeps toggling and the 32 khz oscillator itself. the sdram is placed in self- refresh mode. the pwrcnt1 pin is de-asserted. the sc3200 itself is powered up . the system designer can decide which other system devi ces to power off with the pwrcnt1 pin. no reset is performed, when exiting this state. the sc3200 keeps all context in this state. this state corresponds to acpi sleep state s1, with lower power and longer wake time than in sl1. sl3 sleep state (acpi s3) in this state, the sdram is placed in self-refresh mode, and pwrcnt[2:1] are de-asserted. pwrcnt[2:1] should be used to power off most of the system (except for the sdram). if the save-to-ram feature is used, external cir- cuitry in the sdram interface is required to guarantee data integrity. all sc3200 signals powered by v sb , v sbl or v bat are still functional to allow wakeup and to keep the rtc. the power-up sequence is performed, when exiting this state. this state corresponds to acpi sleep state s3. sl4 and sl5 sleep states (acpi s4 and s5) the sl4 and sl5 states are si milar from the hardware per- spective. in these states, the sc3200 de-asserts pwrcnt[2:1] and onctl#. pwrcnt[2:1] and onctl# should be used to power off the system. all signals pow- ered by v sb , v sbl or v bat are still functional to allow wakeup and to keep the rtc. while in this state, led# can be toggled to give visual noti- fication of this state. acpi function control register (f1bar1+i/o offset 07h[7:6]) is used to control led#. the power-up sequence is performed when exiting this state. this state corresponds to acpi sleep states s4 and s5. table 6-5. wakeup events capability event s0/c1 s0/c3 sl1 sl2 sl3 sl4, sl5 enabled interrupts yes yes yes - - - smi according to table 6-8 yes yes yes - - - sci according to table 6-8 yes yes yes - - - gpio[47:32], gpio[15:0] yes yes yes - - - power button yes yes yes yes yes yes power button override yes yes yes yes yes yes bus master request ye s 1 yesyes--- thermal monitoring yes yes yes yes yes yes usb yes yes yes yes - - sdata_in2 (ac97) yes yes yes yes - - irrx1 (infrared) yes yes yes yes - - gpwio[2:0] yes yes yes yes yes yes ri2# (uart2) yes yes yes yes - - rtc yes yes yes yes yes yes 1. temporarily exits state.
176 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.9.3 power planes control the sc3200 supports up to three power planes. three sig- nals are used to control these power planes. table 6-6 describes the signals and when each is asserted. these signals allow control of the power of system devices and the sc3200 itself. table 6-7 describes the sc3200 power planes with respect to the different sleep and global states. the sc3200 power planes are controlled externally by the three signals (i.e., the syst em designer should make sure the system design is such that table 6-7 is met) for all sup- ported sleep states. v sb and v bat are not controlled by any control signal. v sb exists as long as the ac power is plugged in (for desktop systems) or the main battery is charged (for mobile sys- tems). v bat exists as long as the rtc battery is charged. the case in which v sb does not exist is called mechanical off (g3). 6.2.9.4 power management events the sc3200 supports power management events that can manage: transition of the system from a sleep state to a work state. this is done by the hardware. these events are defined as wakeup events. enabled wakeup events to set the wak_sts bit (f1bar1+i/o offset 08h[15]) to 1, when transitioning the system back to the working state. generation of an interrupt. this invokes the relevant software driver. the interrupt can either be an smi or sci (selected by the sci_en bit, f1bar1+i/o offset 0ch[0]). these events are defined as interrupt events. table 6-8 lists the power management events that can generate an sci or smi. table 6-6. power planes control signals vs. sleep states signal s0 sl1 sl2 sl3 sl4 and sl5 pwrcnt111000 pwrcnt211100 onctl# 00001 table 6-7. power planes vs. sleep/global states sleep/ global state v core , v i/o, v pll v sb , v sbl v bat s0, sl1 and sl2 on on on or off sl3, sl4 and sl5 off on on or off g3 off off on no power off off off illegal on off on or off table 6-8. power management events event sci smi power button yes yes power button override yes - bus master request yes - thermal monitoring yes yes usb yes yes rtc yes yes acpi timer yes yes gpio yes yes sdata_in2 (ac97) yes yes irrx1 yes yes ri2# yes yes gpwio yes yes internal smi signal yes -
amd geode? sc3200 processor data book 177 core logic module revision 5.1 power button the power button (pwrbtn#) input provides two events: a wake request, and a sleep request. for both these events, the pwrbtn# signal is debounced (i.e., the signal state is transferred only after 14 to 16 ms without transitions, to ensure that the signal is no longer bouncing). acpi is non-functional and all acpi outputs are undefined when the power-up sequence does not include using the power button. susp# is an internal signal generated from the acpi block. without an acpi reset, susp# can be per- manently asserted. if the use_susp bit in ccr2 of gx1 module is enabled (index c2h[ 7] = 1), the cpu will stop. if acpi functionality is desir ed, or the situation described above avoided, the power butt on must be toggled. this can be done externally or internally. gpio63 is internally con- nected to pwrbtn#. to toggle the power button with soft- ware, gpio63 must be programmed as an output using the normal gpio programming protocol (see section 6.4.1.1 "gpio support registers" on page 240). gpio63 must be pulsed low for at least 16 ms and not more than 4 sec. asserting por# has no effect on acpi. if por# is asserted and acpi was active prior to por#, then acpi will remain active after por#. therefore, bios must ensure that acpi is inactive before gpio63 is pulsed low. power button wake event - detection of a high-to-low transition on the debounced pwrbtn# input signal when in sl1 to sl5 sleep states. the system is considered in the sleep state, only after it actually transitioned into the state and not only according to the slp_typ field. in reaction to this event, the pwrbtn_sts bit (f1bar1+i/ o offset 08h[8]) is set to 1 and a wakeup event or an inter- rupt is generated (note that this is regardless of the pwrbtn_en bit, f1bar1+i/o offset 0ah[8]). power button sleep event - detection of a high-to-low transition on the debounced pwrbtn# input signal, when in the working state (s0). in reaction to this event, the pwrbtn_sts bit is set to 1. when both the pwrbtn_sts bit and the pwrbtn_en bit are set to 1, an sci interrupt is gener- ated. when sci_en bit is 0, onctl# and pwrcnt[2:1] are de-asserted immediately regardless of the pwrbtn_en bit. power button override when pwrbtn# is 0 for more than four seconds, onctl# and pwrcnt[2:1] are de-asse rted (i.e., the system transi- tions to the sl5 state, ?sof t off?). this power management event is called the power button override event. in reaction to this event, the pwrbtn_sts bit is cleared to 0 and the pwrbtnor_sts bit (f1bar1+i/o offset 08h[11]) is set to 1. thermal monitoring the thermal monitoring event (thrm#) enables control of acpi-os control. when the thrm# signal transitions from high-to-low, the thrm_sts bit (f1bar1+i/o offset 10h[5]) is set to 1. if the thrm_en bit (f1bar1+i/o of fset 12h[5]) is also set to 1, an interrupt is generated. sdata_in2, irrx1, ri2# section 5.4.1 "sio control and configuration registers" on page 113 for control and operation. 6.2.9.5 usage hints during initialization, the bios should: ? clear the susp_hlt bit in ccr2 (gx1 module, index c2h[3]) to 0. this is needed for compliance with c0 definition of acp i, when the halt instruction (hlt) is executed. ? disable the susp_3v option in c3 power state (f0 index 60h[2]). ? disable the susp_3v option in sl1 sleep state (f0 index 60h[1]). smm code should clear the clk_stp bit in the pm clock stop control register (gx_base+memory offset 8500h[0]) to 0 when entering c3 state. smm code should correctly se t the clk_stp bit in the pm clock stop control register (gx_base+memory offset 8500h[0]) when entering the sl1, sl2, and sl3 states.
178 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.10 power management programming the power management resources provided by a com- bined gx1 module and core logic module based system supports a high efficiency power management implementa- tion. the following explanations pertain to a full-featured ?notebook? power managemen t system. the extent to which these resources are employed depends on the appli- cation and on the discretion of the system designer. power management resources can be grouped according to the function they enable or support. the major functions are as follows: apm support cpu power management ? suspend modulation ? 3v suspend ?save-to-disk peripheral power management ? device idle timers and traps ? general purpose timers ? acpi timer register ? power management smi status reporting registers included in the following subsections are details regarding the registers used for configuring power management fea- tures. the majority of these registers are directly accessed through the pci configuration register space designated as function 0 (f0). however, included in the discussions are references to f1barx+i/o offs et xxh. this refers to regis- ters accessed through base address registers in function 1 (f1) at index 10h (f1bar0) and index 40h (f1bar1). 6.2.10.1 apm support many notebook computers rely solely on an advanced power management (apm) driver for enabling the operat- ing system to power-manage the cpu. apm provides sev- eral services which enhance the system power management; but in its current form, apm is imperfect for the following reasons: apm is an os-specific driver, and may not be available for some operating systems. application support is inconsistent. some applications in foreground may prevent idle calls. apm does not help with suspend determination or peripheral power management. the core logic module provides two entry points for apm support: software cpu suspend control via the cpu suspend command register (f0 index aeh) software smi entry via the software smi register (f0 index d0h). this allows the apm bios to be part of the smi handler. 6.2.10.2 cpu power management the three greatest power consumers in a system are the display, the hard drive, and the cpu. the power manage- ment of the first two is relatively straightforward and is dis- cussed in section 6.2.10.3 "peripheral power management" on page 180. apm, if available, is used primarily by cpu power manage- ment since the operat ing system is most capable of report- ing the idle condition. additional resources provided by the core logic module supplement apm by monitoring exter- nal activity and power managing the cpu based on the system demands. the two proc esses for power managing the cpu are suspend modulation and 3v suspend. suspend modulation suspend modulation works by asserting and de-asserting the internal susp# signal to the gx1 module for config- urable durations. when susp# is asserted to the gx1 module, it enters an idle state during which time the power consumption is significantly reduced. even though the pci clock is still running, the gx 1 module stops the clocks to its core when susp# is asserted. by modulating susp# a reduced frequency of operation is achieved. the suspend modulation feature works by assuming that the gx1 module is idle unless external activity indicates otherwise. this approach effectively slows down the gx1 module until external activity indicates a need to run at full speed, thereby reducing power consumption. this approach is the opposite of th at taken by most power man- agement schemes in the industry, which run the system at full speed until a period of inactivity is detected, and then slows down. suspend modulation, the more aggressive approach, yields lower power consumption. suspend modulation serves as the primary cpu power management mechanism when apm is not present. it also acts as a backup for situations where apm does not cor- rectly detect an idle condition in the system. to provide high-speed performance when needed, susp# modulation is temporarily di sabled any time system activity is detected. when this happens, the gx1 module is ?instantly? converted to full speed for a programmed dura- tion. system activities in the core logic module are asserted as: any unmasked irq, accessing port 061h, any asserted smi, and/or accessing the video processor mod- ule interface. the graphics controller is integrated in the gx1 module. therefore, the indication of video activity is sent to the core logic module via the serial link (see sect ion 6.2.2 "pse- rial interface" on page 159 for more information on serial link) and is automatically dec oded. video activity is defined as any access to the vga register space, the vga frame buffer, the graphics accelerator control registers and the configured graphics frame buffer.
amd geode? sc3200 processor data book 179 core logic module revision 5.1 the automatic speedup events (video and irq) for sus- pend modulation should be used together with software- controlled speedup registers for major i/o events such as any access to the fdc, hdd, or parallel/serial ports, since these are indications of major system activities. when major i/o events occur, suspend modulation should be temporarily disabled using the procedures described in the power management registers in the following subsections. if a bus master (ultradma/33, audio, usb) request occurs, the gx1 module automatically de-asserts suspa# and grants the bus to the requesting bus master. when the bus master de-asserts req#, susp a# reasserts. this does not directly affect the suspend modulation programming. configuring suspend modulation: control of the sus- pend modulation feature is accomplished using the sus- pend modulation and suspend configuration registers (f0 index 94h and 96h, respectively). the suspend configuration r egister contains the global power management enable bit, as well as the enables for the individual activity speedup timers. the global power management bit must be enabled for suspend modulation and all other power management resources to function. bit 0 of the suspend configuration register enables sus- pend modulation. bit 1 controls how smi events affect sus- pend modulation. in general this bit should be set to 1, which causes smis to disabl e suspend modulation until it is re-enabled by the smi handler. the suspend modulation register controls two 8-bit counters that represent the number of 32 s intervals that the internal susp# signal is asserted and then de- asserted to the gx1 module. these counters define a ratio which is the effective frequen cy of operation of the system while suspend modulation is enabled. the irq and video speedup timer count registers (f0 index 8ch and 8dh) configure the amount of time which suspend modulation is disabled when the respective events occur. smi speedup disable: if the suspend modulation feature is being used for cpu power management, the occurrence of an smi disables suspend mo dulation so that the system operates at full speed while in smm. there are two meth- ods used to invoke this via bi t 1 of the suspend configura- tion register. 1) if f0 index 96h[1] = 0: use the irq speedup timer (f0 index 8ch) to temporarily disable suspend modu- lation when an smi occurs. 2) if f0 index 96h[1] = 1: disable suspend modulation when an smi occurs until a read to the smi speedup disable register (f1bar0+i/o offset 08h). the smi speedup disable regi ster prevents vsa software from entering suspend modulation while operating in smm. the data read from this register can be ignored. if the suspend modulation feature is disabled, reading this i/ o location has no effect. 3 volt suspend the core logic module supports the stopping of the cpu and system clocks for a 3v sus pend state. if appropriately configured, via the clock stop control register (f0 index bch), the core logic module asserts internal susp_3v after it has gone through the susp#/suspa# handshake. susp_3v is a state indicator, indicating that the system is in a low-activity state and suspend modulation is active. this indicator can be used to put the system into a low- power state (the system clock can be turned off). internal susp_3v is connected to the enable control of the clock generators, so that the clocks to the cpu and the core logic module (and most other system devices) are stopped. the core logic modu le continues to decrement all of its device timers and respond to external smi inter- rupts after the input clock has been stopped, as long as the 32 khz clock continues to oscillate. any smi event or unmasked interrupt causes the core logic module to de- assert susp_3v, restarting t he system clocks. as the cpu or other device might include a pll, the core logic module holds susp# active for a pre-programmed period of delay (the pll re-sync delay) that varies from 0 to 15 ms. after this period has expired, the core logic module de-asserts susp#, stopping suspend. smi# is held active for the entire period, so that the cpu reenters smm when the clocks are restarted. save-to-disk save-to-disk is supported by the core logic module. in this state, the power is typically removed from the core logic module and from the entire sc3200, causing the state of the legacy peripheral devices to be lost. shadow registers are provided for devices which allow their state to be saved prior to removing power. this is necessary because the legacy at peripheral devices used several write only registers. to restore the exact state of these devices on resume, the write only register values are ?shadowed? so that the values can be saved by the power management software. the pc/at compatible keyboard controller (kbc) and floppy port (fdc) do not exist in the sc3200. however, it is possible that one is attached on the isa bus or the lpc bus (e.g., in a superi/o device). some of the kbc and fdc registers are shadowed because they cannot be safely read. additional shadow registers for other functions are described in table 6-29 "f0: pci header/bridge configura- tion registers for gpio and lpc support" on page 206. f eff = f gx1 x asserted count asserted count + de-asserted count
180 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.10.3 peripheral power management the core logic module provides peripheral power man- agement using a combination of device idle timers, address traps, and general purpose i/o pins. idle timers are used in conjunction with traps to support powering down peripheral devices. device idle timers and traps idle timers are used to power manage a peripheral by determining when the peripheral has been inactive for a specified period of time, and removing power from the peripheral at the end of that time period. idle timers are provided for the commonly-used peripherals (fdc, ide, parallel/serial ports, and mouse/keyboard). in addition, there are three use r-defined timers that can be configured for either i/o or memory ranges. the idle timers are 16-bit countdown timers with a one sec- ond timebase or prescaler, providing a timeout range of 1 to 65536 seconds (1092 minutes) (18 hours). the input clock is 32 khz. very small count values have some error since the prescaler is free-running. (see the next subsec- tion "general purpose timers" for further discussion on prescaler value limitations.) when the idle timer count r egisters are loaded with a non- zero value and enabled, the timers decrement until one of two possibilities happens: a bus cycle occurs at that i/o or memory range, or the timer decrements to zero. if a bus cycle occurs, the timer is reloaded and begins dec- rementing again. if the timer decrements to zero, and power management is enabled (f0 index 80h[0] = 1), the timer generates an smi. when an idle timer generates an smi, the smi handler manages the peripheral power, disables the timer, and enables the trap. the next time an event occurs, the trap generates an smi. this time, the smi handler applies power to the peripheral, resets the timer, and disables the trap. relevant registers for controlli ng device idle timers are: f0 index 80h, 81h, 82h, 93h, 98h-9eh, and ach. relevant registers for controlling user defined device idle timers are: f0 index 81h, 82h, a0h, a2h, a4h, c0h, c4h, c8h, cch, cdh, and ceh. although not considered as device idle timers, two addi- tional timers are provided by the core logic module. the video idle timer used for suspend-determination and the vga timer used for softvga. the programming bits for these timers are: f0 index 81h[7], video access idle timer enable f0 index 82h[7], video access trap enable f0 index a6h[15:0], video timer count f0 index 83h[3], vga timer enable f0 index 8bh[6], vga timer base f0 index 8eh[7:0], vga timer count general purpose timers the core logic module contains two general purpose idle timers, general purpose timer 1 (f0 index 88h) and gen- eral purpose timer 2 (f0 index 8ah). these two timers are similar to the device idle time rs in that they count down to zero unless re-triggered, and generate an smi when they reach zero. however, these are 8-bit timers instead of 16 bits, they have a programmable timebase, and the events which reload these timers are configurable. these timers are typically used for an indi cation of system inactivity for suspend determination. general purpose timer 1 can be re-triggered by activity to any of the configured user defined devices, keyboard and mouse, parallel and serial, floppy disk, or hard disk. general purpose timer 2 can be re-triggered by a transi- tion on the gpio7 signal (if gpio7 is properly configured). when a general purpose timer is enabled or when an event reloads the timer, the timer is loaded with the config- ured count value. upon expiration of the timer an smi is generated and a status flag is set. once expired, this counter must be re-initialized by disabling and enabling it. the timebase or prescaler for both general purpose tim- ers can be configured as either 1 second (default) or 1 mil- lisecond. the 32 khz clock feeds the prescaler. the registers at f0 index 89h and 8bh are the control registers for the general purpose timers. the prescaler (1 millisecond or 1 second) that feeds the timers is free-running; meaning that the first count decre- ment will not be correct. the decrement time can be as short as 0 or as long as the prescaler. the actual time for the decrement to occur can not be determined since the current prescaler value can not be read. a periodic timer can be achieved after the first timer smi, because when retriggered, the prescaler will be at or very nearly at the maximum value. any software using these timers must understand this limitation. small count values have the most error with a value of 1having the largest error. acpi timer register the acpi timer register (f1bar0+i/o offset 1ch or at f1bar1+i/o offset 1ch) provides the acpi counter. the counter counts at 14.31818/4 mhz (3.579545 mhz). if smi generation is enabled (f0 index 83h[5] = 1), an smi or sci is generated when bit 23 toggles.
amd geode? sc3200 processor data book 181 core logic module revision 5.1 power management smi status reporting registers the core logic module updates status registers to reflect the smi sources. power management smi sources are the device idle timers, address traps, and general purpose i/o pins. power management events are reported to the gx1 mod- ule through the active low smi# signal. when an smi is ini- tiated, the smi# signal is asserted low and is held low until all smi sources are cleared. at that time, smi# is de- asserted. all smi sources report to the top level smi status register (f1bar0+i/o offset 02h) and the top level smi status mirror register (f1bar0+i/o offset 00h). the top smi sta- tus and status mirror registers are the top level of hierarchy for the smi handler in determining the source of an smi. these two registers are identical except that reading the register at f1bar0+i/o offset 02h clears the status. since all smi sources report to the top level smi status register, many of its bits combine a large number of events requiring a second level of sm i status reporting. the sec- ond level of smi status reporting is set up very much like the top level. there are two st atus reporting registers, one ?read only? (mirror) and one ?read to clear?. the data returned by reading either offset is the same, the difference between the two being that the smi can not be cleared by reading the mirror register. figure 6-11 on page 181 shows an example smi tree for checking and clearing the source of general purpose tim- ers and the user defined trap generated smi. figure 6-11. general purpose timer and udef trap smi tree example smi# asserted smm software reads smi header if bit x = 0 (internal smi) if bit x = 1 (external smi) call internal smi handler to take appropriate action gx1 core logic f1bar0+i/o read to clear to determine top-level source of smi f1bar0+i/o offset 06h read to clear bits [15:10] bits [8:0] bit 9 gtmr_trp_smi offset 02h module to determine second-level source of smi bit 5 pci_trp_smi bit 4 udef3_trp_smi bit 3 udef2_trp_smi bit 2 udef1_trp_smi bit 1 gpt2_smi bit 0 gpt1_smi take appropriate action other_smi other_smi if bit 9 = 1, source of smi is gp timer or udef trap bits [15:6] rsvd top level second level smi de-asserted after all smi sources are cleared (i.e., top and second levels - note so me sources may have a third level) module
182 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.10.4 power manageme nt programming summary table 6-9 provides a programming register summary for the power management timers, traps, and functions. for complete bit information regarding the registers listed in table 6-9, refer to section 6.4.1 "bridge, gpio, and lpc registers - function 0" on page 206. table 6-9. device power management programming summary device power management resource located at f0 index xxh unless otherwise noted enable configuration second level smi status/no clear second level smi status/with clear global timer enable 80h[0] n/a n/a n/a keyboard / mouse idle timer 81h[3] 93h[1:0] 85h[3] f5h[3] parallel / serial idle timer 81h[2] 93h[1:0] 85h[2] f5h[2] floppy disk idle timer 81h[1] 9ah[15:0], 93h[7] 85h[1] f5h[1] video idle timer 1 81h[7] a6h[15:0] 85h[7] f5h[7] vga timer 2 83h[3] 8eh[7:0] f1bar0+i/o offset 00h[6] f1bar0+i/o offset 02h[6] primary hard disk idle timer 81h[0] 98h[15:0], 93h[5] 85h[0] f5h[0] secondary hard disk idle timer 83h[7] ach[15:0], 93h[4] 86h[4] f6h[4] user defined device 1 idle timer 81h[4] a0h[15:0], c0h[31:0], cch[7:0] 85h[4] f5h[4] user defined device 2 idle timer 81h[5] a2h[15:0], c4h[31:0], cdh[7:0] 85h[5] f5h[5] user defined device 3 idle timer 81h[6] a4h[15:0], c8h[31:0], ceh[7:0] 85h[6] f5h[6] global trap enable 80h[2] n/a n/a n/a keyboard / mouse trap 82h[3] 9eh[15:0] 93h[1:0] 86h[3] f6h[3] parallel / serial trap 82h[2] 9ch[15:0], 93h[1:0] 86h[2] f6h[2] floppy disk trap 82h[1] 93h[7] 86h[1] f6h[1] video access trap 82h[7] n/a 86h[7] f6h[7] primary hard disk trap 82h[0] 93h[5] 86h[0] f6h[0] secondary hard disk trap 83h[6] 93h[4] 86h[5] f6h[5] user defined device 1 trap 82h[4] c0h[31:0], cch[7:0] f1bar0+i/o offset 04h[2] f1bar0+i/o offset 06h[2] user defined device 2 trap 82h[5] c4h[31:0], cdh[7:0] f1bar0+i/o offset 04h[3] f1bar0+i/o offset 06h[3] user defined device 3 trap 82h[6] c8h[31:0], ceh[7:0] f1bar0+i/o offset 04h[4] f1bar0+i/o offset 06h[4] general purpose timer 1 83h[0] 88h[7:0], 89h[7:0], 8bh[4] f1bar0+i/o offset 04h[0] f1bar0+i/o offset 06h[0] general purpose timer 2 83h[1] 8ah[7:0], 8bh[5,3,2] f1bar0+i/o offset 04h[1] f1bar0+i/o offset 06h[1] suspend modulation 96h[0] 94h[15:0], 96h[2:0] n/a n/a video speedup 80h[4] 8dh[7:0], a8h[15:0] n/a n/a irq speedup 80h[3] 8ch[7:0] n/a n/a 1. this function is used for suspend determination. 2. this function is used for softvga.
amd geode? sc3200 processor data book 183 core logic module revision 5.1 6.2.11 gpio interface up to 64 gpios in the in the core logic module are pro- vided for system control. for further information, see sec- tion 4.2 "multiplexing, inte rrupt selection, and base address registers" on page 88 and table 6-30 "f0bar0+i/o offset: gpio configuration registers" on page 240. note: not all gpios are available on sc3200 balls. gpios [63:42], [31:21], and [5:2] are reserved. 6.2.12 integrated audio the core logic module provides hardware support for the virtual (soft) audio subsystem as part of the virtual system architecture ? (vsa ? ) technology for capture and playback of audio using an external codec. this eliminates much of the hardware traditionally associated with audio functions. this hardware support includes: six-channel buffered pci bus mastering interface. ac97 version 2.0 compatible interface to the codec. any codec, which supports an independent input and output sample rate conversion interface, can be used with the core logic module. additional hardware provides the necessary functionality for vsa. this hardware includes the ability to: generate an smi to alert software to update required data. an smi is generated when either audio buffer is half empty or full. if the buffers become completely empty or full, the empty bit is asserted. generate an smi on i/o traps. trap accesses for sound card compatibility at either i/o port 220h-22fh, 240h-24fh, 260h-26fh, or 280h-28fh. trap accesses for fm compatibility at i/o port 388h- 38bh. trap accesses for midi uart interface at i/o port 300h- 301h or 330h-331h. trap accesses for serial input and output at com2 (i/o port 2f8h-2ffh) or com4 (i/o port 2e8h-2efh). support trapping for low (i/o port 00h-0fh) and/or high (i/o port c0h-dfh) dma accesses. support hardware status register reads in core logic module, minimizing smi overhead. support is provided for software-generated irqs on irq 2, 3, 5, 7, 10, 11, 12, 13, 14, and 15. the following subsections incl ude details of the registers used for configuring the audio interface. the registers are accessed through f3 index 10h, the base address regis- ter (f3bar0) in function 3. f3bar0 sets the base address for the audio support registers as shown in table 6-37 "f3: pci header regist ers for audio configuration" on page 279. 6.2.12.1 data transport hardware the data transport hardware can be broadly divided into two sections: bus mastering and the codec interface. audio bus masters the core logic module audio hardware includes six pci bus masters (three for input and three for output) for trans- ferring digitized audio between memory and the external codec. with these bus master engines, the core logic module off-loads the cpu and improves system perfor- mance. the programming interface defines a simple scatter/gather mechanism allowing large transfer blocks to be scattered to or gathered from memory. this cuts down on the number of interrupts to and interactions with the cpu. the six bus masters that directly drive specific slots on the ac97 interface are described in table 6-10. table 6-10. bus masters that drive specific slots of the ac97 interface audio bus master # slots description 0 3 and 4 32-bit output to codec. left and right channels. 1 3 and 4 32-bit input from codec. left and right channels. 2 5 16-bit output to codec. 3 5 16-bit input from codec. 4 6 or 11 16-bit output to codec. slot in use is determined by f3bar0+memory offset 08h[19]. 5 6 or 11 16-bit input from codec. slot in use is determined by f3bar0+memory offset 08h[20].
184 amd geode? sc3200 processor data book core logic module revision 5.1 physical region descriptor table address before the bus master starts a master transfer it must be pro- grammed with a pointer (prd table address register) to a physical region descriptor table. this pointer sets the start- ing memory location of the physical region descriptors (prds). the prds describe the areas of memory that are used in the data transfer. the descriptor table entries must be aligned on a 32-byte boundary and the table cannot cross a 64 kb boundary in memory. physical region descriptor format each physical memory region to be transferred is described by a physical region descriptor (prd) as illus- trated in table 6-11. when the bus master is enabled (command register bit 0 = 1), data transfer proceeds until each prd in the prd table has been transferred. the bus master does not cache prds. the prd table consists of two dwords. the first dword contains a 32-bit pointer to a buffer to be transferred. the second dword contains the size (16 bits) of the buffer and flags (eot, eop, jmp). the description of the flags are as follows: eot bit - if set in a prd, this bit indicates the last entry in the prd table (bit 31). the last entry in a prd table must have either the eot bit or the jmp bit set. a prd can not have both the jmp and eot bits set. eop bit - if set in a prd and the bus master has completed the prd?s transfer, the end of page bit is set (status register bit 0 = 1) and an smi is generated. if a second eop is reached due to the completion of another prd before the end of page bit is cleared, the bus master error bit is set (status register bit 1 = 1) and the bus master pauses. in this paused condition, reading the status register clears both the bus master error and the end of page bits and the bus master continues. jmp bit - this prd is special. if set, the memory region physical base address is now the target address of the jmp. the target address must be on a 32-byte boundary so bits[4:0] must be written to 0. there is no data transfer with this prd. this prd allows the creation of a looping mechanism. if a prd table is created with the jmp bit set in the last prd, the prd table does not need a prd with the eot bit set. a prd can not have both the jmp and eot bits set. programming model the following discussion explains, in steps, how to initiate and maintain a bus master transfer between memory and an audio slave device. in the steps listed below, the reference to ?example? refers to figure 6-12 "prd table example" on page 185. 1) software creates a prd table in system memory. each prd entry is 8 bytes long; consisting of a base address pointer and buffer size. the maximum data that can be transferred from a prd entry is 64 kb. a prd table must be aligned on a 32-byte boundary. the last prd in a prd table must have the eot or jmp bit set. example - assume the data is outbound. there are three prds in the example prd table. the first two prds (prd_1, prd_2) have only the eop bit set. the last prd (prd_3) has only the jmp bit set. this example creates a prd loop. 2) software loads the starting address of the prd table by programming the prd table address register. example - program the prd table address register with address_3. 3) software must fill the buffers pointed to by the prds with audio data. it is not absolutely necessary to fill the buffers; however, the buffer filling process must stay ahead of the buffer emptying. the simplest way to do this is by using the eop flags to generate an smi when a prd is empty. example - fill audio buffer_1 and audio buffer_2. the smi generated by the eop from the first prd allows the software to refill audio buffer_1. the second smi refills audio buffer_2. the third smi refills audio buffer_1 and so on. table 6-11. physical region descriptor format dword byte 3 byte 2 byte 1 byte 0 313029282726252423222120191817161514131211109876543210 0 memory region base address [31:1] (audio data buffer) 0 1e o t e o p j m p reserved size [15:1] 0
amd geode? sc3200 processor data book 185 core logic module revision 5.1 4) read the smi status register to clear the bus master error and end of page bits (bits 1 and 0). set the correct direction to the read or write control bit (command register bit 3). note that the direction of the data transfer of a particular bus master is fixed and therefore the direction bit must be programmed accordingly. it is assumed that the codec has been properly programmed to receive the audio data. engage the bus master by writing a ?1? to the bus master control bit (command register bit 0). the bus master reads the prd entry pointed to by the prd table address register and increments the address by 08h to point to the next prd. the transfer begins. example - the bus master is now properly pro- grammed to transfer audio buffer_1 to a specific slot(s) in the ac97 interface. 5) the bus master transfers data to/from memory responding to bus master requests from the ac97 interface. at the completion of each prd, the bus mas- ter?s next response depends on the settings of the flags in the prd. example - at the completion of prd_1 an smi is gen- erated because the eop bit is set while the bus mas- ter continues on to prd_2. the address in the prd table address register is incremented by 08h and is now pointing to prd_3. the smi status register is read to clear the end of page status flag. since audio buffer_1 is now empty, the software can refill it. at the completion of prd_2 an smi is generated because the eop bit is set. the bus master then con- tinues on to prd_3. the address in the prd table address register is increm ented by 08h. the dma smi status register is read to clear the end of page status flag. since audio buffer_2 is now empty, the software can refill it. audio buffer_1 has been refilled from the previous smi. prd_3 has the jmp bit set. this means the bus mas- ter uses the address stored in prd_3 (address_3) to locate the next prd. it does not use the address in the prd table address register to get the next prd. since address_3 is the location of prd_1, the bus master has looped the prd table. stopping the bus master can be accomplished by not read- ing the smi status register end of page status flag. this leads to a second eop which causes a bus master error and pauses the bus master. in effect, once a bus master has been enabled it never has to be disabled, just paused. the bus master cannot be disabled unless the bus master has been paused or has reached an eot. figure 6-12. prd table example address_1 size_1 eot = 0 audio buffer_1 audio buffer_2 size_1 size_2 address_1 eop = 1 jmp = 0 address_2 size_2 eot = 0 eop = 1 jmp = 0 address_3 don?t care eot = 0 eop = 0 jmp = 1 prd_1 prd_2 prd_3 address_2 address_3 32-byte boundary
186 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.12.2 ac97 codec interface the ac97 codec (e.g., lm4548) is the master of the serial interface and generates the clocks to core logic module. figure 6-13 shows the signal connections between two codecs and the sc3200: codec1 can be ac97 rev. 1.3 or higher compliant. codec2 is optional, but must be compliant with ac97 2.0 or higher. (for specifics on the serial interface, refer to the appropriate codec manufacturer?s data book.) ? sdata_in2 has wakeup capability. (see section 5.6 "system wakeup control (swc)" on page 132.) ? if sdata_in2 is not used it must be connected to v ss . ? if an amc97 codec is used (as codec2), it should be connected to sdata_in2 and sdata_in should be connected to v ss . for pc speaker synthesis, the core logic module outputs the pc speaker signal on the pc_beep pin which is connected to the pc_beep input of the ac97 codec. note that pc_beep is muxed with gpio16 and must be programmed via pmr[0] (see table 4-2 on page 88.) codec configuration/control registers the codec 32-bit related registers: gpio status and control registers ? codec gpio status register (f3bar0+memory offset 00h) ? codec gpio control register (f3bar0+memory offset 04h) codec status register (f3bar0+memory offset 08h) codec command register (f3bar0+memory offset 0ch) codec gpio status and control registers: the codec gpio status and c ontrol registers are used for codec gpio related tasks such as enabling a codec gpio interrupt to cause an smi. codec status register: the codec status register stores the codec status word. it is updated every valid status word slot. codec command register: the codec command register writes the control word to the codec. by writing the appropriate control words to this port, the features of the codec can be controlled. the contents of this register are written to the codec during the control word slot. the bit formats for these registers are given in table 6-38 "f3bar0+memory offset: audio configuration registers" on page 280. figure 6-13. ac97 v2.0 c odec signal connections bit_clk pc_beep sdata_out ac97_clk pc_beep sdata_out sdata_in codec1 bit_clk xtal_i sync sync pc_beep sdata_out sdata_in2 bit_clk xtal_i sync sdata_in2 codec2 (optional) sdata_in amd geode? sc3200 processor
amd geode? sc3200 processor data book 187 core logic module revision 5.1 6.2.12.3 vsa technolo gy support hardware the core logic module incorporates the required hard- ware in order to support the virtual system architecture ? (vsa) technology for capture and playback of audio using an external codec. this eliminates much of the hardware traditionally associated with indu stry standard audio func- tions. vsa technology vsa technology provides a framework to enable software implementation of traditionally hardware-only components. vsa software executes in system management mode (smm), enabling it to execute transparently to the operating system, drivers and applications. the vsa design is ba sed upon a simple model for replac- ing hardware components with software. hardware to be virtualized is merely replaced with simple access detection circuitry which asserts the smi# (system management interrupt) internal signal when hardware accesses are detected. the current executi on stream is immediately pre- empted, and the processor enters smm. the smm system software then saves the proce ssor state, initializes the vsa execution environment, decodes the smi source and dis- patches handler routines which have registered requests to service the decoded smi source. once all handler routines have completed, the processo r state is restored and nor- mal execution resumes. in th is manner, hardware accesses are transparently replaced wit h the execution of smm han- dler software. historically, smm software was used primarily for the single purpose of facilitating active power management for note- book designs. that software?s only function was to manage the power up and down of devices to save power. with high performance processors now available, it is feasible to implement, primarily in smm software, pc capabilities tra- ditionally provided by hardware. in contrast to power man- agement code, this virtualization software generally has strict performance requirement s to prevent application per- formance from being significantly impacted. audio smi related registers the smi related registers consist of: audio smi status reporting registers: ? top level smi mirror and status registers (f1bar0+memory offset 00h/02h) ? second level smi status registers (f3bar0+memory offset 10h/12h) i/o trap smi and fast write status register (f3bar0+memory offset 14h) i/o trap smi enable register (f3bar0+memory offset 18h) audio smi status reporting registers: the top smi status mirror and status registers are the top level of hierarchy for the smi handler in determining the source of an smi. these two registers are at f1bar0+memory offset 00h (status mirror) and 02h (sta- tus). the registers are identical except that reading the reg- ister at f1bar0+memory offset 02h clears the status. the second level of audio smi status reporting is set up very much like the top level. there are two status reporting registers, one ?read only? (mirror) and one ?read to clear?. the data returned by reading either offset is the same (i.e., smi was caused by an audio related event). the difference between f3bar0+memory offs et 10h (status mirror) and 12h (status) is in the ability to clear the smi source at 12h. figure 6-14 on page 188 shows an smi tree for checking and clearing the source of an audio smi. only the audio smi bit is detailed here. for details regarding the remaining bits in the top smi status mirr or and status registers refer totable 6-33 "f1bar0+i/o offset: smi status registers" on page 253. i/o trap smi and fast write status register: this 32-bit read-only register (f3bar0+memory offset 14h) not only indicates if the enabled i/o trap generated an smi, but also contains fast path write related bits. i/o trap smi enable register: the i/o trap smi enable register (f3bar0+memory offset 18h) allows traps for specified i/o addresses and config- ures generation for i/o events. it also contains the enabling bit for fast path read/write features. status fast path read/write status fast path read ? if enabled, the core logic module intercepts and responds to reads to several status regis- ters. this speeds up operations, and prevents smi genera- tion for reads to these registers. this process is called status fast path read. status fast path read is enabled via f3bar0+memory offset 18h[4]. in status fast path read the core logic module responds to reads of the following addresses: 388h-38bh, 2x0h, 2x1h, 2x2h, 2x3h, 2x8h and 2x9h note that if neither sound card or fm i/o mapping is enabled, then status read trapping is not possible. fast path write ? if enabled, the core logic module cap- tures certain writes to several i/o locations. this feature prevents two smis from being asserted for write operations that are known to take two accesses (the first access is an index and the second is data). this process is called fast path write. fast path write is enabled in via f3bar0+memory offset 18h[11]. fast path write captures the data and address bit 1 (a1) of the first access, but does not generate an smi. a1 is stored in f3bar0+memory offset 14h[15]. the second access causes an smi, and the data and address are captured as in a normal trapped i/o.
188 amd geode? sc3200 processor data book core logic module revision 5.1 in fast path write, the core logic module responds to writes to the following addresses: 388h, 38ah, 38bh, 2x0h, 2x2h, and 2x8h. table 6-38 on page 280 shows the bit formats of the sec- ond level smi status reporting registers and the fast path read/write programming bits. figure 6-14. audio smi tree example smi# asserted smm software reads smi header if bit x = 0 (internal smi) if bit x = 1 (external smi) call internal smi handler to take appropriate action gx1 core logic module f1bar0+memory read to clear to determine top-level source of smi f3bar0+memory offset 10h read to clear smi de-asserted after al l smi sources are cleared bit 7 abm5_smi bits [15:2] bit 0 bit 1 audio_smi offset 02h module to determine second-level source of smi bits [15:8] bit 6 abm4_smi bit 5 abm3_smi bit 4 abm2_smi bit 3 abm1_smi bit 2 abm0_smi bit 1 ser_intr_smi bit 0 i/o_trap_smi f3bar0+memory offset 14h read to clear to determine third-level source of smi bit 13 smi_sc/fm_trap bits [31:14] bit 12 smi_dma_trap bit 11 smi_mpu_trap bit 10 smi_sc/fm_trap bits [9:0] (i.e., top, second, and third levels) take appropriate action take appropriate action other_smi other_smi rsvd other_ro other_ro top level second level third level if bit 1 = 1, source of smi is if bit 0 = 1, source of smi is i/o trap audio event
amd geode? sc3200 processor data book 189 core logic module revision 5.1 6.2.12.4 irq configuration registers the core logic module provides the ability to set and clear irqs internally through software control. if the irqs are configured for software control, they do not respond to external hardware. there are two registers provided for this feature: internal irq enable register (f3bar0+memory offset 1ah) internal irq control register (f3bar0+memory offset 1ch) internal irq enable register the internal irq enable register configures the irqs as internal (software) interrupts or external (hardware) inter- rupts. any irq used as an internal software driven source must be configured as internal. internal irq control register the internal irq control register allows individual software assertion/de-assertion of the irqs that are enabled as internal. these bits are used as masks when attempting to write a particular irq bit. if the mask bit is set, it can then be asserted/de-asserted according to the value in the low- order 16 bits. otherwise the assertion/de-assertion values of the particular irq can not be changed. 6.2.12.5 lpc interface the lpc interface of the core logic module is based on the intel? low pin count (lpc) interface specification, revision 1.0. in addition to the requirement pins that are specified in the intel lpc interface specification, the core logic module also supports three optional pins: ldrq#, serirq, and lpcpd#. the following subsections briefly describe some sections of the specification. however, for full details refer to the lpc specification directly. the goals of the lpc interface are to: enable a system without an isa bus. reduce the cost of traditional isa bus devices. use on a motherboard only. perform the same cycle types as the isa bus: memory, i/ o, dma, and bus master. increase the memory space from 16 mb to 4 gb to allow bios sizes much greater. provide synchronous design. much of the challenge of an isa design is meeting the different, and in some cases conflicting, isa timi ngs. make the timings synchronous to a reference well known to component designers, such as pci. support software transparency: do not require special drivers or configuration for this interface. the mother- board bios should be able to configure all devices at boot. support desktop and mobile implementations. enable support of a variable number of wait states. enable i/o memory cycle retries in smm handler. enable support of wakeup and other power state transi- tions. assumptions and functionalit y requirements of the lpc interface are: only the following class of devices may be connected to the lpc interface: ? superi/o (fdc, sp, pp, ir, kbc) - i/o slave, dma, bus master (for ir, pp). ? audio, including ac97 style design - i/o slave, dma, bus master. ? generic memory, including bios - memory slave. ? system management controller - i/o slave, bus master. interrupts are communicated with the serial interrupt (serirq) protocol. the lpc interface does not need to support high-speed buses (such as cardbus, 1394, etc.) downstream, nor does it need to support low-latency buses such as usb. figure 6-15 shows a typical setup. in this setup, the lpc is connected through the core logic module to a pci or host bus. figure 6-15. typical setup pci/host bus isa (optional) lpc kbc sp pp fdc core logic superi/o module module
190 amd geode? sc3200 processor data book core logic module revision 5.1 6.2.12.6 lpc interface signal definitions the lpc specification lists seven required and six optional signals for supporting the lpc interface. many of the sig- nals are the same signals found on the pci interface and do not require any new pins on the host. required signals must be implemented by both hosts and peripherals. optional signals may or may not be present on particular hosts or peripherals. the core logic module incorporates all the required lpc interface signals and two of the optional signals: required lpc signals: ? lad[3:0] - multiplexed command, address and data. ? lframe# - frame: indicates start of a new cycle, termination of broken cycle. ? lreset# - reset: this sig nal is not available. use pci reset signal pcirst# instead. ? lclk - clock: this signal is not available. use pci 33 mhz clock signal pciclk instead. core logic module optional lpc signals: ? ldrq# - encoded dma/bus master request: only needed by peripheral that need dma or bus mastering. peripherals may not share the ldrq# signal. ? serirq - serialized irq: only needed by periph- erals that need interrupt support. ? lpcpd# - power down: indicates that the peripheral should prepare for power to the lpc interface to be shut down. optional for the host. 6.2.12.7 cycle types table 6-12 shows the various ty pes of cycles that are sup- ported by the core logic module. 6.2.12.8 lpc inte rface support the lpc interface supports all the features described in the lpc bus interface specific ation, revision 1.0, with the following exceptions: only 8- or 16-bit dma, depending on channel number. does not support the optional larger transfer sizes. only one external drq pin. table 6-12. cycle types cycle type supported sizes (bytes) memory read 1 memory write 1 i/o read 1 i/o write 1 dma read 1 or 2 dma write 1 or 2 bus master memory read 1, 2, or 4 bus master memory write 1, 2, or 4
amd geode? sc3200 processor data book 191 core logic module - pci configuration space and access methods revision 5.1 6.3 register descriptions the core logic module is a multi-function module. its reg- ister space can be broadly divided into three categories in which specific types of registers are located: 1) chipset register space (f0-f5) (note that f4 is for video processor support, see section 7.3.1 on page 345 for register descriptions): comprised of six sepa- rate functions, each with it s own register space, con- sisting of pci header registers and configuration registers. the pci header is a 256-byte region used for configur- ing a pci device or function. the first 64 bytes are the same for all pci devices and are predefined by the pci specification. these registers are used to config- ure the pci for the device. the rest of the 256-byte region is used to configure the device or function itself. 2) usb controller register space (pciusb): consists of the standard pci header registers. the usb controller supports three ports and is openhci compliant. 3) isa legacy register space (i/o ports): contains all the legacy compatibility i/o ports that are internal, trapped, shadowed, or snooped. the following subsections provide: a brief discussion on how to access the registers located in pci configuration space. core logic module register summaries. bit formats for core logic module registers. 6.3.1 pci configuration space and access methods configuration cycles are generat ed in the processor. all configuration registers in the core logic module are accessed through the pci interface using the pci type one configuration mechanism. this mechanism uses two dword i/o locations at 0cf8h and 0cfch. the first loca- tion (0cf8h) references the c onfiguration address register. the second location (0cfch) references the configuration data register (cdr). to access pci configuration space, write the configuration address (0cf8h) register with data that specifies the core logic module as the device on pci being accessed, along with the configuration register offset. on the following cycle, a read or write to the configuration data register (cdr) causes a pci configuration cycle to the core logic module. byte, word, or dword accesses are allowed to cdr at 0cfch, 0cfdh, 0cfeh, or 0cffh. the core logic module has seven pci configuration regis- ter sets, one for each function (f0-f5) and usb (pciusb). base address registers (bar x) in f0-f5 and pciusb set the base addresses for additional i/o or memory mapped configuration registers for each function. table 6-13 shows the pci configuration address register (0cf8h) and how to access the pci header registers. table 6-13. pci configuration address register (0cf8h) 31 30 24 23 16 15 11 10 8 7 2 1 0 configuration space mapping reserved bus number device number function index dword 00 1 (enable) 000 000 0000 0000 xxxx x (note) xxx xxxx xx 00 (always) function 0 (f0): bridge configuration, gpio and lpc configuration register space 80h 0000 0000 1001 0 or 1000 0 000 index function 1 (f1): smi status and acpi timer configuration register space 80h 0000 0000 1001 0 or 1000 0 001 index function 2 (f2): ide controller configuration register space 80h 0000 0000 1001 0 or 1000 0 010 index function 3 (f3): audio configuration register space 80h 0000 0000 1001 0 or 1000 0 011 index function 4 (f4): video processor configuration register space 80h 0000 0000 1001 0 or 1000 0 100 index function 5 (f5): x-bus expansion configuration register space 80h 0000 0000 1001 0 or 1000 0 101 index pciusb: usb controller configuration register space 80h 0000 0000 1001 1 or 1000 1 000 index note: the device number depends upon the idsel strap override bit (f5 bar0+i/o offset 04h[0]). this bit allows selection of the address lines to be used as the idsel. by default: idsel = ad28 (1001 0) for f0-f5, ad29 (1001 1) for pciusb.
192 amd geode? sc3200 processor data book core logic module - register summary revision 5.1 6.3.2 register summary the tables in this subsection summarize the registers of the core logic module. included in the tables are the regis- ter?s reset values and page references where the bit for- mats are found. note: function 4 (f4) is for video processor support (although accessed through the core logic pci configuration registers). refer to section 7.3.1 "register summary" on page 345 for details. table 6-14. f0: pci header/bridge configuration registers for gpio and lpc support summary f0 index width (bits) type name reset value reference (table 6-29) 00h-01h 16 ro vendor identification register 100bh page 206 02h-03h 16 ro device identification register 0500h page 206 04h-05h 16 r/w pci command register 000fh page 206 06h-07h 16 r/w pci status register 0280h page 207 08h 8 ro device revision id register 00h page 208 09h-0bh 24 ro pci class code register 060100h page 208 0ch 8 r/w pci cache line size register 00h page 208 0dh 8 r/w pci latency timer register 00h page 208 0eh 8 ro pci header type register 80h page 208 0fh 8 ro pci bist register 00h page 208 10h-13h 32 r/w base address register 0 (f0bar0) ? sets the base address for the i/o mapped gpio runtime and configuration registers (sum- marized in table 6-15). 00000001h page 208 14h-17h 32 r/w base address register 1 (f0bar1) ? sets the base address for the i/o mapped lpc configuratio n registers (summarized in table 6-16) 00000001h page 208 18h-2bh --- --- reserved 00h page 208 2ch-2dh 16 ro subsystem vendor id 100bh page 208 2eh-2fh 16 ro subsystem id 0500h page 208 30h-3fh --- --- reserved 00h page 208 40h 8 r/w pci function control register 1 39h page 209 41h 8 r/w pci function control register 2 00h page 209 42h --- --- reserved 00h page 210 43h 8 r/w pit delayed transactions register 02h page 210 44h 8 r/w reset control register 01h page 210 45h --- --- reserved 00h page 211 46h 8 r/w pci functions enable register feh page 211 47h 8 r/w miscellaneous enable register 00h page 211 48h-4bh --- --- reserved 00h page 211 4ch-4fh 32 r/w top of system memory ffffffffh page 212 50h 8 r/w pit control/isa clk divider 7bh page 212 51h 8 r/w isa i/o recovery control register 40h page 212 52h 8 r/w rom/at logic control register 98h page 213 53h 8 r/w alternate cpu support register 00h page 213 54h-59h --- --- reserved 00h page 214 5ah 8 r/w decode control register 1 01h page 214 5bh 8 r/w decode control register 2 20h page 214 5ch 8 r/w pci interrupt steering register 1 00h page 215 5dh 8 r/w pci interrupt steering register 2 00h page 215 5eh-5fh --- --- reserved 00h page 215 60h-63h 32 r/w acpi control register 00000000h page 216 64h-6bh --- --- reserved 00h page 216
amd geode? sc3200 processor data book 193 core logic module - register summary revision 5.1 6ch-6fh 32 r/w rom mask register 0000fff0h page 216 70h-71h 16 r/w iocs1# base address register 0000h page 217 72h 8 r/w iocs1# control register 00h page 217 73h 8 --- reserved 00h page 217 74h-75h 16 r/w iocs0 base address register 0000h page 217 76h 8 r/w iocs0 control register 00h page 217 77h --- --- reserved 00h page 217 78h-7bh 32 r/w doccs base address register 00000000h page 218 7ch-7fh 32 r/w doccs control register 00000000h page 218 80h 8 r/w power management enable register 1 00h page 218 81h 8 r/w power management enable register 2 00h page 219 82h 8 r/w power management enable register 3 00h page 221 83h 8 r/w power management enable register 4 00h page 222 84h 8 ro second level pme/smi status mirror register 1 00h page 223 85h 8 ro second level pme/smi status mirror register 2 00h page 224 86h 8 ro second level pme/smi status mirror register 3 00h page 225 87h 8 ro second level pme/smi status mirror register 4 00h page 226 88h 8 r/w general purpose timer 1 count register 00h page 226 89h 8 r/w general purpose timer 1 control register 00h page 227 8ah 8 r/w general purpose timer 2 count register 00h page 228 8bh 8 r/w general purpose timer 2 control register 00h page 228 8ch 8 r/w irq speedup timer count register 00h page 228 8dh 8 r/w video speedup timer count register 00h page 228 8eh 8 r/w vga timer count register 00h page 229 8fh-92h --- --- reserved 00h page 229 93h 8 r/w miscellaneous device control register 00h page 229 94h-95h 16 r/w suspend modulation register 0000h page 229 96h 8 r/w suspend configuration register 00h page 230 97h --- --- reserved 00h page 230 98h-99h 16 r/w hard disk idle timer count register ? primary channel 0000h page 230 9ah-9bh 16 r/w floppy disk idle timer count register 0000h page 230 9ch-9dh 16 r/w parallel / serial idle timer count register 0000h page 230 9eh-9fh 16 r/w keyboard / mouse idle timer count register 0000h page 231 a0h-a1h 16 r/w user defined device 1 id le timer count register 0000h page 231 a2h-a3h 16 r/w user defined device 2 id le timer count register 0000h page 231 a4h-a5h 16 r/w user defined device 3 id le timer count register 0000h page 231 a6h-a7h 16 r/w video idle timer count register 0000h page 231 a8h-a9h 16 r/w video overflow count register 0000h page 231 aah-abh --- --- reserved 00h page 231 ach-adh 16 r/w hard disk idle timer count register ? secondary channel 0000h page 232 aeh 8 wo cpu suspend command register 00h page 232 afh 8 wo suspend notebook command register 00h page 232 b0h-b3h --- --- reserved 00h page 232 b4h 8 ro floppy port 3f2h shadow register xxh page 232 b5h 8 ro floppy port 3f7h shadow register xxh page 232 b6h 8 ro floppy port 1f2h shadow register xxh page 232 b7h 8 ro floppy port 1f7h shadow register xxh page 232 table 6-14. f0: pci header/bridge configuration registers for gpio and lpc support summary (continued) f0 index width (bits) type name reset value reference (table 6-29)
194 amd geode? sc3200 processor data book core logic module - register summary revision 5.1 b8h 8 ro dma shadow register xxh page 233 b9h 8 ro pic shadow register xxh page 233 bah 8 ro pit shadow register xxh page 233 bbh 8 ro rtc index shadow register xxh page 234 bch 8 r/w clock stop control register 00h page 234 bdh-bfh --- --- reserved 00h page 234 c0h-c3h 32 r/w user defined device 1 base address register 00000000h page 234 c4h-c7h 32 r/w user defined device 2 base address register 00000000h page 234 c8h-cbh 32 r/w user defined device 3 base address register 00000000h page 234 cch 8 r/w user defined device 1 control register 00h page 235 cdh 8 r/w user defined device 2 control register 00h page 235 ceh 8 r/w user defined device 3 control register 00h page 235 cfh --- --- reserved 00h page 235 d0h 8 wo software smi register 00h page 235 d1h-ebh 16 --- reserved 00h page 235 ech 8 r/w timer test register 00h page 236 edh-f3h --- --- reserved 00h page 236 f4h 8 rc second level pme/smi status register 1 00h page 236 f5h 8 rc second level pme/smi status register 2 00h page 236 f6h 8 rc second level pme/smi status register 3 00h page 237 f7h 8 rc second level pme/smi status register 4 00h page 238 f8h-ffh --- --- reserved 00h page 239 table 6-14. f0: pci header/bridge configuration registers for gpio and lpc support summary (continued) f0 index width (bits) type name reset value reference (table 6-29)
amd geode? sc3200 processor data book 195 core logic module - register summary revision 5.1 table 6-15. f0bar0: gpio support registers summary f0bar0+ i/o offset width (bits) type name reset value reference (table 6-30) 00h-03h 32 r/w gpdo0 ? gpio data out 0 register ffffffffh page 240 04h-07h 32 ro gpdi0 ? gpio data in 0 register ffffffffh page 240 08h-0bh 32 r/w gpien0 ? gpio interrupt enable 0 register 00000000h page 240 0ch-0fh 32 r/w1c gpst0 ? gpio status 0 register 00000000h page 240 10h-13h 32 r/w gpdo1 ? gpio data out 1 register ffffffffh page 241 14h-17h 32 ro gpdi1 ? gpio data in 1 register ffffffffh page 241 18h-1bh 32 r/w gpien1 ? gpio interrupt enable 1 register 00000000h page 241 1ch-1fh 32 r/w1c gpst1 ? gpio status 1 register 00000000h page 241 20h-23h 32 r/w gpio signal configuration select register 00000000h page 241 24h-27h 32 r/w gpio signal configuration access register 00000044h page 242 28h-2bh 32 r/w gpio reset control register 00000000h page 243 table 6-16. f0bar1: lpc support registers summary f0bar1+ i/o offset width (bits) type name reset value reference (table 6-31) 00h-03h 32 r/w serirq_src ? serial irq source register 00000000h page 244 04h-07h 32 r/w serirq_lvl ? serial irq level control register 00000000h page 245 08h-0bh 32 r/w serirq_cnt ? serial irq control register 00000000h page 247 0ch-0fh 32 r/w drq_src ? drq source register 00000000h page 247 10h-13h 32 r/w lad_en ? lpc address enable register 00000000h page 248 14h-17h 32 r/w lad_d0 ? lpc address decode 0 register 00080020h page 249 18h-1bh 32 r/w lad_d1 ? lpc address decode 1 register 00000000h page 250 1ch-1fh 32 r/w lpc_err_smi ? lpc error smi register 00000080h page 250 20h-23h 32 ro lpc_err_add ? lpc error address register 00000000h page 251
196 amd geode? sc3200 processor data book core logic module - register summary revision 5.1 table 6-17. f1: pci header registers for smi status and acpi support summary f1 index width (bits) type name reset value reference (table 6-32) 00h-01h 16 ro vendor identification register 100bh page 252 02h-03h 16 ro device identification register 0501h page 252 04h-05h 16 r/w pci command register 0000h page 252 06h-07h 16 ro pci status register 0280h page 252 08h 8 ro device revision id register 00h page 252 09h-0bh 24 ro pci class code register 068000h page 252 0ch 8 ro pci cache line size register 00h page 252 0dh 8 ro pci latency timer register 00h page 252 0eh 8 ro pci header type register 00h page 252 0fh 8 ro pci bist register 00h page 252 10h-13h 32 r/w base address register 0 (f1bar0) ? sets the base address for the i/o mapped smi status registers (summarized in table 6-18). 00000001h page 252 14h-2bh --- --- reserved 00h page 252 2ch-2dh 16 ro subsystem vendor id 100bh page 252 2eh-2fh 16 ro subsystem id 0501h page 252 30h-3fh --- --- reserved 00h page 252 40h-43h 32 r/w base address register 1 (f1bar1) ? sets the base address for the i/o mapped acpi support registers (summarized in table 6- 19) 00000001h page 252 44h-ffh --- --- reserved 00h page 252 table 6-18. f1bar0: smi status registers summary f1bar0+ i/o offset width (bits) type name reset value reference (table 6-33) 00h-01h 16 ro top level pme/smi status mirror register 0000h page 253 02h-03h 16 ro/rc top level pme/smi status register 0000h page 254 04h-05h 16 ro second level general traps & timers pme/smi status mirror register 0000h page 256 06h-07h 16 rc second level general traps & timers pme/smi status register 0000h page 257 08h-09h 16 read to enable smi speedup disable register 0000h page 258 0ah-1bh --- --- reserved 00h page 258 1ch-1fh 32 ro acpi timer register xxxxxxxxh page 258 20h-21h 16 ro second level acpi pme/smi status mirror register 0000h page 258 22h-23h 16 rc second level acpi pme/smi status register 0000h page 259 24h-27h 32 r/w external smi register 00000000h page 259 28h-4fh --- --- not used 00h page 262 50h-ffh --- --- the i/o mapped registers located here (f1bar 0+i/o offset 50h-ffh) are also accessible at f0 index 50h-ffh. the preferred method is to program these registers through the f0 register space.
amd geode? sc3200 processor data book 197 core logic module - register summary revision 5.1 table 6-19. f1bar1: acpi support registers summary f1bar1+ i/o offset width (bits) type name reset value reference (table 6-34) 00h-03h 32 r/w p_cnt ? processor control register 00000000h page 263 04h 8 ro reserved, do not read 00h page 263 05h 8 ro p_lvl3 ? enter c3 power state register xxh page 263 06h 8 r/w smi_cmd ? os/bios requests register 00h page 263 07h 8 r/w acpi_fun_cnt ? acpi function control register 00h page 263 08h-09h 16 r/w pm1a_sts ? pm1a status register 0000h page 264 0ah-0bh 16 r/w pm1a_en ? pm1a enable register 0000h page 265 0ch-0dh 16 r/w pm1a_cnt ? pm1a control register 0000h page 265 0eh 8 r/w acpi_bios_sts register 00h page 266 0fh 8 r/w acpi_bios_en register 00h page 267 10h-11h 16 r/w gpe0_sts ? general purpose event 0 status register xxxxh page 267 12h-13h 16 r/w gpe0_en ? general purpose event 0 enable register 0000h page 269 14h 8 r/w gpwio control register 1 00h page 270 15h 8 r/w gpwio control register 2 00h page 270 16h 8 r/w gpwio data register 00h page 271 17h --- --- reserved 00h page 271 18h-1bh 32 r/w acpi sci_routing register 00000f00h page 271 1ch-1fh 32 ro pm_tmr ? pm timer register xxxxxxxxh page 272 20h 8 r/w pm2_cnt ? pm2 control register 00h page 272 21h-ffh --- --- not used 00h page 272
198 amd geode? sc3200 processor data book core logic module - register summary revision 5.1 table 6-20. f2: pci header registers for ide controller support summary f2 index width (bits) type name reset value reference (table 6-35) 00h-01h 16 ro vendor identification register 100bh page 273 02h-03h 16 ro device identification register 0502h page 273 04h-05h 16 r/w pci command register 0000h page 273 06h-07h 16 ro pci status register 0280h page 273 08h 8 ro device revision id register 01h page 273 09h-0bh 24 ro pci class code register 010180h page 273 0ch 8 ro pci cache line size register 00h page 273 0dh 8 ro pci latency timer register 00h page 273 0eh 8 ro pci header type register 00h page 273 0fh 8 ro pci bist register 00h page 273 10h-13h 32 ro base address register 0 (f2bar0) ? reserved for possible future use by the core logic module. 00000000h page 273 14h-17h 32 ro base address register 1 (f2bar1) ? reserved for possible future use by the core logic module. 00000000h page 273 18h-1bh 32 ro base address register 2 (f2bar2) ? reserved for possible future use by the core logic module. 00000000h page 273 1ch-1fh 32 ro base address register 3 (f2bar3) ? reserved for possible future use by the core logic module. 00000000h page 273 20h-23h 32 r/w base address register 4 (f2bar4) ? sets the base address for the i/o mapped bus master ide registers (summarized in table 6-21) 00000001h page 273 24h-2bh --- --- reserved 00h page 273 2ch-2dh 16 ro subsystem vendor id 100bh page 273 2eh-2fh 16 ro subsystem id 0502h page 273 30h-3fh --- --- reserved 00h page 274 40h-43h 32 r/w channel 0 drive 0 pio register 00009172h page 274 44h-47h 32 r/w channel 0 drive 0 dma control register 00077771h page 275 48h-4bh 32 r/w channel 0 drive 1 pio register 00009172h page 275 4ch-4fh 32 r/w channel 0 drive 1 dma control register 00077771h page 275 50h-53h 32 r/w channel 1 drive 0 pio register 00009172h page 276 54h-57h 32 r/w channel 1 drive 0 dma control register 00077771h page 276 58h-5bh 32 r/w channel 1 drive 1 pio register 00009172h page 276 5ch-5fh 32 r/w channel 1 drive 1 dma control register 00077771h page 276 60h-ffh --- --- reserved 00h page 276
amd geode? sc3200 processor data book 199 core logic module - register summary revision 5.1 table 6-21. f2bar4: ide controller support registers summary f2bar4+ i/o offset width (bits) type name reset value reference (table 6-36) 00h 8 r/w ide bus master 0 command register ? primary 00h page 277 01h --- --- not used --- page 277 02h 8 r/w ide bus master 0 status register ? primary 00h page 277 03h --- --- not used --- page 277 04h-07h 32 r/w ide bus master 0 prd table address ? primary 00000000h page 277 08h 8 r/w ide bus master 1 command register ? secondary 00h page 278 09h --- --- not used --- page 278 0ah 8 r/w ide bus master 1 status register ? secondary 00h page 278 0bh --- --- not used --- page 278 0ch-0fh 32 r/w ide bus master 1 prd table address ? secondary 00000000h page 278 table 6-22. f3: pci header registers for audio support summary f3 index width (bits) type name reset value reference (table 6-37) 00h-01h 16 ro vendor identification register 100bh page 279 02h-03h 16 ro device identification register 0503h page 279 04h-05h 16 r/w pci command register 0000h page 279 06h-07h 16 ro pci status register 0280h page 279 08h 8 ro device revision id register 00h page 279 09h-0bh 24 ro pci class code register 040100h page 279 0ch 8 ro pci cache line size register 00h page 279 0dh 8 ro pci latency timer register 00h page 279 0eh 8 ro pci header type register 00h page 279 0fh 8 ro pci bist register 00h page 279 10h-13h 32 r/w base address register 0 (f3bar0) ? sets the base address for the memory mapped vsa audio interface control register block (summarized in table 6-23). 00000000h page 279 14h-2bh --- --- reserved 00h page 279 2ch-2dh 16 ro subsystem vendor id 100bh page 279 2eh-2fh 16 ro subsystem id 0503h page 279 30h-ffh --- --- reserved 00h page 279
200 amd geode? sc3200 processor data book core logic module - register summary revision 5.1 table 6-23. f3bar0: audio support registers summary f3bar0+ memory offset width (bits) type name reset value reference (table 6-38) 00h-03h 32 r/w codec gpio status register 00000000h page 280 04h-07h 32 r/w codec gpio control register 00000000h page 280 08h-0bh 32 r/w codec status register 00000000h page 280 0ch-0fh 32 r/w codec command register 00000000h page 281 10h-11h 16 rc second level audio smi status register 0000h page 281 12h-13h 16 ro second level audio smi st atus mirror register 0000h page 282 14h-17h 32 ro i/o trap smi and fast write status register 00000000h page 283 18h-19h 16 r/w i/o trap smi enable register 0000h page 284 1ah-1bh 16 r/w internal irq enable register 0000h page 285 1ch-1fh 32 r/w internal irq control register 00000000h page 286 20h 8 r/w audio bus master 0 command register 00h page 288 21h 8 rc audio bus master 0 smi status register 00h page 288 22h-23h ---- --- not used --- page 288 24h-27h 32 r/w audio bus master 0 prd table address 00000000h page 288 28h 8 r/w audio bus master 1 command register 00h page 289 29h 8 rc audio bus master 1 smi status register 00h page 289 2ah-2bh --- --- not used --- page 289 2ch-2fh 32 r/w audio bus master 1 prd table address 00000000h page 289 30h 8 r/w audio bus master 2 command register 00h page 290 31h 8 rc audio bus master 2 smi status register 00h page 290 32h-33h --- --- not used 00h page 290 34h-37h 32 r/w audio bus master 2 prd table address 00000000h page 290 38h 8 r/w audio bus master 3 command register 00h page 291 39h 8 rc audio bus master 3 smi status register 00h page 291 3ah-3bh --- --- not used --- page 291 3ch-3fh 32 r/w audio bus master 3 prd table address 00000000h page 291 40h 8 r/w audio bus master 4 command register 00h page 292 41h 8 rc audio bus master 4 smi status register 00h page 292 42h-43h --- --- not used --- page 292 44h-47h 32 r/w audio bus master 4 prd table address 00000000h page 292 48h 8 r/w audio bus master 5 command register 00h page 293 49h 8 rc audio bus master 5 smi status register 00h page 293 4ah-4bh --- --- not used --- page 293 4ch-4fh 32 r/w audio bus master 5 prd table address 00000000h page 293
amd geode? sc3200 processor data book 201 core logic module - register summary revision 5.1 table 6-24. f5: pci header registers for x-bus expansion support summary f5 index width (bits) type name reset value reference (table 6-39) 00h-01h 16 ro vendor identification register 100bh page 294 02h-03h 16 ro device identification register 0505h page 294 04h-05h 16 r/w pci command register 0000h page 294 06h-07h 16 ro pci status register 0280h page 294 08h 8 ro device revision id register 00h page 294 09h-0bh 24 ro pci class code register 068000h page 294 0ch 8 ro pci cache line size register 00h page 294 0dh 8 ro pci latency timer register 00h page 294 0eh 8 ro pci header type register 00h page 294 0fh 8 ro pci bist register 00h page 294 10h-13h 32 r/w base address register 0 (f5bar0) ? sets the base address for the x-bus expansion support registers (summarized in table 6-25.) 00000000h page 294 14h-17h 32 r/w base address register 1 (f5bar1) ? reserved for possible future use by the core logic module. 00000000h page 294 18h-1bh 32 r/w base address register 2 (f5bar2) ? reserved for possible future use by the core logic module. 00000000h page 294 1ch-1fh 32 r/w base address register 3 (f5bar3) ? reserved for possible future use by the core logic module. 00000000h page 295 20h-23h 32 r/w base address register 4 (f5bar4) ? reserved for possible future use by the core logic module. 00000000h page 295 24h-27h 32 r/w base address register 5 (f5bar5) ? reserved for possible future use by the core logic module. 00000000h page 295 28h-2bh --- --- reserved 00h page 295 2ch-2dh 16 ro subsystem vendor id 100bh page 295 2eh-2fh 16 ro subsystem id 0505h page 295 30h-3fh --- --- reserved 00h page 295 40h-43h 32 r/w f5bar0 base address register mask ffffffc1h page 295 44h-47h 32 r/w f5bar1 base address register mask 00000000h page 296 48h-4bh 32 r/w f5bar2 base address register mask 00000000h page 296 4ch-4fh 32 r/w f5bar3 base address register mask 00000000h page 296 50h-53h 32 r/w f5bar4 base address register mask 00000000h page 296 54h-57h 32 r/w f5bar5 base address register mask 00000000h page 296 58h 8 r/w f5barx initialized register 00h page 296 59h-ffh --- --- reserved xxh page 296 60h-63h 32 r/w scratchpad for chip number 00000000h page 296 64h-67h 32 r/w scratchpad for configuration block address 00000000h page 297 68h-ffh --- --- reserved 00h page 297 table 6-25. f5bar0: i/o control support registers summary f5bar0+ i/o offset width (bits) type name reset value reference (table 6-40) 00h-03h 32 r/w i/o control register 1 010c0007h page 298 04h-07h 32 r/w i/o control register 2 00000002h page 299 08h-0bh 32 r/w i/o control register 3 00009000h page 299
202 amd geode? sc3200 processor data book core logic module - register summary revision 5.1 table 6-26. pciusb: usb pci configuration register summary pciusb index width (bits) type name reset value reference (table 6-41) 00h-01h 16 ro vendor identification 0e11h page 300 02h-03h 16 ro device identification a0f8h page 300 04h-05h 16 r/w command register 00h page 300 06h-07h 16 r/w status register 0280h page 301 08h 8 ro device revision id 08h page 301 09h-0bh 24 ro class code 0c0310h page 301 0ch 8 r/w cache line size 00h page 301 0dh 8 r/w latency timer 00h page 301 0eh 8 ro header type 00h page 301 0fh 8 ro bist register 00h page 301 10h-13h 32 r/w base address 0 00000000h page 301 14h-2bh --- --- reserved 00h page 302 2ch-2dh 16 ro subsystem vendor id 0e11h page 302 2eh-2fh 16 ro subsystem id a0f8h page 302 30h-3bh --- --- reserved 00h page 302 3ch 8 r/w interrupt line register 00h page 302 3dh 8 r/w interrupt pin register 01h page 302 3eh 8 ro min. grant register 00h page 302 3fh 8 ro max. latency register 50h page 302 40h-43h 32 r/w asic test mode enable register 000f0000h page 302 44h 8 r/w asic operational mode enable 00h page 302 45h-ffh --- --- reserved 00h page 302
amd geode? sc3200 processor data book 203 core logic module - register summary revision 5.1 table 6-27. usb_bar: usb controller registers summary usb_bar0 +memory offset width (bits) type name reset value reference (table 6-42) 00h-03h 32 r/w hcrevision 00000110h page 303 04h-07h 32 r/w hccontrol 00000000h page 303 08h-0bh 32 r/w hccommandstatus 00000000h page 303 0ch-0fh 32 r/w hcinterruptstatus 00000000h page 303 10h-13h 32 r/w hcinterruptenable 00000000h page 304 14h-17h 32 r/w hcinterruptdisable 00000000h page 304 18h-1bh 32 r/w hchcca 00000000h page 305 1ch-1fh 32 r/w hcperiodcurrented 00000000h page 305 20h-23h 32 r/w hccontrolheaded 00000000h page 305 24h-27h 32 r/w hccontrolcurrented 00000000h page 305 28h-2bh 32 r/w hcbulkheaded 00000000h page 305 2ch-2fh 32 r/w hcbulkcurrented 00000000h page 305 30h-33h 32 r/w hcdonehead 00000000h page 305 34h-37h 32 r/w hcfminterval 00002edfh page 306 38h-3bh 32 ro hcframeremaining 00000000h page 306 3ch-3fh 32 ro hcfmnumber 00000000h page 306 40h-43h 32 r/w hcperiodicstart 00000000h page 306 44h-47h 32 r/w hclsthreshold 00000628h page 306 48h-4bh 32 r/w hcrhdescriptora 01000003h page 306 4ch-4fh 32 r/w hcrhdescriptorb 00000000h page 307 50h-53h 32 r/w hcrhstatus 00000000h page 307 54h-57h 32 r/w hcrhportstatus[1] 00000000h page 308 58h-5bh 32 r/w hcrhportstatus[2] 00000000h page 309 5ch-5fh 32 r/w hcrhportstatus[3] 00000000h page 310 60h-9fh --- --- reserved xxxxxxxxh page 311 100h-103h 32 r/w hcecontrol 00000000h page 311 104h-107h 32 r/w hceinput 000000xxh page 312 108h-10dh 32 r/w hceoutput 000000xxh page 312 10ch-10fh 32 r/w hcestatus 00000000h page 312
204 amd geode? sc3200 processor data book core logic module - register summary revision 5.1 table 6-28. isa legacy i/o register summary i/o port type name reference dma channel control registers (table 6-43) 000h r/w dma channel 0 address register page 313 001h r/w dma channel 0 transfer count register page 313 002h r/w dma channel 1 address register page 313 003h r/w dma channel 1 transfer count register page 313 004h r/w dma channel 2 address register page 313 005h r/w dma channel 2 transfer count register page 313 006h r/w dma channel 3 address register page 313 007h r/w dma channel 3 transfer count register page 313 008h read dma status register, channels 3:0 page 313 write dma command register, channels 3:0 page 314 009h wo software dma request register, channels 3:0 page 314 00ah w dma channel mask register, channels 3:0 page 314 00bh wo dma channel mode register, channels 3:0 page 315 00ch wo dma clear byte pointer command, channels 3:0 page 315 00dh wo dma master clear command, channels 3:0 page 315 00eh wo dma clear mask register command, channels 3:0 page 315 00fh wo dma write mask register command, channels 3:0 page 315 0c0h r/w dma channel 4 address register (not used) page 315 0c2h r/w dma channel 4 transfer count register (not used) page 315 0c4h r/w dma channel 5 address register page 315 0c6h r/w dma channel 5 transfer count register page 315 0c8h r/w dma channel 6 address register page 315 0cah r/w dma channel 6 transfer count register page 315 0cch r/w dma channel 7 address register page 315 0ceh r/w dma channel 7 transfer count register page 315 0d0h read dma status register, channels 7:4 page 316 write dma command register, channels 7:4 page 316 0d2h wo software dma request register, channels 7:4 page 317 0d4h w dma channel mask register, channels 7:4 page 317 0d6h wo dma channel mode register, channels 7:4 page 317 0d8h wo dma clear byte pointer command, channels 7:4 page 317 0dah wo dma master clear command, channels 7:4 page 317 0dch wo dma clear mask register command, channels 7:4 page 317 0deh wo dma write mask register command, channels 7:4 page 318 dma page registers (table 6-44) 081h r/w dma channel 2 low page register page 318 082h r/w dma channel 3 low page register page 318 083h r/w dma channel 1 low page register page 318 087h r/w dma channel 0 low page register page 318 089h r/w dma channel 6 low page register page 318 08ah r/w dma channel 7 low page register page 318 08bh r/w dma channel 5 low page register page 318 08fh r/w sub-isa refresh low page register page 318 481h r/w dma channel 2 high page register page 318 482h r/w dma channel 3 high page register page 318 483h r/w dma channel 1 high page register page 318
amd geode? sc3200 processor data book 205 core logic module - register summary revision 5.1 487h r/w dma channel 0 high page register page 318 489h r/w dma channel 6 high page register page 318 48ah r/w dma channel 7 high page register page 318 48bh r/w dma channel 5 high page register page 318 programmable interval timer registers (table 6-45) 040h w pit timer 0 counter page 319 r pit timer 0 status page 319 041h w pit timer 1 counter (refresh) page 319 r pit timer 1 status (refresh) page 319 042h w pit timer 2 counter (speaker) page 320 r pit timer 2 status (speaker) page 320 043h r/w pit mode control word register page 320 read status command counter latch command programmable interrupt controller registers (table 6-46) 020h / 0a0h wo master / slave pci icw1 page 321 021h / 0a1h wo master / slave pic icw2 page 321 021h / 0a1h wo master / slave pic icw3 page 321 021h / 0a1h wo master / slave pic icw4 page 321 021h / 0a1h r/w master / slave pic ocw1 page 321 020h / 0a0h wo master / slave pic ocw2 page 322 020h / 0a0h wo master / slave pic ocw3 page 322 020h / 0a0h ro master / slave pic interrupt request and service registers for ocw3 commands page 322 keyboard controller registers (table 6-47) 060h r/w external keyboard controller data register page 324 061h r/w port b control register page 324 062h r/w external keyboard controller mailbox register page 324 064h r/w external keyboard controller command register page 324 066h r/w external keyboard controller mailbox register page 324 092h r/w port a control register page 324 real-time clock registers (table 6-48) 070h wo rtc address register page 325 071h r/w rtc data register page 325 072h wo rtc extended address register page 325 073h r/w rtc extended data register page 325 miscellaneous registers (table 6-49) 0f0h, 0f1h wo coprocessor error register page 325 170h-177h/ 376h-377h r/w secondary ide registers page 325 1f0-1f7h/ 3f6h-3f7h r/w primary ide registers page 325 4d0h r/w interrupt edge/level select register 1 page 325 4d1h r/w interrupt edge/level select register 2 page 326 table 6-28. isa legacy i/o register summary (continued) i/o port type name reference
206 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 6.4 chipset register space the chipset register space of the core logic module is comprised of six separate functions (f0-f5), each with its own register space. base address registers (bars) in each pci header register space set the base address for the configuration registers for each respective function. the configuration registers accessed through bars are i/o or memory mapped. the pci header registers in all functions are very similar. 1) function 0 (f0): pci header/bridge configuration registers for gpio, and lpc support (see section 6.4.1). 2) function 1 (f1): pci header registers for smi status and acpi support (see section 6.4.2 on page 252). 3) function 2 (f2): pci header/channel 0 and 1 configu- ration registers for ide controller support (see sec- tion 6.4.3 on page 273). 4) function 3 (f3): pci header registers for audio sup- port (see section 6.4.4 on page 279). 5) function 4 (f4): pci header registers video proces- sor support (see section 7.3 on page 345). 6) function 5 (f5): pci header registers for x-bus expansion support (see section 6.4.5 on page 294). function 5 contain six bars in their standard pci header locations (i.e., index 10h, 14h, 18h, 1ch, 20h, and 24h). in addition there are six mask registers that allow the six bars to be fully programmable from 4 gb to 16 bytes for memory and from 4 gb to 4 bytes for i/o general remarks: reserved bits that are defined as "must be set to 0 or 1" should be written with that value. reserved bits that are not defined as "must be set to 0 or 1" should be written with a value that is read from them. "read to clear" registers that are wider than one byte should be read in one read operation. if they are read a byte at a time, status bits may be lost, or not cleared. 6.4.1 bridge, gpio, and lpc registers - function 0 the register space designated as function 0 (f0) is used to configure bridge features and functionality unique to the core logic module. in addition, it configures the pci por- tion of support hardware for the gpio and lpc support registers. the bit formats for the pci header and bridge configuration registers are given in table 6-29. note: the registers at f0 index 50h-ffh can also be accessed at f1bar 0+i/o offset 50h-ffh. how- ever, the preferred method is to program these reg- isters through the f0 register space. located in the pci header registers of f0, are two base address registers (f0barx) used for pointing to the regis- ter spaces designated for gpio and lpc configuration (described in section 6.4.1.1 "gpio support registers" on page 240 and section 6.4.1.2 "lpc support registers" on page 244). table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support bit description index 00h-01h vendor identification register (ro) reset value: 100bh index 02h-03h device identification register (ro) reset value: 0500h index 04h-05h pci command regi ster (r/w) reset value: 000fh 15:10 reserved. must be set to 0. 9 fast back-to-back enable. this function is not supported when the core logic module is a master. it must always be dis- abled (i.e., must be set to 0). 8 serr#. allow serr# assertion on detection of special errors. 0: disable. (default) 1: enable. 7 wait cycle control (read only). this function is not supported in the core logic module. it is always disabled (always reads 0, hardwired). 6 parity error. allow the core logic module to check for parity errors on pci cycles for which it is a target and to assert perr# when a parity error is detected. 0: disable. (default) 1: enable. 5 vga palette snoop enable. (read only) this function is not supported in the core logic module. it is always disabled (always reads 0, hardwired).
amd geode? sc3200 processor data book 207 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 4 memory write and invalidate. allow the core logic module to do memory write and invalidate cycles, if the pci cache line register (f0 index 0ch) is set to 32 bytes (08h). 0: disable. (default) 1: enable. 3 special cycles. allow the core logic module to respond to special cycles. 0: disable. 1: enable. (default) this bit must be enabled to allow an smi to be generated from a cpu shutdown cycle. 2 bus master. allow the core logic module bus mastering capabilities. 0: disable. 1: enable. (default) this bit must be set to 1. 1 memory space. allow the core logic module to respond to memory cycles from the pci bus. 0: disable. 1: enable. (default) 0 i/o space. allow the core logic module to res pond to i/o cycles from the pci bus: 0: disable. 1: enable. (default) this bit must be set to 1 to access i/o offsets through f0bar0 and f0bar1 (see f0 index 10h and 14h). index 06h-07h pci status register (r/w) reset value: 0280h 15 detected parity error. this bit is set whenever a parity error is detected. write 1 to clear. 14 signaled system error. this bit is set whenever the core logic module asserts serr# active. write 1 to clear. 13 received master abort. this bit is set whenever a master abort cycle oc curs. a master abort occurs when a pci cycle is not claimed, except for special cycles. write 1 to clear. 12 received target abort. this bit is set whenever a target abort is receiv ed while the core logic module is the master for the pci cycle. write 1 to clear. 11 signaled target abort. this bit is set whenever the core logic m odule signals a target abort. this occurs when an address parity error occurs for an address that hits in the active address decode space of the core logic module. write 1 to clear. 10:9 devsel# timing. (read only) these bits are always 01, as the core logic module always responds to cycles for which it is an active target with medium devsel# timing. 00: fast 01: medium 10: slow 11: reserved. 8 data parity detected. this bit is set when: 1) the core logic module asserts perr# or observed perr# asserted. 2) the core logic module is the master for the cycle in whic h the perr# occurred, and pe is set (f0 index 04h[6] = 1). write 1 to clear. 7 fast back-to-back capable. (read only) enables the core logic module, as a tar get, to accept fast back-to-back trans- actions. 0: disable. 1: enable. this bit is always set to 1. 6:0 reserved. (read only) must be set to 0 for future use. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
208 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 08h device revision id register (ro) reset value: 00h index 09h-0bh pci class code register (ro) reset value: 060100h index 0ch pci cache line size register (r/w) reset value: 00h 7:0 pci cache line size register. this register sets the size of the pci cache line, in increments of four bytes. for memory write and invalidate cycles, the pci cache line size must be set to 32 bytes (08h) and the memory write and invalidate bit (f0 index 04h[4]) must be set to 1. index 0dh pci latency timer register (r/w) reset value: 00h 7:4 reserved. must be set to 0. 3:0 pci latency timer value. the pci latency timer register prevents sy stem lockup when a slave does not respond to a cycle that the core logic module masters. if the value is set to 00h (default), the timer is disabled. if the timer is written with any other value, bits [3:0] become the four most significant bits in a timer that counts pci clock s for slave response. the timer is reset on each valid data transfer. if the counter expires before the next assertion of trdy# is received, the core logic module stops the transaction with a master abort and asserts serr#, if enabled to do so (via f0 index 04h[8]). index 0eh pci header type (ro) reset value: 80h 7:0 pci header type register. this register defines the format of this header . this header has a format of type 0. (for more information about this format, see the pci local bus specification, revision 2.2.) additionally, bit 7 of this register defines whether this pci devi ce is a multifunction device (bit 7 = 1) or not (bit 7 = 0). index 0fh pci bist register (ro) reset value: 00h this register indicates various information about the pci built-in self-test (bist) mechanism. note: this mechanism is not supported in the core logic module in the sc3200. 7 bist capable. indicates if the device can run a built-in self-test (bist). 0: the device has no bist functionality. 1: the device can run a bist. 6 start bist. setting this bit to 1 starts up a bist on the device. the device resets this bit when the bist is completed. (not supported.) 5:4 reserved. 3:0 bist completion code. upon completion of the bist, the completion code is stored in these bits. a completion code of 0000 indicates that the bist was successfully comp leted. any other value indicates a bist failure. index 10h-13h base address register 0 - f0bar0 (r/w) reset value: 00000001h this register allows access to i/o mapped gpio runtime and configuration registers. bits [5:0] are read only (000001), indicati ng a 64- byte aligned i/o address space. refer to table 6-30 on page 240 for the gpio register bit formats and reset values. 31:6 gpio base address. 5:0 address range. (read only) index 14h-17h base address register 1 - f0bar1 (r/w) reset value: 00000001h this register allows access to i/o mapped lpc configuration r egisters. bits [5:0] are read only (000001), indicating a 64-byte aligned i/o address space. refer to table 6-31 on page 244 for t he bit formats and reset values of the lpc registers. 31:6 lpc base address. 5:0 address range. (read only) index 18h-2bh reserved reset value: 00h index 2ch-2dh subsystem vendor id (ro) reset value: 100bh index 2eh-2fh subsystem id (ro) reset value: 0500h index 30h-3fh reserved reset value: 00h table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 209 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 40h pci function control register 1 (r/w) reset value: 39h 7:6 reserved. must be set to 0. 5 reserved. must be set to 0. 4 pci subtractive decode. 0: disable transfer of subtractive decode address to ex ternal pci bus. external pci bus is not usable. 1: enable transfer of subtractive decode address to external pci bus. recommended setting. 3 reserved . must be set to 1. 2 reserved . must be set to 0. 1 perr# signals serr#. assert serr# when perr# is asserted or detect ed as active by the core logic module (allows perr# assertion to be cascaded to nmi (smi) generation in the system). 0: disable. 1: enable. 0 pci interrupt acknowledge cycle response. the core logic module responds to pci interrupt acknowledge cycles. 0: disable. 1: enable. index 41h pci function control register 2 (r/w) reset value: 00h 7:6 reserved. must be set to 0. 5 x-bus configuration trap. if this bit is set to 1 and an access occurs to one of the configuration registers in pci function 5 (f5) register space, an smi is generat ed. writes are trapped; access to the re gister is denied. reads are snooped; access to the register is allowed. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[5]. 4 video configuration trap. if this bit is set to 1 and an access occurs to one of the configuration registers in pci function 4 (f4) register space, an smi is generated. writes are trapped; access to the register is denied. reads are snooped; access to the register is allowed. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[5]. 3 audio configuration trap. if this bit is set to 1 and an access occurs to one of the configuration registers in pci function 3 (f3) register space, an smi is generat ed. writes are trapped; access to the re gister is denied. reads are snooped; access to the register is allowed. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[5]. 2 ide configuration trap. if this bit is set to 1 and an access occurs to on e of the configuration registers in pci function 2 (f2) register space, an smi is generated. writes are trapped; access to the register is denied. reads are snooped; access to the register is allowed. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[5]. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
210 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 1 power management configuration trap. if this bit is set to 1 and an access occurs to one of the configuration registers in pci function 1 (f1) register space, an sm i is generated. writes are trapped; access to the register is denied. reads are snooped; access to the register is allowed. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[5]. 0 legacy configuration trap. if this bit is set to 1 and an access occurs to one of the configuration registers in pci function 0 (f0), an smi is generated. reads and writes are snooped; access to the register is allowed. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[5]. index 42h reserved reset value: 00h index 43h delayed transactions register (r/w) reset value: 02h 7:6 reserved. must be set to 0. 5 reserved. must be set to 1. 4 enable pci delayed transactions for access to i/o address 170h-177h (secondary ide channel). pio mode uses repeated i/o transactions that are fast er when non-delayed tr ansactions are used. 0: i/o addresses complete as fast as possible on pci. (default) 1: accesses to secondary ide channel i/o addr esses are delayed transactions on pci. for best performance of vip, this bit shoul d be set to 1 unless pio mode 3 or 4 are used. 3 enable pci delayed transactions for access to i/o address 1f0h-1f7h (primary ide channel). pio mode uses repeated i/o transactions that are fast er when non-delayed tr ansactions are used. 0: i/o addresses complete as fast as possible on pci. (default) 1: accesses to primary ide channel i/o addr esses are delayed transactions on pci. for best performance of vip, this bit shoul d be set to 1 unless pio mode 3 or 4 are used. 2 enable pci delayed transactions for at legacy pic i/o addresses. some pic status reads are long. enabling delayed transactions help reduce dma latency for high bandwidth devices like vip. 0: pic i/o addresses complete as fast as possible on pci. (default) 1: accesses to pic i/o addresses are delayed transactions on pci. for best performance of vip, this bit should be set to 1. 1 enable pci delayed transactions for at legacy pit i/o addresses. some x86 programs (certain benchmarks/diagnos- tics) assume a particular latency for pit acce sses; this bit allows that code to work. 0: pit i/o addresses complete as fast as possible on pci. 1: accesses to pit i/o addresses ar e delayed transactions on pci. (default) for best performance (e.g., when running micr osoft windows?), this bit should be set to 0. 0 reserved. must be set to 0. index 44h reset control register (r/w) reset value: 01h 7 ac97 soft reset. active low reset for the ac97 codec interface. 0: ac97_rst# is driven high. (default) 1: ac97_rst# is driven low. 6:4 reserved. must be set to 0. 3 ide controller reset. reset the ide controller. 0: disable. 1: enable. write 0 to clear. this bit is level-sensitive and must be cleared after the reset is enabled. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 211 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 2 ide reset. reset ide bus. 0: disable. 1: enable (drive ide_rst# low). write 0 to clear. this bit is level-sensitive and must be cleared after the reset is enabled. note: when x-bus warm start is enabled (bit 0 = 1) or duri ng por#, ide_rst# is put into tri-state mode. to prop- erly reset the ide bus, after por# the boot code must cause ide_rst# to activate. 1 pci reset. reset pci bus. 0: disable. 1: enable. when this bit is set to 1, the core logic module output signal pcirst# is asserted and all devices on the pci bus (including pciusb) are reset. no other function within the core logic module is affected by this bit. write 0 to clear this bit. this bit is level-sensitive and must be cleared after the reset is enabled. 0 x-bus warm start. writing and reading this bit each have different meanings. when reading this bit, it indicates whether or not a warm start occurred since power-up: 0: a warm start occurred. 1: no warm start has occurred. when writing this bit, it can be us ed to trigger a system-wide reset: 0: no effect. 1: execute system-wide reset (used only for clock configuration at power-up). index 45h reserved reset value: 00h index 46h pci functions enable register (r/w) reset value: feh 7:6 reserved. resets to 11. 5 f5 (pci function 5). when asserted (set to 1), enables the register space designated as f5. this bit must always be set to 1. (default) 4 f4 (pci function 4). when asserted (set to 1), enables the register space designated as f4. this bit must always be set to 1. (default) 3 f3 (pci function 3). when asserted (set to 1), enables the register space designated as f3. this bit must always be set to 1. (default) 2 f2 (pci function 2). when asserted (set to 1), enables the register space designated as f2. this bit must always be set to 1. (default) 1 f1 (pci function 1). when asserted (set to 1), enables the register space designated as f1. this bit must always be set to 1. (default) 0 reserved. must be set to 0. index 47h miscellaneous enable register (r/w) reset value: 00h 7:3 reserved. must be set to 0. 2 f0bar1 (pci function 0, base address register 1). f0bar1, pointer to i/o mapped lpc configuration registers. 0: disable. 1: enable. 1 f0bar0 (pci function 0, base address register 0). f0bar0, pointer to i/o mapped gpio configuration registers. 0: disable. 1: enable. 0 reserved. must be set to 0. index 48h-4bh reserved reset value: 00h table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
212 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 4ch-4fh top of system memory (r/w) reset value: ffffffffh 31:0 top of system memory. highest address in system used to determine acti ve decode for external pci mastered memory cycles. if an external pci master requests a memory address below t he value programmed in this regi ster, the cycle is transferred from the external pci bus interface to the fast-pci interface for servicing by the gx1 module. note: the four least significant bits must be set to 1100. index 50h pit control/isa clk divider (r/w) reset value: 7bh 7 pit software reset. 0: disable. 1: enable. 6 pit counter 1. 0: forces counter 1 output (out1) to zero. 1: allows counter 1 output (out1) to pass to the port 061h[4]. 5 pit counter 1 enable. 0: sets gate1 input low. 1: sets gate1 input high. 4 pit counter 0. 0: forces counter 0 output (out0) to zero. 1: allows counter 0 output (out0) to pass to irq0. 3 pit counter 0 enable. 0: sets gate0 input low. 1: sets gate0 input high. 2:0 isa clock divisor. determines the divisor of the pci clock used to ma ke the isa clock, which is typically programmed for approximately 8 mhz: 000: divide by 1 100: divide by 5 001: divide by 2 101: divide by 6 010: divide by 3 110: divide by 7 011: divide by 4 111: divide by 8 if pci clock = 25 mhz, use setting of 010 (divide by 3). if pci clock = 30 or 33 mhz, use a setting of 011 (divide by 4). index 51h isa i/o recovery control register (r/w) reset value: 40h 7:4 8-bit i/o recovery. these bits determine the number of isa bus cloc ks between back-to-back 8-bit i/o read cycles. this count is in addition to a preset one-cl ock delay built into the controller. 0000: 1 pci clock 0001: 2 pci clocks ::: ::: ::: 1111: 16 pci clocks 3:0 16-bit i/o recovery. these bits determine the number of isa bus cl ocks between back-to-back 16-bit i/o cycles. this count is in addition to a preset one-cl ock delay built into the controller. 0000: 1 pci clock 0001: 2 pci clocks ::: ::: ::: 1111: 16 pci clocks table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 213 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 52h rom/at logic control register (r/w) reset value: 98h 7 snoop fast keyboard gate a20 and fast reset. enables the snoop logic associat ed with keyboard commands for a20 mask and reset. 0: disable snooping. the keyboard controller handles the commands. 1: enable snooping. 6:5 reserved. must be set to 0. 4 enable a20m# de-assertion on warm reset. force a20m# high during a warm re set (guarantees that a20m# is de- asserted regardless of the state of a20). 0: disable. 1: enable. 3 enable port 092h (port a). port 092h decode and the logical functions. 0: disable. 1: enable. 2 upper rom size. selects upper rom addressing size. 0: 256k (fffc0000h-ffffffffh). 1: use rom mask register (f0 index 6ch). romcs# goes active for the above ranges whether strapped for isa or lpc. (refer to f0bar1+i/o offset 10h[15] for fur- ther strapping/programming details.) the selected range can then be either positively or subtractively decoded through f0 index 5bh[5]. 1 rom write enable . when asserted, enables writes to rom space, allowing flash programming. if strapped for isa and this bit is set to 1, writes to the c onfigured rom space asserts romcs# , enabling the write cycle to the flash device on the isa bus. otherwi se, romcs# is inhibited for writes. if strapped for lpc and this bit is set to 1, the cycle runs on the lpc bus. otherwise, the lpc bus cycle is inhibited for writes. refer to f0bar1+i/o offset 10h[15] for further strapping/programming details. 0 lower rom size. selects lower rom addressing size in which romcs# goes active. 0: lower rom access are 000f0000h-000fffffh (64 kb). (default) 1: lower rom accesses are 000e0000h-000fffffh (128 kb). romcs# goes active for the above ranges whether strapped for isa or lpc. (refer to f0bar1+i/o offset 10h[15] for fur- ther strapping/programming details.) the selected range can then be either positively or subtractively decoded through f0 index 5bh[5]. index 53h alternate cpu support register (r/w) reset value: 00h 7:6 reserved. must be set to 0. 5 bidirectional smi enable. 0: disable. 1: enable. this bit must be set to 0. 4:3 reserved. must be set to 0. 2 reserved. must be set to 0. 1 irq13 function selection. selects function of the internal irq13/ferr# signal. 0: ferr#. 1: irq13. this bit must be set to 1. 0 generate smi on a20m# toggle. 0: disable. 1: enable. this bit must be set to 1. smi status is reported at f1bar0+i/o offset 00h/02h[7]. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
214 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 54h-59h reserved reset value: 00h index 5ah decode control register 1 (r/w) reset value: 01h indicates pci positive or negative decodi ng for various i/o ports on the isa bus. note: positive decoding by the core logic module speeds up i/o cycle time. the i/o ports m entioned in the bit descriptions below, do not exist in the core logic module. it is assumed that if posi tive decode is enabled for a port, the port exists on the isa bus . 7 secondary floppy positive decode. selects pci positive or subtractive dec oding for accesses to i/o ports 372h-375h and 377h. 0: subtractive. 1: positive. 6 primary floppy positive decode. selects pci positive or subtractive decodi ng for accesses to i/o ports 3f2h-3f5h and 3f7h. 0: subtractive. 1: positive. 5 com4 positive decode. selects pci positive or subtractive decoding for accesses to i/o ports 2e8h-2efh. 0: subtractive. 1: positive. 4 com3 positive decode. selects pci positive or subtractive decoding for accesses to i/o ports 3e8h-3efh. 0: subtractive. 1: positive. 3 com2 positive decode. selects pci positive or subtractive decoding for accesses to i/o ports 2f8h-2ffh. 0: subtractive. 1: positive. 2 com1 positive decode. selects pci positive or subtractive decoding for accesses to i/o ports 3f8h-3ffh. 0: subtractive. 1: positive. 1 keyboard controller positive decode. selects pci positive or subtractive decoding for accesses to i/o ports 060h and 064h (as well as 062h and 066h, if enabled - f4 index 5bh[7] = 1). 0: subtractive. 1: positive. note: if f0bar1+i/o offset 10h bits 10 = 0 and 16 = 1, then this bit must be written 0. 0 real-time clock positive decode. selects pci positive or subtractive decoding for accesses to i/o ports 070h-073h. 0: subtractive. 1: positive. index 5bh decode control register 2 (r/w) reset value: 20h note: positive decoding by the core logic module speeds up the i/o cycle time. the key board, lpt3, lpt2, and lpt1 i/o ports do not exist in the core logic module. it is assumed that if pos itive decoding is enabled for any of these ports, the port exists on the isa bus. 7 keyboard i/o port 062h/066h positive decode. this alternate port to the keyboard controller is provided in support of power management features. 0: disable. 1: enable. 6 reserved. must be set to 0. 5 bios rom positive decode. selects pci positive or subtractive decodi ng for accesses to the configured rom space. 0: subtractive. 1: positive. rom configuration is at f0 index 52h[2:0]. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 215 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 4 secondary ide controller positive decode. selects pci positive or subtractive decoding for accesses to i/o ports 170h- 177h and 376h-377h (excluding writes to 377h). 0: subtractive. subtractively decoded ide addresses are forwarded to the pci slot bus. if a master abort occurs, they are then forwarded to isa. 1: positive. positively decoded ide addres ses are forwarded to the internal ide controller and then to the ide bus. 3 primary ide controller positive decode. selects pci positive or subtractive de coding for accesses to i/o ports 1f0h- 1f7h and 3f6h-3f7h (excluding writes to 3f7h). 0: subtractive. subtractively decoded ide addresses are forwarded to the pci slot bus. if a master abort occurs, they are then forwarded to isa. 1: positive. positively decoded ide addres ses are forwarded to the internal ide controller and then to the ide bus. 2 lpt3 positive decode. selects pci positive or subtractive dec oding for accesses to i/o ports 278h-27fh. 0: subtractive. 1: positive. 1 lpt2 positive decode. selects pci positive or subtractive dec oding for accesses to i/o ports 378h-37fh. 0: subtractive. 1: positive. 0 lpt1 positive decode. selects pci positive or subtractive decodi ng for accesses to i/o ports 3bch-3bfh 0: subtractive. 1: positive. index 5ch pci interrupt steering register 1 (r/w) reset value: 00h indicates target interrupts for signals intb# and inta#. note: the target interrupt must first be configured as level sensitiv e via i/o ports 4d0h and 4d1h in order to maintain pci interrupt compatibility. 7:4 intb# (ebga ball af1 / tepbga ball c26) target interrupt. 0000: disable 0100: irq4 1000: reserved 1100: irq12 0001: irq1 0101: irq5 1001: irq9 1101: reserved 0010: reserved 0110: irq6 1010: irq10 1110: irq14 0011: irq3 0111: irq7 1011: irq11 1111: irq15 3:0 inta# (ebga ball ae3 / tepbga ball d26) target interrupt. 0000: disable 0100: irq4 1000: reserved 1100: irq12 0001: irq1 0101: irq5 1001: irq9 1101: reserved 0010: reserved 0110: irq6 1010: irq10 1110: irq14 0011: irq3 0111: irq7 1011: irq11 1111: irq15 index 5dh pci interrupt steering register 2 (r/w) reset value: 00h indicates target interrupts for signals intd# and intc#. note that intd# is muxed with ide_data7 (selection made via pmr[24]) a nd intc# is muxed with gpio19+iochrdy (selection made via pmr[9,4]). see table 4-2 on page 88 for pmr bit descriptions. note: the target interrupt must first be configured as level sensitiv e via i/o ports 4d0h and 4d1h in order to maintain pci interrupt compatibility. 7:4 intd# (ebga ball b22 / tepbga ball aa2) target interrupt. 0000: disable 0100: irq4 1000: reserved 1100: irq12 0001: irq1 0101: irq5 1001: irq9 1101: reserved 0010: reserved 0110: irq6 1010: irq10 1110: irq14 0011: irq3 0111: irq7 1011: irq11 1111: irq15 3:0 intc# (ebga ball h4 / tepbga ball c9) target interrupt. 0000: disable 0100: irq4 1000: reserved 1100: irq12 0001: irq1 0101: irq5 1001: irq9 1101: reserved 0010: reserved 0110: irq6 1010: irq10 1110: irq14 0011: irq3 0111: irq7 1011: irq11 1111: irq15 index 5eh-5fh reserved reset value: 00h table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
216 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 60h-63h acpi control re gister (r/w) reset value: 00000000h 31:8 reserved. must be set to 0. 7 susp_3v shut down pll5. allow internal susp_3v to shut down pll5. 0: clock generator is stopped when internal susp_3v is active. 1: clock generator continues working when internal susp_3v is active. 6 susp_3v shut down pll4. allow internal susp_3v to shut down pll4 0: clock generator is stopped when internal susp_3v is active. 1: clock generator continues working when internal susp_3v is active. 5 susp_3v shut down pll3. allow internal susp_3v to shut down pll3. 0: clock generator is stopped when internal susp_3v is active. 1: clock generator continues working when internal susp_3v is active. 4 susp_3v shut down pll2. allow internal susp_3v to shut down pll2. 0: clock generator is stopped when internal susp_3v is active. 1: clock generator continues working when internal susp_3v is active. 3 susp_3v shut down pll6. allow internal susp_3v to shut down pll6. 0: clock generator is stopped when internal susp_3v is active. 1: clock generator continues working when internal susp_3v is active. 2 acpi c3 susp_3v enable. allow internal susp_3v to be active during c3 state. 0: disable. 1: enable. 1 acpi sl1 susp_3v enable. allow internal susp_3v to be active during sl1 sleep state. 0: disable. 1: enable. 0 acpi c3 support enable. allow support of c3 states. 0: disable. 1: enable. index 64h-6bh reserved reset value: 00h index 6ch-6fh rom mask register (r/w) reset value: 0000fff0h note: register must be read/written as a dword. 31:16 reserved. must be written to 0. 15:8 reserved. must be written to ffh. 7:4 rom size. if f0 index 52h[2] = 1: 0000: 16 mb = ff000000h-ffffffffh 1000: 8 mb = ff800000h-ffffffffh 1100: 4 mb = ffc00000h-ffffffffh 1110: 2 mb = ffe00000h-ffffffffh 1111: 1 mb = fff00000h-ffffffffh all other settings for these bits are reserved. 3:0 reserved. must be set to 0. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 217 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 70h-71h iocs1# base address register (r/w) reset value: 0000h 15:0 i/o chip select 1 base address. this 16-bit value represent s the i/o base address used to enable assertion of iocs1# (ebga ball h2 or al12 / tepbga ball d10 or n30 - see pmr[23] in table 4-2 on page 88). this register is used in c onjunction with f0 index 72h (iocs1# control register). index 72h iocs1# control register (r/w) reset value: 00h this register is used in conj unction with f0 index 70h (iocs1# base address register). 7 i/o chip select 1 positive decode (iocs1#). 0: disable. 1: enable. 6 writes result in chip select. when this bit is set to 1, writes to c onfigured i/o address (base address configured in f0 index 70h; range configured in bits [4:0]) cause iocs1# to be asserted. 0: disable. 1: enable. 5 reads result in chip select. when this bit is set to 1, re ads from configured i/o address (b ase address configured in f0 index 70h; range configured in bits [4:0]) cause iocs1# to be asserted. 0: disable. 1: enable. 4:0 iocs1# i/o address range. this 5-bit field is used to select the range of iocs1#. 00000: 1 byte 01111: 16 bytes 00001: 2 bytes 11111: 32 bytes 00011: 4 bytes all other combinations are reserved. 00111: 8 bytes index 73h reserved reset value: 00h index 74h-75h iocs0# base address register (r/w) reset value: 0000h 15:0 i/o chip select 0 base address. this 16-bit value represents the i/o bas e address used to enable the assertion of iocs0# (ebga ball j4 / tepbga ball a10 - see pmr[23] in table 4-2 on page 88). this register is used in c onjunction with f0 index 76h (iocs0# control register). index 76h iocs0# control register (r/w) reset value: 00h this register is used in conj unction with f0 index 74h (iocs0# base address register). 7 i/o chip select 0 positive decode (iocs0#). 0: disable. 1: enable. 6 writes result in chip select. when this bit is set to 1, writes to c onfigured i/o address (base address configured in f0 index 74h; range configured in bits [4:0]) cause iocs0# to be asserted. 0: disable. 1: enable. 5 reads result in chip select. when this bit is set to 1, re ads from configured i/o address (b ase address configured in f0 index 74h; range configured in bits [4:0]) cause iocs0# to be asserted. 0: disable. 1: enable. 4:0 iocs0# i/o address range. this 5-bit field is used to select the range of iocs0#. 00000: 1 byte 01111: 16 bytes 00001: 2 bytes 11111: 32 bytes 00011: 4 bytes all other combinations are reserved. 00111: 8 bytes index 77h reserved reset value: 00h table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
218 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 78h-7bh doccs# base address register (r/w) reset value: 00000000h 31:0 diskonchip chip select base address. this 32-bit value represents the memo ry base address used to enable assertion of doccs# (ebga ball h3 or aj13 / tepbga ball a9 or n31, see pmr[23] in table 4-2 on page 88). this register is used in c onjunction with f0 index 7ch (doccs# control register). index 7ch-7fh doccs# control register (r/w) reset value: 00000000h this register is used in conj unction with f0 index 78h (doccs# base address register). 31:27 reserved. must be set to 0. 26 diskonchip chip select positive decode (doccs#). 0: disable. 1: enable. 25 writes result in chip select. when this bit is set to 1, writes to conf igured memory address (bas e address configured in f0 index 78h; range configured in bits [18:0]) cause doccs# to be asserted. 0: disable. 1: enable. 24 reads result in chip select. when this bit is set to 1, reads from conf igured memory address (base address configured in f0 index 78h; range configured in bits [18:0]) cause doccs# to be asserted. 0: disable. 1: enable. 23:19 reserved. must be set to 0. 18:0 doccs# memory address range. this 19-bit mask is used to qualify ac cesses on which doccs# is asserted by mask- ing the upper 19 bits of the incoming pci address (ad[31:13]). index 80h power management enable register 1 (r/w) reset value: 00h 7:6 reserved. must be set to 0. 5 codec sdata_in smi. when set to 1, this bit allows an smi to be generated in response to an ac97 codec producing a positive edge on sdata_in. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 87h/f7h[2]. 4 video speedup. any video activity, as decoded from the serial connec tion (pserial) from the gx1 module disables clock throttling (via internal susp#/suspa# handshake) for a conf igurable duration when system is power-managed using cpu suspend modulation. 0: disable. 1: enable. the duration of the speedup is configured in the video spe edup timer count register (f0 index 8dh). detection of an external vga access (3bx, 3cx, 3dx and a000h-b7ffh) on the pci bus is also supported. this configuration is non-stan- dard, but it does allow the power management routines to support an external vga chip. 3 irq speedup. any unmasked irq (per i/o ports 021h/0a1h) or smi di sables clock throttling (via internal susp#/suspa# handshake) for a configurable duration when s ystem is power-managed using cpu suspend modulation. 0: disable. 1: enable. the duration of the speedup is configured in the irq speedup timer count register (f0 index 8ch). 2 traps. globally enable all power management i/o traps. 0: disable. 1: enable. this excludes the audio i/o traps, which are enabled via f3bar0+memory offset 18h. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 219 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 1 idle timers. device idle timers. 0: disable. 1: enable. note: disable at this level does not reload the timers on the enable. the timers are disabled at their current counts. this bit has no affect on the suspend modulation register (f0 index 94h). only applicable when in apm mode (f1bar1+i/o offset 0ch[0] = 0) and not acpi mode. 0 power management. global power management. 0: disable. 1: enable. this bit must be set to 1 immediately after post for power management resources to function. index 81h power management enable register 2 (r/w) reset value: 00h 7 video access idle timer enable. turn on video idle timer count register (f0 index a6h) and generate an smi when the timer expires. 0: disable. 1: enable. if an access occurs in the video address range (sets bit 0 of the gx1 module?s pserial register) the timer is reloaded with the programmed count. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[7]. 6 user defined device 3 (udef3) idle timer enable. turn on udef3 idle timer count register (f0 index a4h) and gener- ate an smi when the timer expires. 0: disable. 1: enable. if an access occurs in the programmed address range, the timer is reloaded with the programmed count. udef3 address programming is at f0 index c8h ( base address register) and ceh (control register). top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[6]. 5 user defined device 2 (udef2) idle timer enable. turn on udef2 idle timer count register (f0 index a2h) and gener- ate an smi when the timer expires. 0: disable. 1: enable. if an access occurs in the programmed address range, the timer is reloaded with the programmed count. udef2 address programming is at f0 index c4h ( base address register) and cdh (control register). top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[5]. 4 user defined device 1 (udef1) idle timer enable. turn on udef1 idle timer count register (f0 index a0h) and gener- ate an smi when the timer expires. 0: disable. 1: enable. if an access occurs in the programmed address range, the timer is reloaded with the programmed count. udef1 address programming is at f0 index c0h ( base address register) and cch (control register). top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[4]. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
220 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 3 keyboard/mouse idle timer enable. turn on keyboard/mouse idle timer count register (f0 index 9eh) and generate an smi when the timer expires. 0: disable. 1: enable. if an access occurs in the address ranges listed belo w, the timer is reloaded with the programmed count: ? keyboard controller: i/o ports 060h/064h. ? com1: i/o port 3f8h-3ffh (if f0 index 93h[1:0] = 10 this range is included). ? com2: i/o port 2f8h-2ffh (if f0 index 93h[1:0] = 11 this range is included). top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[3]. 2 parallel/serial idle timer enable. turn on parallel/serial port idle timer count register (f0 index 9ch) and generate an smi when the timer expires. 0: disable. 1: enable. if an access occurs in the address ranges listed belo w, the timer is reloaded with the programmed count. ? lpt1: i/o port 3bch-3beh. ? lpt2: i/o port 378h-37fh. ? com1: i/o port 3f8h-3ffh (if f0 index 93h[1:0] = 10 this range is excluded). ? com2: i/o port 2f8h-2ffh (if f0 index 93h[1:0] = 11 this range is excluded). ? com3: i/o port 3e8h-3efh. ? com4: i/o port 2e8h-2efh. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[2]. 1 floppy disk idle timer enable. turn on floppy disk idle timer count register (f0 index 9ah) and generate an smi when the timer expires. 0: disable. 1: enable. if an access occurs in the address ranges (listed bel ow, the timer is reloaded with the programmed count. ? primary floppy disk: i/o port 3f2h-3f5h, 3f7h. ? secondary floppy disk: i/o port 372h-375h, 377h. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[1]. 0 primary hard disk idle timer enable. turn on primary hard disk idle timer count register (f0 index 98h) and generate an smi when the timer expires. 0: disable. 1: enable. if an access occurs in the address ranges selected in f0 index 93h[5], the timer is reloaded with the programmed count. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[0]. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 221 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 82h power management enable register 3 (r/w) reset value: 00h 7 video access trap. if this bit is enabled and an access occurs in the video address range (sets bit 0 of the gx1 module?s pserial register), an smi is generated. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 86h/f6h[7]. 6 user defined device 3 (udef3) access trap. if this bit is enabled and an access occurs in the programmed address range, an smi is generated. udef3 address programming is at f0 index c8h (base address register) and ceh (control register). 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[4]. 5 user defined device 2 (udef2) access trap. if this bit is enabled and an access occurs in the programmed address range, an smi is generated. udef2 address programming is at f0 index c4h (base addres s register) and cdh (control register). 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[3]. 4 user defined device 1 (udef1) access trap. if this bit is enabled and an access occurs in the programmed address range, an smi is generated. udef1 address programming is at f0 index c0h (base address register), and cch (control register). 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[2]. 3 keyboard/mouse access trap. 0: disable. 1: enable. if this bit is enabled and an access occurs in the address ranges listed below, an smi is generated. ? keyboard controller: i/o ports 060h/064h. ? com1: i/o port 3f8h-3ffh (if f0 index 93h[1:0] = 10 this range is included). ? com2: i/o port 2f8h-2ffh (if f0 index 93h[1:0] = 11 this range is included). top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 86h/f6h[3]. 2 parallel/serial access trap. 0: disable. 1: enable. if this bit is enabled and an access occurs in the address ranges listed below, an smi is generated. ? lpt1: i/o port 3bch-3beh. ? lpt2: i/o port 378h-37fh. ? com1: i/o port 3f8h-3ffh (if f0 index 93h[1:0] = 10 this range is excluded). ? com2: i/o port 2f8h-2ffh (if f0 index 93h[1:0] = 11 this range is excluded). ? com3: i/o port 3e8h-3efh. ? com4: i/o port 2e8h-2efh. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 86h/f6h[2]. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
222 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 1 floppy disk access trap. 0: disable. 1: enable. if this bit is enabled and an access occurs in the address ranges listed below, an smi is generated. ? primary floppy disk: i/o port 3f2h-3f5h, 3f7h. ? secondary floppy disk: i/o port 372h-375h, 377h. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 86h/f6h[1]. 0 primary hard disk access trap. 0: disable. 1: enable. if this bit is enabled and an access occurs in the addre ss ranges selected in f0 index 93h[5], an smi is generated. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 86h/f6h[0]. index 83h power management enable register 4 (r/w) reset value: 00h 7 secondary hard disk idle timer enable. turn on secondary hard disk idle timer count register (f0 index ach) and generate an smi when the timer expires. 0: disable. 1: enable. if an access occurs in the address ranges selected in f0 index 93h[4], the timer is reloaded with the programmed count. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 86h/f6h[4]. 6 secondary hard disk access trap. if this bit is enabled and an access occurs in the address ranges selected in f0 index 93h[4], an smi is generated. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 86h/f6h[5]. 5 acpi timer smi. allow smi generation for msb toggles on the acpi timer (f1bar0+i/o offset 1ch or f1bar1+i/o offset 1ch). 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 87h/f7h[0]. 4 thrm# smi. allow smi generation on assertion of thrm#. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 87h/f7h[6]. 3 vga timer enable. turn on vga timer count register (f0 index 8eh) and generate an smi when the timer reaches 0. 0: disable. 1: enable. if an access occurs in the programmed address range, the time r is reloaded with the programmed count. f0 index 8bh[6] selects the timebase for the vga timer. smi status is reported at f1bar0+i/o offset 00h/02h[6] (top level only). table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 223 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 2 video retrace interrupt smi. allow smi generation whenever video retrace occurs. 0: disable. 1: enable. this information is decoded from the serial connection (pserial r egister, bit 7) from the gx1 module. this function is nor- mally not used for power management but for soft (vsa) vga routines. smi status reporting is at f1bar0+i/o offset 00h/02h[5] (top level only). 1 general purpose timer 2 enable. turn on gp timer 2 count register (f0 index 8ah) and generate an smi when the timer expires. 0: disable. 1: enable. this idle timer is reloaded from the as sertion of gpio7 (if programmed to do so). gp timer 2 programming is at f0 index 8bh[5,3,2]. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[1]. 0 general purpose timer 1 enable. turn on gp timer 1 count register (f0 index 88h) and generate an smi when the timer expires. 0: disable. 1: enable. this idle timer?s load is multi-s ourced and gets reloaded any time an enabled event (f0 index 89h[6:0]) occurs. gp timer 1 programming is at f0 index 8bh[4]. top level smi status is reported at f1bar0+i/o offset 00h/02h[9]. second level smi status is report ed at f1bar0+i/o offset 04h/06h[0]. index 84h second level pme/smi status mirror register 1 (ro) reset value: 00h the bits in this register are used for the second level of stat us reporting. the top level is reported at f1bar0+i/o offset 00h /02h[0]. this register is called a "mirror" register since an identical register exists at f0 index f4h. reading this register does not clear the status, while reading its counterpart at f0 index f4h clears the status at both the second and the top levels. 7:3 reserved. reads as 0. 2 gpwio2 smi status. indicates whether or not an smi was c aused by a transition on the gpwio2 pin. 0: no. 1: yes. to enable smi generation: 1) ensure that gpwio2 is enabled as an input: f1bar1+i/o offset 15h[2] = 0. 2) set f1bar1+i/o offset 15h[6] to 1. 1 gpwio1 smi status. indicates whether or not an smi was c aused by a transition on the gpwio1 pin. 0: no. 1: yes. to enable smi generation: 1) ensure that gpwio1 is enabled as an input: f1bar1+i/o offset 15h[1] = 0. 2) set f1bar1+i/o offset 15h[5] to 1. 0 gpwio0 smi status. indicates whether or not an smi was c aused by a transition on the gpwio0 pin. 0: no. 1: yes. to enable smi generation: 1) ensure that gpwio0 is enabled as an input: f1bar1+i/o offset 15h[0] = 0. 2) set f1bar1+i/o offset 15h[4] to 1. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
224 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 85h second level pme/smi status mirror register 2 (ro) reset value: 00h the bits in this register c ontain second level status reporting. top level st atus is reported in f1bar0+i/o offset 00h/02h[0]. this register is called a ?mirro r? register since an identical regi ster exists at f0 index f5h. reading this register does not clear the status, while reading its counterpart at f0 index f5h clears the status at both the second and top levels. 7 video idle timer timeout. indicates whether or not an smi was caused by expiration of video idle timer count register (f0 index a6h). 0: no. 1: yes. to enable smi generation, set f0 index 81h[7] to 1. 6 user defined device idle timer 3 timeout. indicates whether or not an smi was caused by expiration of user defined device 3 idle timer count register (f0 index a4h). 0: no 1: yes to enable smi generation, set f0 index 81h[6] to 1. 5 user defined device idle timer 2 timeout. indicates whether or not an smi was caused by expiration of user defined device 2 idle timer count register (f0 index a2h). 0: no. 1: yes. to enable smi generation, set f0 index 81h[5] to 1. 4 user defined device idle timer 1 timeout. indicates whether or not an smi was caused by expiration of user defined device 1 idle timer count register (f0 index a0h). 0: no. 1: yes. to enable smi generation, set f0 index 81h[4] to 1. 3 keyboard/mouse idle timer timeout. indicates whether or not an smi was caus ed by expiration of keyboard/mouse idle timer count register (f0 index 9eh). 0: no. 1: yes. to enable smi generation, set f0 index 81h[3] to 1. 2 parallel/serial idle timer timeout. indicates whether or not an smi was caused by expiration of parallel/serial port idle timer count register (f0 index 9ch). 0: no. 1: yes. to enable smi generation, set f0 index 81h[2] to 1. 1 floppy disk idle timer timeout. indicates whether or not an smi was caused by expiration of floppy disk idle timer count register (f0 index 9ah). 0: no. 1: yes. to enable smi generation, set f0 index 81h[1] to 1. 0 primary hard disk idle timer timeout. indicates whether or not an smi was caused by expiration of primary hard disk idle timer count register (f0 index 98h). 0: no. 1: yes. to enable smi generation, set f0 index 81h[0] to 1. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 225 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 86h second level pme/smi status mirror register 3 (ro) reset value: 00h the bits in this register c ontain second level status reporting. top level st atus is reported in f1bar0+i/o offset 00h/02h[0]. this register is called a ?mirro r? register since an identical regi ster exists at f0 index f6h. reading this register does not clear the status, while reading its counterpart at f0 index f6h clears the status at both the second and top levels. 7 video access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to the video i/o tr a p. 0: no. 1: yes. to enable smi generation, set f0 index 82h[7] to 1. 6 reserved. 5 secondary hard disk access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to the secondary hard disk. 0: no. 1: yes. to enable smi generation, set f0 index 83h[6] to 1. 4 secondary hard disk idle timer smi status. indicates whether or not an smi wa s caused by expiration of secondary hard disk idle timer count register (f0 index ach). 0: no. 1: yes. to enable smi generation, set f0 index 83h[7] to 1. 3 keyboard/mouse access trap smi status. indicates whether or not an smi was caused by an trapped i/o access to the keyboard or mouse. 0: no. 1: yes. to enable smi generation, set f0 index 82h[3] to 1. 2 parallel/serial access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to either the serial or parallel ports. 0: no. 1: yes. to enable smi generation, set f0 index 82h[2] to 1. 1 floppy disk access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to the floppy disk. 0: no. 1: yes. to enable smi generation, set f0 index 82h[1] to 1. 0 primary hard disk access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to the primary hard disk. 0: no. 1: yes. to enable smi generation, set f0 index 82h[0] to 1. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
226 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 87h second level pme/smi status mirror register 4 (ro) reset value: 00h the bits in this register cont ain second level status reporting. top level status is reported at f1bar0+i/o offset 00h/02h[0]. this register is called a ?mirro r? register since an identical regi ster exists at f0 index f7h. reading this register does not clear the status, while reading its counterpart at f0 index f7h clears the status at both the second and top levels except for bit 7 which has a third level of smi status reporting at f0bar0+i/o 0ch/1ch. 7 gpio event smi status. indicates whether or not an smi was caused by a transition of any of the gpios (gpio47-gpio32 and gpio15-gpio0). 0: no. 1: yes. to enable smi generation, set f1bar1+i/o offset 0ch[0] to 0. f0bar0+i/o offset 08h/18h selects which gpios are enabled to generate a pme and setting f1bar1+i/o offset 0ch[0] = 0 enables the pme to generate an smi. in addition, the selected gpio must be enabled as an input (f0bar0+i/o offset 20h and 24h). the next level (third level) of smi status is at f0bar0+i/o 0ch/1ch[15:0]. 6 thermal override smi status. indicates whether or not an smi was caused by the assertion of thrm#. 0: no. 1: yes. to enable smi generation, set f0 index 83h[4] to 1. 5:4 reserved. always reads 0. 3 sio pwureq smi status. indicates whether or not an smi was caused by a power-up event from the sio. 0: no. 1: yes. a power-up event is defined as any of the following events/activities: ?ri2# ?sdata_in2 ? irrx1 (ceir) to enable smi generation, set f1bar1+i/o offset 0ch[0] to 0. 2 codec sdata_in smi status. indicates whether or not an smi was ca used by ac97 codec producing a positive edge on sdata_in. 0: no. 1: yes. to enable smi generation, set f0 index 80h[5] to 1. 1 rtc alarm (irq8#) smi status. indicates whether or not an smi was caused by an rtc interrupt. 0: no. 1: yes. this smi event can only occur while in 3v suspend and an rt c interrupt occurs with f1bar1+i/o offset 0ch[0] = 0. 0 acpi timer smi status. indicates whether or not an smi was caused by an acpi timer (f1bar0+i/o offset 1ch or f1bar1+i/o offset 1ch) msb toggle. 0: no. 1: yes. to enable smi generation, set f0 index 83h[5] to 1. index 88h general purpose timer 1 count register (r/w) reset value: 00h 7:0 gpt1_count. this field represents the load value for general purpos e timer 1. this value can represent either an 8-bit counter or a 16-bit counter (selected in f0 index 8bh[4]). it is loaded into the counter when the timer is enabled (f0 index 83h[0] = 1). once enabled, an enabled event (configured in f0 index 89h[6:0]) reloads the timer. the counter is decremented with each clock of the configured timebase (1 ms or 1 sec selected at f0 index 89h[7]). upon expiration of the counter, an smi is generated, and the top leve l smi status is reported at f1bar0+i/o offset 00h/02h[9]. the second level smi status is reported at f1bar0+i/o offset 04h/06h[0]. once expired, this counter must be re-initialized by either disabling and enabling it, or writing a new count va lue in this register. see section 6.2.10.3 "peripheral power management" on page 180 for a discussion on the limitati ons of producing count error with small values. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 227 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 89h general purpose timer 1 control register (r/w) reset value: 00h 7 general purpose timer 1 timebase. selects timebase for general purpose timer 1 (f0 index 88h). 0: 1 second. 1: 1 millisecond. 6 re-trigger general purpose timer 1 on user defined device 3 (udef3) activity. 0: disable. 1: enable. any access to the configured (memory or i/o) address range for udef3 (configured in f0 index c8h and ceh) reloads general purpose timer 1. 5 re-trigger general purpose timer 1 on user defined device 2 (udef2) activity. 0: disable. 1: enable. any access to the configured (memory or i/o) address range for udef2 (configur ed in f0 index c4h and cdh) reloads general purpose timer 1. 4 re-trigger general purpose timer 1 on user defined device 1 (udef1) activity . 0: disable. 1: enable. any access to the configured (memory or i/o) address range for udef1 (configur ed in f0 index c0h and cch) reloads general purpose timer 1. 3 re-trigger general purpose timer 1 on keyboard or mouse activity. 0: disable. 1: enable. any access to the keyboard or mouse i/o address range listed below reloads general purpose timer 1: ? keyboard controller: i/o ports 060h/064h. ? com1: i/o port 3f8h-3ffh (if f0 index 93h[1:0] = 10 this range is included). ? com2: i/o port 2f8h-2ffh (if f0 index 93h[1:0] = 11 this range is included). 2 re-trigger general purpose timer 1 on parallel/serial port activity. 0: disable. 1: enable. any access to the parallel or serial port i/o addres s range listed below reloads the general purpose timer 1: ? lpt1: i/o port 3bch-3beh. ? lpt2: i/o port 378h-37fh. ? com1: i/o port 3f8h-3ffh (if f0 index 93h[1:0] = 10 this range is excluded). ? com2: i/o port 2f8h-2ffh (if f0 index 93h[1:0] = 11 this range is excluded). ? com3: i/o port 3e8h-3efh. ? com4: i/o port 2e8h-2efh. 1 re-trigger general purpose timer 1 on floppy disk activity. 0: disable. 1: enable. any access to the floppy disk drive address ranges listed below reloads g eneral purpose timer 1: ? primary floppy disk: i/o port 3f2h-3f5h, 3f7h ? secondary floppy disk: i/o port 372h-375h, 377h the active floppy disk drive is configured via f0 index 93h[7]. 0 re-trigger general purpose timer 1 on primary hard disk activity. 0: disable. 1: enable. any access to the primary hard disk address range select ed in f0 index 93h[5], reloads general purpose timer 1. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
228 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 8ah general purpose timer 2 count register (r/w) reset value: 00h 7:0 gpt2_count. this field represents the load value for general purpose timer 2. this value can r epresent either an 8-bit or 16-bit counter (configured in f0 index 8bh[5]). it is loaded into the counter when the timer is enabled (f0 index 83h[1] = 1). once the timer is enabled and a transition occurs on gpio7, the timer is re-loaded. the counter is decremented with each clock of the configured timebase (1 ms or 1 sec selected at f0 index 8bh[3]). upon expiration of the counter, an smi is generated and the top leve l of status is f1bar0+i/o offset 00h/02h[9]. the second level of status is reported at f1bar0+i/o offset 04h/06h[1]). on ce expired, this counter must be re-initialized by either dis- abling and enabling it, or by writing a new count value in th is register. section 6.2.10.3 "peripheral power management" on page 180 for a discussion on the limitations of producing count error with small values. for gpio7 to act as the reload for this counter, it must be enabled as such (f0 index 8bh[2]) and be configured as an input. (gpio pin programming is at f0bar0+i/o offset 20h and 24h.) index 8bh general purpose timer 2 control register (r/w) reset value: 00h 7 re-trigger general purpose timer 1 (gp timer 1) on secondary hard disk activity. 0: disable. 1: enable. any access to the secondary hard disk address range selected in f0 index 93h[4] reloads gp timer 1. 6 vga timer base. selects timebase for vga timer register (f0 index 8eh). 0: 1 millisecond. 1: 32 microseconds. 5 general purpose timer 2 (gp timer 2) shift. gp timer 2 is treated as an 8-bit or 16-bit timer. 0: 8-bit. the count value is loaded into gp timer 2 count register (f0 index 8ah). 1: 16-bit. the value loaded into gp timer 2 count register is shifted left by eigh t bits, the lower eight bits become zero, and this 16-bit value is used as the count for gp timer 2. 4 general purpose timer 1 (gp timer 1) shift. gp timer 1 is treated as an 8-bit or 16-bit timer. 0: 8-bit. the count value is that loaded into gp timer 1 count register (f0 index 88h). 1: 16-bit. the value loaded into gp timer 1 count register is shifted left by eight bit, the lower eight bits become zero, and this 16-bit value is used as the count for gp timer 1. 3 general purpose timer 2 (gp timer 2) timebase. selects timebase for gp timer 2 (f0 index 8ah). 0: 1 second. 1: 1 millisecond. 2 re-trigger timer on gpio7 pin transition. a rising-edge transition on the gpio7 pi n reloads gp timer 2 (f0 index 8ah). 0: disable. 1: enable. for gpio7 to work here, it must firs t be configured as an input. (gpio pin pr ogramming is at f0bar0+i/o offset 20h and 24h.) 1:0 reserved. set to 0. index 8ch irq speedup timer count register (r/w) reset value: 00h 7:0 irq speedup timer load value. this field represents the load value for the irq speedup timer. it is loaded into the counter when suspend modulation is enabled (f0 index 96h[0] = 1) and an intr or an access to i/o port 061h occurs. when the event occurs, the suspend modulati on logic is inhibited, permi tting full performance operation of the gx1 module. upon expiration, no smi is generated; the suspend modulation begins again. the irq speedup timer?s timebase is 1 ms. this speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. a typical value here would be 2 to 4 ms. index 8dh video speedup timer count register (r/w) reset value: 00h 7:0 video speedup timer load value. this field represents the load value for the video speedup timer. it is loaded into the counter when suspend modulation is enabled (f0 index 96[0] = 1) and any access to the graphics controller occurs. when a video access occurs, the suspend modulation logic is inhibi ted, permitting full-performance operation of the gx1 module. upon expiration, no smi is generated, and suspend modulation begins again. the video speedup ti mer?s timebase is 1 ms. this speedup mechanism allows instantaneous response to video activity for fu ll speed during video processing calcula- tions. a typical value here would be 50 ms to 100 ms. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 229 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 8eh vga timer count register (r/w) reset value: 00h 7:0 vga timer load value. this field represents the load value for vga timer. it is loaded into the counter when the timer is enabled (f0 index 83h[3] = 1). the counter is decremented with each clock of the configured timebase (f0 index 8bh[6]). upon expiration of the counter, an smi is generated and the stat us is reported at f1bar0+i/o offset 00h/02h[6] (only). once expired, this counter must be re-initi alized by either disabling and enabling it, or by writing a new count value in this register. note: although grouped with the power management idle timers , the vga timer is not a power management function. it is not affected by the global power management enable setting at f0 index 80h[0]. index 8fh-92h reserved reset value: 00h index 93h miscellaneous device control register (r/w) reset value: 00h 7 floppy drive port select. indicates whether all system resources used to power manage the floppy drive use the primary, or secondary fdc addresses for decode. 0: secondary. 1: primary. 6 reserved. must be set to 1. 5 partial primary hard disk decode. this bit is used to restrict the addr esses which are decoded as primary hard disk accesses. 0: power management monitors all reads and writes to i/o port 1f0h-1f7h, 3f6h-3f7h (excludes writes to 3f7h), and 170h-177h, 376h-377h (excludes writes to 377h). 1: power management monitors only writes to i/o port 1f6h and 1f7h. 4 partial secondary hard disk decode. this bit is used to restrict the addr esses which are decoded as secondary hard disk accesses. 0: power management monitors all reads and writes to i/o port 170h-177h, 376h-377h (excludes writes to 377h). 1: power management monitors only writes to i/o port 176h and 177h. 3:2 reserved. must be set to 0. 1 mouse on serial enable. mouse is present on a serial port. 0: no. 1: yes. if a mouse is attached to a serial port (i.e ., this bit is set to 1), that port is re moved from the serial device list being us ed to monitor serial port access for power management purpos es and added to the keyboard/mouse decode. this is done because a mouse, along with the keyboard, is considered an i nput device and is used only to determine when to blank the screen. this bit and bit 0 of this register determine the decode used for the keyboard/mouse idle timer count register (f0 index 9eh) as well as the parallel/serial port idle timer count register (f0 index 9ch). 0 mouse port select. selects which serial port the mouse is attached to: 0: com1 1: com2. for more information see the description of bit 1 in this register (above). index 94h-95h suspend modulation register (r/w) reset value: 0000h 15:8 suspend signal asserted counter. this 8-bit counter represents the number of 32 s intervals that the internal susp# signal is asserted to the gx1 module. t ogether with bits [7:0], perform the su spend modulation function for cpu power management. the ratio of susp# asserted-to-de-asserted sets up an effective (emulated) clock frequency, allowing the power manager to reduce gx1 module power consumption. this counter is prematurely re set if an enabled speedup event occurs (i.e., irq and video speedups). 7:0 suspend signal de-asserted counter. this 8-bit counter represents the number of 32 s intervals that the internal susp# signal is de-asserted to the gx1 module. together with bits [15:8], perform the suspend modulation function for cpu power management. the ratio of susp# asserted-to-de-asserted sets up an effective (emulated) clock frequency, allowing the power manager to reduce gx1 module power consumption. this counter is prematurely re set if an enabled speedup event occurs (i.e., irq and video speedups). table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
230 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 96h suspend configuration register (r/w) reset value: 00h 7:3 reserved. must be set to 0. 2 suspend mode configuration. special 3v suspend mode to support powering down the gx1 module during suspend. 0: disable. 1: enable. 1 smi speedup configuration. selects how the suspend modulation function should react when an smi occurs. 0: use the irq speedup timer count register (f0 index 8ch) to temporarily disable suspend modulation when an smi occurs. 1: disable suspend modulation when an smi occurs until a read to the smi speedup disable register (f1bar0+i/o offset 08h). the purpose of this bit is to disable suspend modulation while the gx1 module is in the system management mode so that vsa and power management operations occur at full speed. two methods for accomplishing this are: map the smi into the irq speedup timer count register (f0 index 8ch). - or - have the smi disable suspend modulation until the smi handl er reads the smi speedup disable register (f1bar0+i/o offset 08h). this the preferred method. this bit has no affect if the suspend modul ation feature is disabled (bit 0 = 0). 0 suspend modulation feature enable. this bit is used to enable/dis able the suspend modulation feature. 0: disable. 1: enable. when enabled, the internal susp# signal is asserted and de-asserted for the durations programmed in the suspend modu- lation register (f0 index 94h). the setting of this bit is mirrored in the top level pme/smi status register (f1bar0+i/o offset 00h/02h[15]. it is used by the smi handler to determine if the smi speedup disable r egister (f1bar0+i/o offset 08h) must be cleared on exit. index 97h reserved reset value: 00h index 98h-99h primary hard disk idle timer count register (primary channel) (r/w) reset value: 0000h 15:0 primary hard disk idle timer count. this idle timer is used to determine when t he primary hard disk is not in use so that it can be powered down. the 16-bit value pr ogrammed here represents the period of hard disk inactivity after which the sys- tem is alerted via an smi. the timer is aut omatically reloaded with the count value w henever an access occurs to the config- ured hard disk?s data port (i/o port 1f0h or 3f6h). this counter uses a 1 second timebase. to enab le this timer, set f0 index 81h[0] = 1. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[0]. index 9ah-9bh floppy disk idle timer count register (r/w) reset value: 0000h 15:0 floppy disk idle timer count. this idle timer is used to determine when the flopp y disk drive is not in use so that it can be powered down. the 16-bit value programmed here represents the period of floppy disk drive inac tivity after which the sys- tem is alerted via an smi. the timer is aut omatically reloaded with the count value w henever an access occurs to the config- ured floppy drive?s data port (i/o port 3f5h or 375h). this counter uses a 1 second time base. to enable this timer, set f0 index 81h[1] = 1. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[1]. index 9ch-9dh parallel / serial idle timer count register (r/w) reset value: 0000h 15:0 parallel / serial idle timer count. this idle timer is used to determine when the parallel and serial ports are not in use so that the ports can be power managed. the 16-bit value programmed in this register represents the period of inactivity for these ports after which the system is alerted via an smi. the timer is automatically reloaded with the count value whenever an access occurs to the parallel (lpt) or serial (com) i/o address spaces. if the mouse is enabled on a serial port, that port is not considered here. this counter uses a 1 second timebase. to enab le this timer, set f0 index 81h[2] = 1. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[2]. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 231 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index 9eh-9fh keyboard / mouse idle timer count register (r/w) reset value: 0000h 15:0 keyboard / mouse idle timer count. this idle timer determines when the key board and mouse are not in use so that the lcd screen can be blanked. the 16-bit value pr ogrammed in this register represents t he period of inactivity for these ports after which the system is alerted via an smi. the timer is automatically reloaded with the count value whenever an access occurs to either the keyboard or mous e i/o address spaces (includi ng the mouse serial port address space when a mouse is enabled on a serial port.) this counter uses a 1 second time base. to enable this timer, set f0 index 81h[3] = 1. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[3]. index a0h-a1h user defined device 1 idle timer count register (r/w) reset value: 0000h 15:0 user defined device 1 (udef1) idle timer count. this idle timer determines when t he device configur ed as user defined device 1 (udef1) is not in use so that it can be power m anaged. the 16-bit value programmed in this register represents the period of inactivity for this device after which the syst em is alerted via an smi. the ti mer is automatically reloaded with the count value whenever an access occurs to memory or i/o address space configured in t he f0 index c0h (base address register) and f0 index cch (control register). this counter uses a 1 second time base. to enable this timer, set f0 index 81h[4] = 1. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[4]. index a2h-a3h user defined device 2 idle timer count register (r/w) reset value: 0000h 15:0 user defined device 2 (udef2) idle timer count. this idle timer determines when t he device configured as udef2 is not in use so that it can be power managed. the 16-bit value programm ed in this register represents the period of inactivity for this device after which the system is alerted via an smi. the timer is automatica lly reloaded with the count value whenever an access occurs to memory or i/o address space configured in the f0 index c4h (base address register) and f0 index cdh (control register). this counter uses a 1 second timebase. to enab le this timer, set f0 index 81h[5] = 1. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[5]. index a4h-a5h user defined device 3 idle timer count register (r/w) reset value: 0000h 15:0 user defined device 3 (udef3) idle timer count. this idle timer determines when t he device configured as udef3 is not in use so that it can be power managed. the 16-bit value programm ed in this register represents the period of inactivity for this device after which the system is alerted via an smi. the timer is automatica lly reloaded with the count value whenever an access occurs to memory or i/o address space configured in the udef3 base address register (f0 index c8h) and udef3 control register (f0 index ceh). this counter uses a 1 second timebase. to enab le this timer, set f0 index 81h[6] = 1. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[6]. index a6h-a7h video idle timer count register (r/w) reset value: 0000h 15:0 video idle timer count. this idle timer determines when the graphics subsystem has been idle as part of the suspend- determination algorithm. the 16-bit value pr ogrammed in this register represents th e period of video inactivity after which the system is alerted via an smi. the count in this timer is automatically reset at any access to the graphics controller space. this counter uses a 1 second timebase. to enab le this timer, set f0 index 81h[7] = 1. since the graphics controller is embedded in the gx1 module, video activity is communicated to the core logic module via the serial connection (pserial register, bit 0). the core logic module also detects accesses to standard vga space on pci (3bxh, 3cxh, 3dxh and a000h-b7ffh) if an external vga controller is being used. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 85h/f5h[7]. index a8h-a9h video overflow count register (r/w) reset value: 0000h 15:0 video overflow count. each time the video speedup counter is triggered, a 100 ms timer is started. if the 100 ms timer expires before the video speedup counter lapses, the video overfl ow count register increments and the 100 ms timer retrig- gers. software clears the overflow register when new evaluations are to begin. the count contained in th is register can be combined with other data to determine the type of video accesses present in the system. index aah-abh reserved reset value: 00h table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
232 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index ach-adh secondary hard disk idle timer count register (r/w) reset value: 0000h 15:0 secondary hard disk idle timer count. this idle timer is used to determine when the secondary hard disk is not in use so that it can be powered down. the 16-bit value programmed in this register represents the period of hard disk inactivity after which the system is alerted via an smi. t he timer is automatically reloaded with the count value whenever an access occurs to the configured hard disk?s data port (i/o port 1f0h or 170h). this counter uses a 1 second timebase. to enab le this timer, set f0 index 83h[7] = 1. top level smi status is reported at f1bar0+i/o offset 00h/02h[0]. second level smi status is reported at f0 index 86h/f6h[4]. index aeh cpu suspend command register (wo) reset value: 00h 7:0 software cpu suspend command. if bit 0 in the clock stop control register is set low (f0 index bch[0] = 0), a write to this register causes an internal su sp#/suspa# handshake with the gx1 module, placing the gx1 module in a low-power state. the actual data written is irrelevant. once in this state, any unmasked irq or smi releases the gx1 module halt con- dition. if f0 index bch[0] = 1, writing to this register invokes a fu ll system suspend. in this case, the internal susp_3v signal is asserted after the susp#/suspa# halt. upon a resume event, the pll delay programmed in the f0 index bch[7:4] is invoked, allowing the clock chip and gx1 modu le pll to stabilize before de-asserting susp#. index afh suspend notebook command register (wo) reset value: 00h 7:0 software cpu stop clock suspend. a write to this register causes a su sp#/suspa# handshake with the cpu, placing the gx1 module in a low-power state. following this handshake, the susp_3v signal is asserted. the susp_3v signal is intended to be used to stop all system clocks. upon a resume event, the internal susp_3v signal is de-asserted. after a slight delay, the core logic module de-asserts the susp# signal. once the clocks are stable, the gx1 module de-asserts suspa# and system operation resumes. index b0h-b3h reserved reset value: 00h index b4h floppy port 3f2h shadow register (ro) reset value: xxh 7:0 floppy port 3f2h shadow. last written value of i/o port 3f2h. requi red for support of fdc power on/off and 0v sus- pend/resume coherency. this register is a copy of an i/o register which cannot safely be directly read. the value in th is register is not deterministi c of when the register is being read. it is provided here to assist in a suspend-to-disk operation. index b5h floppy port 3f7h shadow register (ro) reset value: xxh 7:0 floppy port 3f7h shadow. last written value of i/o port 3f7h. requi red for support of fdc power on/off and 0v sus- pend/resume coherency. this register is a copy of an i/o register which cannot safely be directly read. the value in th is register is not deterministi c of when the register is being read. it is provided here to assist in a suspend-to-disk operation. index b6h floppy port 372h shadow register (ro) reset value: xxh 7:0 floppy port 372h shadow. last written value of i/o port 372h. required for support of fdc power on/off and 0v sus- pend/resume coherency. this register is a copy of an i/o register which cannot safely be directly read. the value in th is register is not deterministi c of when the register is being read. it is provided here to assist in a suspend-to-disk operation. index b7h floppy port 377h shadow register (ro) reset value: xxh 7:0 floppy port 377h shadow. last written value of i/o port 377h. required for support of fdc power on/off and 0v sus- pend/resume coherency. this register is a copy of an i/o register which cannot safely be directly read. the value in th is register is not deterministi c of when the register is being read. it is provided here to assist in a suspend-to-disk operation. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 233 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index b8h dma shadow register (ro) reset value: xxh 7:0 dma shadow. this 8-bit port sequences through the following list of shadowed dma controller registers. at power on, a pointer starts at the first register in the list and continuing through the other regi sters in subsequent reads according to th e read sequence. a write to this register re sets the read sequence to the first register . each shadow register in the sequence contains the last data written to that location. the read sequence for this register is: 1. dma channel 0 mode register 2. dma channel 1 mode register 3. dma channel 2 mode register 4. dma channel 3 mode register 5. dma channel 4 mode register 6. dma channel 5 mode register 7. dma channel 6 mode register 8. dma channel 7 mode register 9. dma channel mask register (bit 0 is channel 0 mask, etc.) 10. dma busy register (bit 0 or 1 means a dma occurred within last 1 ms, all other bits are 0) index b9h pic shadow register (ro) reset value: xxh 7:0 pic shadow. this 8-bit port sequences through the fo llowing list of shadowed interrupt controller registers. at power on, a pointer starts at the first register in the list and continuing through the other regi sters in subsequent reads according to th e read sequence. a write to this register re sets the read sequence to the first register . each shadow register in the sequence contains the last data written to that location. the read sequence for this register is: 1. pic1 icw1 2. pic1 icw2 3. pic1 icw3 4. pic1 icw4 - bits [7:5] of icw4 are always 0. 5. pic1 ocw2 - bits [6:3] of ocw2 are always 0 (see note). 6. pic1 ocw3 - bits [7:4] are 0 and bits [6:3] are 1. 7. pic2 icw1 8. pic2 icw2 9. pic2 icw3 10. pic2 icw4 - bits [7:5] of icw4 are always 0. 11. pic2 ocw2 - bits [6:3] of ocw2 are always 0 (see note). 12. pic2 ocw3 - bits [7:4] are 0 and bits [6:3] are 1. note: to restore ocw2 to the shadow register value, write the appropriate address twice. first with the shadow register value, then with the shadow register value ored with c0h. index bah pit shadow register (ro) reset value: xxh 7:0 pit shadow. this 8-bit port sequences through the following list of shadowed programmable interval timer registers. at power on, a pointer starts at the first register in the li st and continuing through the other registers in subsequent reads according to the read sequence. a write to th is register resets the read sequence to the first register. each shadow register in the sequence contains the last data written to that location. the read sequence for this register is: 1. counter 0 lsb (least significant byte) 2. counter 0 msb 3. counter 1 lsb 4. counter 1 msb 5. counter 2 lsb 6. counter 2 msb 7. counter 0 command word 8. counter 1 command word 9. counter 2 command word note: the lsb/msb of the count is the counter base value, not the current value. bits [7:6] of the command words are not used. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
234 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index bbh rtc index shadow register (ro) reset value: xxh 7:0 rtc index shadow. the rtc shadow register contains the last writte n value of the rtc index register (i/o port 070h). index bch clock stop control register (r/w) reset value: 00h 7:4 pll delay. the programmed value in this field sets the delay (in mi lliseconds) after a break event occurs before the internal susp# signal is de-asserted to the gx1 m odule. this delay is designe d to allow the clock chip and cpu pll to stabilize before starting execution. this delay is only invoked if the stp_clk bit was set. the 4-bit field allows va lues from 0 to 15 ms. 0000: 0 ms 0100: 4 ms 1000: 8 ms 1100: 12 ms 0001: 1 ms 0101: 5 ms 1001: 9 ms 1101: 13 ms 0010: 2 ms 0110: 6 ms 1010: 10 ms 1110: 14 ms 0011: 3 ms 0111: 7 ms 1011: 11 ms 1111: 15 ms 3:1 reserved. set to 0. 0 cpu clock stop. 0: normal internal susp#/suspa# handshake. 1: full system suspend. note: this register configures the core logi c module to support a 3v suspend mode. setting bit 0 causes the susp_3v signal to assert after the appropriate conditions, stopping the system clocks. a delay of 0-15 ms is programmable (bits [7:4]) to allow f or a delay for the clock chip and cpu pll to stabilize when an event resumes the system. a write to the cpu suspend command register (f0 index aeh) with bit 0 written as: 0: internal susp#/suspa# handshake occurs. the gx1 module is put into a low-power state, and the system clocks are not stopped. when a break/resume event occurs, it releases the cpu halt condition. 1: internal susp#/suspa# handshake occurs and the susp_3v signal is asserted, thus invoking a full system suspend (both gx1 module and system clocks are stopped). when a break event oc curs, the susp_3v signal is de-asserted, the pll delay programmed in bits [7:4] are invoked which allows the cloc k chip and gx1 module pll to stabilize before de-asserting the internal susp# signal. index bdh-bfh reserved reset value: 00h index c0h-c3h user defined device 1 base address register (r/w) reset value: 00000000h 31:0 user defined device 1 base address. this 32-bit register supports power management (trap and idle timer resources) for a pcmcia slot or some other device in the system. the va lue in this register is used as the address comparator for the device trap/timer logic. the device can be memo ry or i/o mapped (configured in f0 index cch). the core logic module cannot snoop addresses on the fast-pci bus unless it actually claims t he cycle. therefore, traps and idle timers cannot support power management of devices on the fast-pci bus. index c4h-c7h user defined device 2 base address register (r/w) reset value: 00000000h 31:0 user defined device 2 base address. this 32-bit register supports power management (trap and idle timer resources) for a pcmcia slot or some other device in the system. the va lue in this register is used as the address comparator for the device trap/timer logic. the device can be memo ry or i/o mapped (configured in f0 index cdh). the core logic module cannot snoop addresses on the fast-pci bus unless it actually claims t he cycle. therefore, traps and idle timers cannot support power management of devices on the fast-pci bus. index c8h-cbh user defined device 3 base address register (r/w) reset value: 00000000h 31:0 user defined device 3 base address. this 32-bit register supports power management (trap and idle timer resources) for a pcmcia slot or some other device in the system. the va lue in this register is used as the address comparator for the device trap/timer logic. the device can be memo ry or i/o mapped (configured in f0 index ceh). the core logic module cannot snoop addresses on the fast-pci bu s unless the it actually claims the cycle. therefore, traps and idle timers cannot support power management of devices on the fast-pci bus. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 235 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index cch user defined device 1 control register (r/w) reset value: 00h 7 memory or i/o mapped. determines how user defined device 1 is mapped. 0: i/o. 1: memory. 6:0 mask. if bit 7 = 0 (i/o): bit 6 0: disable write cycle tracking 1: enable write cycle tracking bit 5 0: disable read cycle tracking 1: enable read cycle tracking bits [4:0] mask for address bits a[4:0] if bit 7 = 1 (memory): bits [6:0] mask for address memory bits a[15:9] ( 512 bytes min. and 64 kb max.) a[8:0] are ignored. note: a "1" in a mask bit means that t he address bit is ignored for comparison. index cdh user defined device 2 control register (r/w) reset value: 00h 7 memory or i/o mapped. determines how user defined device 2 is mapped. 0: i/o 1: memory 6:0 mask. if bit 7 = 0 (i/o): bit 6 0: disable write cycle tracking 1: enable write cycle tracking bit 5 0: disable read cycle tracking 1: enable read cycle tracking bits [4:0] mask for address bits a[4:0] if bit 7 = 1 (memory): bits [6:0] mask for address memory bits a[15:9] ( 512 bytes min. and 64 kb max.) a[8:0] are ignored. note: a "1" in a mask bit means that t he address bit is ignored for comparison. index ceh user defined device 3 control register (r/w) reset value: 00h 7 memory or i/o mapped. determines how user defined device 3 is mapped. 0: i/o. 1: memory. 6:0 mask. if bit 7 = 0 (i/o): bit 6 0: disable write cycle tracking 1: enable write cycle tracking bit 5 0: disable read cycle tracking 1: enable read cycle tracking bits [4:0] mask for address bits a[4:0] if bit 7 = 1 (memory): bits [6:0] mask for address memory bits a[15:9] ( 512 bytes min. and 64 kb max.) a[8:0] are ignored. note: a "1" in a mask bit means that t he address bit is ignored for comparison. index cfh reserved reset value: 00h index d0h software smi register (wo) reset value: 00h 7:0 software smi. a write to this location generates an smi. the data writte n is irrelevant. this regi ster allows software entry into smm via normal bus access instructions. index d1h-ebh reserved reset value: 00h table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
236 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 index ech timer test register (r/w) reset value: 00h 7:0 timer test value. the timer test register is intended only for test and debug purposes. it is not intended for setting opera- tional timebases. for normal operation, never write to this register. index edh-f3h reserved reset value: 00h index f4h second level pme/smi status register 1 (rc) reset value: 00h the bits in this register c ontain second level status reporting. top level st atus is reported in f1bar0+i/o offset 00h/02h[0]. reading this register clears the status at both the second and top levels. a read-only ?mirror? version of th is register exists at f0 index 84h. if the va lue of the register must be read without clearin g the smi source (and consequently de -asserting smi), f0 index 84h can be read instead. 7:3 reserved. reads as 0. 2 gpwio2 smi status. indicates whether or not an smi was caused by a transition on the gpwio2 pin. 0: no. 1: yes. to enable smi generation: 1) ensure that gpwio2 is enabled as an input: f1bar1+i/o offset 15h[2] = 0. 2) set f1bar1+i/o offset 15h[6] = 1 to allow smi generation. 1 gpwio1 smi status. indicates whether or not an smi was caused by a transition on the gpwio1 pin. 0: no. 1: yes. to enable smi generation: 1) ensure that gpwio1 is enabled as an input: f1bar1+i/o offset 15h[1] = 0. 2) set f1bar1+i/o offset 15h[5] to 1 to allow smi generation. 0 gpwio0 smi status. indicates whether or not an smi was caused by a transition on the gpwio0 pin. 0: no 1: yes to enable smi generation: 1) ensure that gpwio0 is enabled as an input: f1bar1+i/o offset 15h[0] = 0. 2) set f1bar1+i/o offset 15h[4] to 1 to allow smi generation. index f5h second level pme/smi status register 2 (rc) reset value: 00h the bits in this register c ontain second level status reporting. top level st atus is reported in f1bar0+i/o offset 00h/02h[0]. reading this register clears the status at both the second and top levels. a read-only ?mirror? version of th is register exists at f0 index 85h. if the va lue of the register must be read without clearin g the smi source (and consequently de -asserting smi), f0 index 85h can be read instead. 7 video idle timer smi status. indicates whether or not an smi was caused by expiration of video idle timer count regis- ter, (f0 index a6h). 0: no. 1: yes. to enable smi generation, set f0 index 81h[7] = 1. 6 user defined device idle timer 3 (udef3) smi status. indicates whether or not an smi was caused by expiration of user defined device 3 (udef3) idle timer count register (f0 index a4h). 0: no. 1: yes. to enable smi generation, set f0 index 81h[6] = 1. 5 user defined device idle timer 2 (udef2) smi status. indicates whether or not an smi was caused by expiration of user defined device 2 (udef2) idle timer count register (f0 index a2h). 0: no. 1: yes. to enable smi generation, set f0 index 81h[5] = 1. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 237 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 4 user defined device idle timer 1 (udef1) smi status. indicates whether or not an smi was caused by expiration of user defined device 1 (udef1) idle timer count register (f0 index a0h). 0: no. 1: yes. to enable smi generation, set f0 index 81h[4] = 1. 3 keyboard/mouse idle timer smi status. indicates whether or not an smi was caused by expiration of keyboard/ mouse idle timer count register (f0 index 9eh). 0: no. 1: yes. to enable smi generation, set f0 index 81h[3] = 1. 2 parallel/serial idle timer smi status. indicates whether or not an smi was caused by expiration of parallel/serial port idle timer count register (f0 index 9ch). 0: no. 1: yes. to enable smi generation, set f0 index 81h[2] = 1. 1 floppy disk idle timer smi status. indicates whether or not an smi was caused by expiration of floppy disk idle timer count register (f0 index 9ah). 0: no. 1: yes. to enable smi generation, set f0 index 81h[1] = 1. 0 hard disk idle timer smi status. indicates whether or not an smi was caused by expiration of hard disk idle timer count register (f0 index 98h). 0: no. 1: yes. to enable smi generation, set f0 index 81h[0] = 1. index f6h second level pme/smi status register 3 (rc) reset value: 00h the bits in this register c ontain second level status reporting. top level st atus is reported in f1bar0+i/o offset 00h/02h[0]. reading this register clears the status at both the second and top levels. a read-only ?mirror? version of th is register exists at f0 index 86h. if the va lue of the register must be read without clearin g the smi source (and consequently de -asserting smi), f0 index 86h can be read instead. 7 video access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to the video i/o tr a p. 0: no. 1: yes. to enable smi generation, set f0 index 82h[7] = 1. 6 reserved. reads as 0. 5 secondary hard disk access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to the secondary hard disk. 0: no. 1: yes. to enable smi generation, set f0 index 83h[6] = 1. 4 secondary hard disk idle timer smi status. indicates whether or not an smi wa s caused by expiration of secondary hard disk idle timer count register (f0 index ach). 0: no. 1: yes. to enable smi generation, set f0 index 83h[7] = 1. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
238 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 3 keyboard/mouse access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to the keyboard or mouse. 0: no. 1: yes. to enable smi generation, set f0 index 82h[3] = 1. 2 parallel/serial access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to either the serial or parallel ports. 0: no. 1: yes. to enable smi generation, set f0 index 82h[2] =1. 1 floppy disk access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to the floppy disk. 0: no. 1: yes. to enable smi generation, set f0 index 82h[1] = 1. 0 primary hard disk access trap smi status. indicates whether or not an smi was caused by a trapped i/o access to the primary hard disk. 0: no. 1: yes. to enable smi generation, set f0 index 82h[0] = 1. index f7h second level pme/smi status register 4 (rc) reset value: 00h the bits in this register c ontain second level status reporting. top level st atus is reported in f1bar0+i/o offset 00h/02h[0]. reading this register clears the status at both the second and top levels except for bit 7 which has a third level of status re porting at f0bar0+i/o 0ch/1ch. a read-only ?mirror? version of th is register exists at f0 index 87h. if the va lue of the register must be read without clearin g the smi source (and consequently de -asserting smi), f0 index 87h can be read instead. 7 gpio event smi status (read only, read does not clear). indicates whether or not an smi was caused by a transition of any of the gpios (gpio47- gpio32 and gpio15-gpio0). 0: no. 1: yes. to enable smi generation, set f1bar1+i/o offset 0ch[0] = 0. f0bar0+i/o offset 08h/18h selects which gpios are enabled to generate a pme and setting f1bar1+i/o offset 0ch[0] = 0 enables the pme to generate an smi. in addition, the selected gpio must be enabled as an input (f0bar0+i/o offset 20h and 24h). the next level (third level) of smi status is at f0bar0+i/o 0ch/1ch. 6 thermal override smi status. indicates whether or not an smi was caused by an assertion of the thrm#. 0: no. 1: yes. to enable smi generation set f0 index 83h[4] = 1. 5:4 reserved. read as 0. 3 sio pwureq smi status. indicates whether or not an smi was caused by a power-up event from the sio. 0: no. 1: yes. a power-up event is defined as any of the following events/activities: ?ri2# ?sdata_in2 ? irrx1 (ceir) to enable smi generation, set f1bar1+i/o offset 0ch[0] = 0. table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
amd geode? sc3200 processor data book 239 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 2 codec sdata_in smi status. indicates whether or not an smi was ca used by ac97 codec producing a positive edge on sdata_in. 0: no. 1: yes. to enable smi generation, set f0 index 80h[5] = 1. 1 rtc alarm (irq8#) smi status. indicates whether or not an smi was caused by an rtc interrupt. 0: no. 1: yes. this smi event can only occur while in 3v suspend and an rtc interrupt occurs and f1bar1+i/o offset 0ch[0] = 0. 0 acpi timer smi status. indicates whether or not an smi was caused by an acpi timer (f1bar0+i/o offset 1ch or f1bar1+i/o offset 1ch) msb toggle. 0: no. 1: yes. to enable smi generation, set f0 index 83h[5] = 1. index f8h-ffh reserved reset value: 00h table 6-29. f0: pci header/bridge configuration registers for gpio and lpc support (continued) bit description
240 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 6.4.1.1 gpio supp ort registers f0 index 10h, base address register 0 (f0bar0) points to the base address of where the gpio runtime and configu- ration registers are located. table 6-29 gives the bit for- mats of i/o mapped registers accessed through f0bar0. table 6-30. f0bar0+i/o offset: gpio configuration registers bit description offset 00h-03h gpdo0 ? gpio data out 0 register (r/w) reset value: ffffffffh 31:0 gpio data out. bits [31:0] of this register co rrespond to gpio31-gpio0 signals, respec tively. the value of each bit deter- mines the value driven on the corresponding gpio signal when its output buffer is enab led. writing to the bit latches the written data unless the bit is locked by the gpio configurat ion register lock bit (f0bar0+ i/o offset 24h[3]). reading the bit returns the value, regardless of the signal value and configuration. 0: corresponding gpio signal is dr iven to low when output enabled. 1: corresponding gpio signal is dr iven or released to high (according to buffer type and static pull-up selection) when out- put is enabled. offset 04h-07h gpdi0 ? gpio data in 0 register (ro) reset value: ffffffffh 31:0 gpio data in. bits [31:0] of this register correspond to gpio31-gpio0 signals, res pectively. reading each bit returns the value of the corresponding gpio signal, regardless of the si gnal configuration and the gpdo0 register (f0bar0+i/o offset 00h) value. writes to this r egister are ignored. 0: corresponding gpio si gnal level is low. 1: corresponding gpio si gnal level is high. offset 08h-0bh gpien0 ? gpio interrupt enable 0 register (r/w) reset value: 00000000h 31:16 reserved. must be set to 0. 15:0 gpio power management event (pme) enable. bits [15:0] correspond to gpio15-gp io0 signals, respectively. each bit allows pme generation by t he corresponding gpio signal. 0: disable pme generation. 1: enable pme generation. notes: 1) all of the enabled gpio pmes are alwa ys reported at f1bar1+i/o offset 10h[3]. 2) any enabled gpio pme can be selected to generate an sci or smi at f1bar1+i/o offset 0ch[0]. if sci is selected, then the individually selected gpio pmes are globally enabled for sci generation at f1bar1+i/o offset 12h[3] and the status is reported at f1bar1+i/o offset 10h[3]. if smi is selected, the individually selected gpio pmes generate an smi and the status is reported at f1bar0+i/o offset 00h/02h[0]. offset 0ch-0fh gpst0 ? gpio status 0 register (r/w1c) reset value: 00000000h 31:16 reserved. must be set to 0. 15:0 gpio status . bits [15:0] correspond to gpio15-gp io0 signals, respectively. each bi t reports a 1 when hardware detects the edge (rising/falling on the gpio signal) that is programmed in f0bar0+i/o offset 24h[5]. if the corresponding bit in f0bar0+i/o offset 08h is set, this edge generates a pme. 0: no active edge detected since the bit was last cleared. 1: active edge detected. writing 1 to the a status bit clears it to 0. this is the third level of smi status reporting to the second level at f0 index 87h/f7h[7] and the top level at f1bar0+i/o offset 00h/02h[0]. clearing the third leve l also clears the second and top levels. this is the second level of sci status reporting to the t op level at f1bar1+offset 10h[3]. the status must be cleared at both the this level and the top level (i.e., the top level is not automatically cleared when a bit in this register is cleared) .
amd geode? sc3200 processor data book 241 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 offset 10h-13h gpdo1 ? gpio data out 1 register (r/w) reset value: ffffffffh 31:0 gpio data out. bits [31:0] of this register correspond to gpio 63-gpio32 signals, respective ly. the value of each bit determines the value driven on the correspondi ng gpio signal when its output buffer is enabled. writing to the bit latches the written data unless the bit is locked by the gpio confi guration register lock bit (f0b ar0+i/o offset 24h[3]). reading the bit returns the value, regardless of the signal value and configuration. 0: corresponding gpio signal driven to low when output enabled. 1: corresponding gpio signal driven or releas ed to high (according to buffer type and st atic pull-up selection) when output enabled. offset 14h-17h gpdi1 ? gpio data in 1 register (ro) reset value: ffffffffh 31:0 gpio data in. bits [31:0] of this register correspond to gpio63-gp io32 signals, respectively. r eading each bit returns the value of the corresponding gpio signal, regardless of the si gnal configuration and the gpdo1 register (f0bar0+i/o offset 10h) value. writes to th is register are ignored. 0: corresponding gpio signal level low. 1: corresponding gpio signal level high. offset 18h-1bh gpien1 ? gpio interrupt enable 1 register (r/w) reset value: 00000000h 31:16 reserved. must be set to 0. 15:0 gpio power management event (pme) enable. bits [15:0] of this register correspond to gpio47-gpio32 signals, respectively. each bit allows pme gener ation by the corresponding gpio signal. 0: disable pme generation. 1: enable pme generation. notes: 1) all of the enabled gpio pmes are alwa ys reported at f1bar1+i/o offset 10h[3]. 2) any enabled gpio pme can be selected to generate an sci or smi at f1bar1+i/o offset 0ch[0]. if sci is selected, the individually selected gpio pmes are globally enabled for sci generation at f1bar1+i/ o offset 12h[3] and the status is reported at f1bar1+i/o offset 10h[3]. if smi is selected, the individually selected gpio pmes generate an smi and the status is reported at f1bar0+i/o offset 00h/02h[0]. offset 1ch-1fh gpst1 ? gpio status 1 register (r/w1c) reset value: 00000000h 31:16 reserved. must be set to 0. 15:0 gpio status . bits [15:0] correspond to gpio47 -gpio32 signals, respecti vely. each bit reports a 1 when hardware detects the edge (rising/falling on the gpio signal) that is programmed in f0bar0+i/o offset 24h[5]. if the corresponding bit in f0bar0+i/o offset 18h is set, this edge generates a pme. 0: no active edge detected since the bit was last cleared. 1: active edge detected. writing 1 to the a status bit clears it to 0. this is the third level of smi status reporting to the second level at f0 index 87h/f7h[7] and the top level at f1bar0+i/o offset 00h/02h[0]. clearing the third leve l also clears the second and top levels. this is the second level of sci status reporting to the t op level at f1bar1+offset 10h[3]. the status must be cleared at both the this level and the top level (i.e., the top level is not automatically cleared when a bit in this register is cleared) . offset 20h-23h gpio signal configuration select register (r/w) reset value: 00000000h 31:6 reserved. must be set to 0. table 6-30. f0bar0+i/o offset: gpio configuration registers (continued) bit description
242 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 5:0 signal select. selects the gpio signal to be configured in the bank se lected via bit 5 setting (i.e., bank 0 or bank 1). see table 4-2 on page 88 for gpio ball muxing options. gpios without an associated ball number are not available externally. bank 0 000000 = gpio0 (ebga: h1 / tepbga: d11) 010000 = gpio16 (ebga: al15 / tepbga: v31) 000001 = gpio1 (ebga: h2, al12 / tepbga: d10, n30) 010001 = gpio17 (ebga: j4 / tepbga: a10) 000010 = gpio2 010010 = gpio18 (ebga: a28 / tepbga: ag1) 000011 = gpio3 010011 = gpio19 (ebga: h4 / tepbga: c9) 000100 = gpio4 010100 = gpio20 (ebga: h3, aj13 / tepbga: a9, n31) 000101 = gpio5 010101 = gpio21 000110 = gpio6 (ebga: ah3 / tepbga: d28) 010110 = gpio22 000111 = gpio7 (ebga: ah4 / tepbga: c30) 010111 = gpio23 001000 = gpio8 (ebga: aj2 / tepbga: c31) 011000 = gpio24 001001 = gpio9 (ebga: ag4 / tepbga: c28) 011001 = gpio25 001010 = gpio10 (ebga: aj1 / tepbga: b29) 011010 = gpio26 001011 = gpio11 (ebga: h30 / tepbga: aj8) 011011 = gpio27 001100 = gpio12 (ebga: aj12 / tepbga: n29) 011100 = gpio28 001101 = gpio13 (ebga: al11 / tepbga: m29) 011101 = gpio29 001110 = gpio14 (ebga: f1 / tepbga: d9) 011110 = gpio30 001111 = gpio15 (ebga: g3 / tepbga: a8) 011111 = gpio31 bank 1 100000 = gpio32 (ebga: aj11 / tepbga: m28) 110000 = gpio48 100001 = gpio33 (ebga: al10 / tepbga: l31) 110001 = gpio49 100010 = gpio34 (ebga: ak10 / tepbga: l30) 110010 = gpio50 100011 = gpio35 (ebga: aj10 / tepbga: l29) 110011 = gpio51 100100 = gpio36 (ebga: al9 / tepbga: l28) 110100 = gpio52 100101 = gpio37 (ebga: ak9 / tepbga: k31) 110101 = gpio53 100110 = gpio38 (ebga: aj9 / tepbga: k28) 110110 = gpio54 100111 = gpio39 (ebga: al8 / tepbga: j31) 110111 = gpio55 101000 = gpio40 (ebga: a21 / tepbga: y3) 111000 = gpio56 101001 = gpio41 (ebga: c19 / tepbga: w4) 111001 = gpio57 101010 = gpio42 111010 = gpio58 101011 = gpio43 111011 = gpio59 101100 = gpio44 111100 = gpio60 101101 = gpio45 111101 = gpio61 101110 = gpio46 111110 = gpio62 101111 = gpio47 111111 = gpio63 (note) note: gpio63 can be used to generate the pwrbtn# input signal . see pwrbtn# signal description in section 3.4.15 "power management interface signals" on page 80. offset 24h-27h gpio signal configurat ion access register (r/w) reset value: 00000044h this register is used to indica te configuration for the gpio signal that is se lected in the gpio signal configuration select re gister (above). note: pme debouncing, polarity, and edge/level configuration is only applicable on gpio0-gpio15 signals (bank 0 = 00000 to 01111) and on gpio32-gpio47 signals (bank 1 settings of 00000 to 01111). the remaining gpios (gpio16-gpio31 and gpio48-gpio63) can not generate pmes, therefor e these bits have no function and read 0. 31:7 reserved. must be set to 0. 6 pme debounce enable. enables/disables irq debounce (debounce period = 16 ms). 0: disable. 1: enable. (default). see the note in the description of this register for more information about the default value of this bit. 5 pme polarity. selects the polarity of the signal that issues a pme fr om the selected gpio signal (falling/low or rising/high). 0: falling edge or low level input. (default) 1: rising edge or high level input. see the note in the description of this register for more information about the default value of this bit. table 6-30. f0bar0+i/o offset: gpio configuration registers (continued) bit description
amd geode? sc3200 processor data book 243 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 4 pme edge/level select. selects the type (edge or level) of the signal that issues a pme from the selected gpio signal. 0: edge input. (default) 1: level input. for normal operation, always set this bit to 0 (edge input). erratic system behavior results if this bit is set to 1. see the note in the description of this register for more information about the default value of this bit. 3 lock. this bit locks the selected gpio signal. once this bit is set to 1 by software, it can only be cleared to 0 by power on reset or by watchdog reset. 0: no effect. (default) 1: direction, output type, pull-up and output value locked. 2 pull-up control. enables/disables the internal pu ll-up capability of the selected gpio signal. it supports open-drain output signals with internal pull -ups and ttl input signals. 0: disable. 1: enable. (default) bits [1:0] of this register must = 01 for this bit to have effect. 1 output type. controls the output buffer type (open-drain or push-pull) of t he selected gpio signal. 0: open-drain. (default) 1: push-pull. bit 0 of this register must be set to 1 for this bit to have effect. 0 output enable. indicates the gpio signal output state. it has no effect on input. 0: tri-state - setting for gpio to fu nction as an input only. (default) 1: output enabled. offset 28h-2bh gpio reset contro l register (r/w) reset value: 00000000h 31:1 reserved. must be set to 0. 0 gpio reset. reset the gpio logic. 0: disable. 1: enable. write 0 to clear. this bit is level-sensitive and must be cleared after the re set is enabled (normal operation requires this bit to be 0). table 6-30. f0bar0+i/o offset: gpio configuration registers (continued) bit description
244 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 6.4.1.2 lpc support registers f0 index 14h, base address register 1 (f0bar1) points to the base address of the regist er space that contains the configuration registers for lpc support. table 6-31 gives the bit formats of the i/o mapped registers accessed through f0bar1. the lpc interface supports all features described in the lpc bus specification 1.0, with the following exceptions: only 8- or 16-bit dma, depending on channel number. does not support the optional larger transfer sizes. only one external drq pin. table 6-31. f0bar1+i/o offset: lpc interface configuration registers bit description offset 00h-03h serirq_src ? serial irq source register (r/w) reset value: 00000000h note: some signals require additional programming to make them external ly accessible. see table 4-2 "multiplexing, interrupt selec- tion, and base address registers" on page 88 for pin multip lexing details and table 3-6 "strap options" on page 58 for lpc_rom strap information. 31:21 reserved. 20 intd source. selects the interface source of the intd# signal. 0: pci - intd# (ebga ball b22; tepbga ball aa2). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 19 intc source. selects the interface source of the intc# signal. 0: pci - intc# (ebga ball h4; tepbga ball c9). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 18 intb source. selects the interface source of the intb# signal. 0: pci - intb# (ebga ball af1; tepbga ball c26). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 17 inta source. selects the interface source of the inta# signal. 0: pci - inta# (ebga ball ae3; tepbga ball d26). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 16 reserved. set to 0. 15 irq15 source. selects the interface source of the irq15 signal. 0: isa - irq15 (ebga ball h30; tepbga ball aj8). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 14 irq14 source. selects the interface source of the irq14 signal. 0: isa - irq14 (ebga ball d25; tepbga ball af1). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 13 irq13 source. selects the interface source of the internal irq13 signal. 0: isa - irq13 internal signal. (an input from the cpu indica ting that a floating point erro r has been detected and that inter- nal intr should be asserted.) 1: lpc - serirq (ebga ball al8; tepbga ball j31). 12 irq12 source. selects the interface source of the irq12 signal. 0: isa - irq12 (unavailable externally). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 11 irq11 source. selects the interface source of the irq11 signal. 0: isa - irq11 (unavailable externally). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 10 irq10 source. selects the interface source of the irq10 signal. 0: isa - irq10 (unavailable externally). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 9 irq9 source. selects the interface source of the irq9 signal. 0: isa - irq9 (ebga ball c22; tepbga ball aa3). 1: lpc - serirq (ebga ball al8; tepbga ball j31).
amd geode? sc3200 processor data book 245 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 8 irq8# source. selects the interface source of the irq8# signal. 0: isa - irq8# internal signal. (connected to internal rtc.) 1: lpc - serirq (ebga ball al8; tepbga ball j31). 7 irq7 source. selects the interface source of the irq7 signal. 0: isa - irq7 (unavailable externally). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 6 irq6 source. selects the interface source of the irq6 signal. 0: isa - irq6 (unavailable externally). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 5 irq5 source. selects the interface source of the irq5 signal. 0: isa - irq5 (unavailable externally). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 4 irq4 source. selects the interface source of the irq4 signal. 0: isa - irq4 (unavailable externally). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 3 irq3 source. selects the interface source of the irq3 signal. 0: isa - irq3 (unavailable externally). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 2 reserved. must be set to 0. 1 irq1 source. selects the interface source of the irq1 signal. 0: isa - irq1 (unavailable externally). 1: lpc - serirq (ebga ball al8; tepbga ball j31). 0 irq0 source. selects the interface source of the irq0 signal. 0: isa - irq0 internal signal. (connected to out0, system timer, of the internal 8254 pit.) 1: lpc - serirq (ebga ball al8; tepbga ball j31). offset 04h-07h serirq_lvl ? serial irq le vel control register (r/w) reset value: 00000000h 31:21 reserved. 20 intd# polarity. if lpc is selected as the interface source for intd# (f 0bar1+i/o offset 00h[20] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 19 intc# polarity. if lpc is selected as the interface source for intc# (f 0bar1+i/o offset 00h[19] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 18 intb# polarity. if lpc is selected as the interface source for intb# (f0bar1+i/o offset 00h[18] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 17 inta# polarity. if lpc is selected as the interface source for inta# (f0bar1+i/o offset 00h[17] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 16 reserved. must be set to 0. 15 irq15 polarity. if lpc is selected as the interface source for irq15 (f0bar1+i/o offset 00h[15] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. table 6-31. f0bar1+i/o offset: lpc interface configuration registers (continued) bit description
246 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 14 irq14 polarity. if lpc is selected as the interface source for irq14 (f0bar1+i/o offset 00h[14] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 13 irq13 polarity. if lpc is selected as the interface source for irq13 (f0bar1+i/o offset 00h[13] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 12 irq12 polarity. if lpc is selected as the interface source for irq12 (f0bar1+i/o offset 00h[12] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 11 irq11 polarity. if lpc is selected as the interface source for irq11 (f0bar1+i/o offset 00h[11] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 10 irq10 polarity. if lpc is selected as the interface source for irq10 (f0bar1+i/o offset 00h[10] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 9 irq9 polarity. if lpc is selected as the interface source for irq9 (f0bar1+i/o offset 00h[9] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 8 irq8# polarity. if lpc is selected as the interface source for irq8# (f0bar1+i/o offset 00h[8] = 1) , this bit allows signal polarity selection. 0: active high. 1: active low. 7 irq7 polarity. if lpc is selected as the interface source for irq7 (f0bar1+i/o offset 00h[7] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 6 irq6 polarity. if lpc is selected as the interface source for irq6 (f0bar1+i/o offset 00h[6] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 5 irq5 polarity. if lpc is selected as the interface source for irq5 (f0bar1+i/o offset 00h[5] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 4 irq4 polarity. if lpc is selected as the interface source for irq4 (f0bar1+i/o offset 00h[4] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 3 irq3 polarity. if lpc is selected as the interface source for irq3 (f0bar1+i/o offset 00h[3] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. table 6-31. f0bar1+i/o offset: lpc interface configuration registers (continued) bit description
amd geode? sc3200 processor data book 247 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 2 smi# polarity. this bit allows signal polarity se lection of the smi# generated from lpc. 0: active high. 1: active low. 1 irq1 polarity. if lpc is selected as the interface source for irq1 (f0bar1+i/o offset 00h[1] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. 0 irq0 polarity. if lpc is selected as the interface source for irq0 (f0bar1+i/o offset 00h[0] = 1), this bit allows signal polarity selection. 0: active high. 1: active low. offset 08h-0bh serirq_cnt ? serial ir q control register (r/w) reset value: 00000000h 31:8 reserved. 7 serial irq enable. 0: disable. 1: enable. 6 serial irq interface mode. 0: continuous. 1: quiet. 5:2 number of irq data frames. 0000: 17 frames 0100: 21 frames 1000: 25 frames 1100: 29 frames 0001: 18 frames 0101: 22 frames 1001: 26 frames 1101: 30 frames 0010: 19 frames 0110: 23 frames 1010: 27 frames 1110: 31 frames 0011: 20 frames 0111: 24 frames 1011: 28 frames 1111: 32 frames 1:0 start frame pulse width. 00: 4 clocks 01: 6 clocks 10: 8 clocks 11: reserved offset 0ch-0fh drq_src ? drq sour ce register (r/w) reset value: 00000000h note: drqx are internal signals between the core logic and super i/o modules. some signals requi re additional programming to make them externally accessible. see table 4-2 "multiplexing, interrupt selection, and base address registers" on page 88 for pin multiplexing details and table 3-6 "strap options" on page 58 for lpc_rom strap information. 31:8 reserved. 7 drq7 source. selects the interface source of the drq7 signal. 0: isa - drq7 (unavailable externally). 1: lpc - ldrq# (ebga ball al9; tepbga ball l28). 6 drq6 source. selects the interface source of the drq6 signal. 0: isa - drq6 (unavailable externally). 1: lpc - ldrq# (ebga ball al9; tepbga ball l28). 5 drq5 source. selects the interface source of the drq5 signal. 0: isa - drq5 (unavailable externally). 1: lpc - ldrq# (ebga ball al9; tepbga ball l28). 4 lpc bm0 cycles. allow lpc bus master 0 cycles. 0: enable. 1: disable. 3 drq3 source. selects the interface source of the drq3 signal. 0: isa - drq3 (unavailable externally). 1: lpc - ldrq# (ebga ball al9; tepbga ball l28). table 6-31. f0bar1+i/o offset: lpc interface configuration registers (continued) bit description
248 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 2 drq2 source. selects the interface source of the drq2 signal. 0: isa - drq2 (unavailable externally). 1: lpc - ldrq# (ebga ball al9; tepbga ball l28). 1 drq1 source. selects the interface source of the drq1 signal. 0: isa - drq1 (unavailable externally). 1: lpc - ldrq# (ebga ball al9; tepbga ball l28). 0 drq0 source. selects the interface source of the drq0 signal. 0: isa - drq0 (unavailable externally). 1: lpc - ldrq# (ebga ball al9; tepbga ball l28). offset 10h-13h lad_en ? lpc address en able register (r/w) reset value: 00000000h 31:18 reserved. 17 lpc rtc. rtc addresses i/o ports 070h-073h. see bit 16 for decode. 16 lpc/isa default mapping. works in conjunction with bits 17 and [14:0] of this register to enable mapping of specific peripherals to lpc or internal isa interfaces. if bit [x] = 0 and bit 16 = 0 then: transaction routed to internal isa bus. if bit [x] = 0 and bit 16 = 1 then: transaction routed to lpc interface. if bit [x] = 1 and bit 16 = 0 then: transaction routed to lpc interface. if bit [x] = 1 and bit 16 = 1 then: transaction routed to internal isa bus. bit [x] is defined as bits 17 and [14:0]. 15 lpc rom addressing. depends upon f0 index 52h[2,0]. 0: disable. 1: enable. 14 lpc alternate superi/o addressing. alternate superi/o control addresse s 4eh-4fh. see bit 16 for decode. 13 lpc superi/o addressing. superi/o control addresses i/o ports 2eh-2fh. see bit 16 for decode. note: this bit should not be routed to lpc when using the inte rnal superi/o module and if io_siocfg_in (f5bar0+i/o offset 00h[26:25]) = 10. 12 lpc ad-lib addressing. ad-lib addresses i/o ports 388h-389h. see bit 16 for decode. 11 lpc acpi addressing. acpi microcontroller addresses i/o ports 62h and 66h. see bit 16 for decode. 10 lpc keyboard controller addressing. kbc addresses i/o ports 60h and 64h. note: if this bit = 0 and bit 16 = 1, then f0 index 5ah[1] must be written 0. 9 lpc wide generic addressing. wide generic addresses. see bit 16 for decode. address selection made via f0bar1+i/o offset 18h[15:9] note: the selected range must not overlap any address range t hat is positively decoded by f0bar1+i/o offset 10h bits [17], [14:10], and [8:0]. 8 lpc game port 1 addressing. game port 1 addresses. see bit 16 for decode. address selection made via f0bar1+i/o offset 14h[22:19] 7 lpc game port 0 addressing. game port 0 addresses. see bit 16 for decode. address selection made via f0bar1+i/o offset 14h[18:15]. 6 lpc floppy disk controller addressing. fdc addresses. see bit 16 for decode. address selection made via f0bar1+i/o offset 14h[14] 5 lpc microsoft sound system (mss) addressing. mss addresses. see bit 16 for decode. address selection made via f0bar1+i/o offset 14h[13:12]. 4 lpc midi addressing. midi addresses. see bit 16 for decode. address selection made via f0bar1+i/o offset 14h[11:10]. 3 lpc audio addressing. audio addresses. see bit 16 for decode. address selection made via f0bar1+i/o offset 14h[9:8]. 2 lpc serial port 1 addressing. serial port 1 addresses. see bit 16 for decode. address selection made via f0bar1+i/o offset 14h[7:5]. table 6-31. f0bar1+i/o offset: lpc interface configuration registers (continued) bit description
amd geode? sc3200 processor data book 249 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 1 lpc serial port 0 addressing. serial port 0 addresses. see bit 16 for decode. address selection made via f0bar1+i/o offset 14h[4:2]. 0 lpc parallel port addressing. parallel port addresses. see bit 16 for decode. address selection made via f0bar1+i/o offset 14h[1:0]. offset 14h-17h lad_d0 ? lpc address d ecode 0 register (r/w) reset value: 00080020h 31:23 reserved. 22:19 lpc game port 1 address select. selects i/o port: 0000: 200h 0100: 204h 1000: 208h 1100: 20ch 0001: 201h 0101: 205h 1001: 209h 1101: 20dh 0010: 202h 0110: 206h 1010: 20ah 1110: 20eh 0011: 203h 0111: 207h 1011: 20bh 1111: 20fh selected address range is enabled via f0bar1+i/o offset 10h[8]. 18:15 lpc game port 0 address select. selects i/o port: 0000: 200h 0100: 204h 1000: 208h 1100: 20ch 0001: 201h 0101: 205h 1001: 209h 1101: 20dh 0010: 202h 0110: 206h 1010: 20ah 1110: 20eh 0011: 203h 0111: 207h 1011: 20bh 1111: 20fh selected address range is enabled via f0bar1+i/o offset 10h[7]. 14 lpc floppy disk controller address select. selects i/o port: 0: 3f0h-3f7h. 1: 370h-377h. selected address range is enabled via f0bar1+i/o offset 10h[6]. 13:12 lpc microsoft sound system (mss) address select. selects i/o port: 00: 530h-537h 10: e80h-e87h 01: 604h-60bh 11: f40h-f47h selected address range is enabled via f0bar1+i/o offset 10h[5]. 11:10 lpc midi address select. selects i/o port: 00: 300h-301h 10: 320h-321h 01: 310h-311h 11: 330h-331h selected address range is enabled via f0bar1+i/o offset 10h[4]. 9:8 lpc audio address select. selects i/o port: 00: 220h-233h 10: 260h-273h 01: 240h-253h 11: 280h-293h selected address range is enabled via f0bar1+i/o offset 10h[3]. 7:5 lpc serial port 1 address select. selects i/o port: 000: 3f8h-3ffh 010: 220h-227h 100: 238h-23fh 110: 338h-33fh 001: 2f8h-2ffh 011: 228h-22fh 101: 2e8h-2efh 111: 3e8h-3efh selected address range is enabled via f0bar1+i/o offset 10h[2]. 4:2 lpc serial port 0 address select. selects i/o port: 000: 3f8h-3ffh 010: 220h-227h 100: 238h-23fh 110: 338h-33fh 001: 2f8h-2ffh 011: 228h-22fh 101: 2e8h-2efh 111: 3e8h-3efh selected address range is enabled via f0bar1+i/o offset 10h[1]. 1:0 lpc parallel port address select. selects i/o port: 00: 378h-37fh (+778h-77fh for ecp) 01: 278h- 27fh (+678h-67fh for ecp) (note) 10: 3bch-3bfh (+7bch-7bfh for ecp) 11: reserved selected address range is enabled via f0bar1+i/o offset 10h[0]. note: 279h is read only, writes are forwarded to isa for pnp. table 6-31. f0bar1+i/o offset: lpc interface configuration registers (continued) bit description
250 amd geode? sc3200 processor data book core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 offset 18h-1bh lad_d1 ? lpc address d ecode 1 register (r/w) reset value: 00000000h 31:16 reserved. must be set to 0. 15:9 wide generic base address select. defines a 512 byte space. can be mapped anywhere in the 64 kb i/o space. ac97 and other configuration regist ers are expected to be mapped to this rang e. it is wide enough to allow many unforeseen devices to be supported. enabled at f0bar1+i/o offset 10h[9]. note: the selected range must not overlap any address range t hat is positively decoded by f0bar1+i/o offset 10h bits [17], [14:10], and [8:0]. 8:0 reserved. must be set to 0. offset 1ch-1fh lpc_err_smi ? lpc erro r smi register (r/w) reset value: 00000080h 31:12 reserved. must be set to 0. 11 lpcpd# override enable. determines how lpcpd# output is controlled. 0: acpi logic. 1: lpcpd# override value bit (bit 10 of this register). 10 lpcpd# override value. selects value of lpcpd# output if bi t 11 of this register is set to 1. 0: power down sequence. 1: normal power. 9 smi serial irq enable. allows serial irq to generate an smi. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 02h[3]. second level status is reported at bit 6 of this register. 8 smi configuration for lpc error enable. allows lpc errors to generate an smi. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 02h[3]. second level status is reported at bit 5 of this register. 7 lpcpd# pin status. (read only) reflects the current value of the lpcpd# output signal. 6 smi source is serial irq. indicates whether or not an smi was generated by an serirq. 0: no. 1: yes. write 1 to clear. to enable smi generation, set bit 9 of this register to 1. this is the second level of status reporting. the top level status is reported in f1bar0+i/o offset 02h[3]. writing a 1 to this bit also clears the top level stat us bit as long as bit 5 of this register is cleared. 5 lpc error status. indicates whether or not an smi was generated by an error that occurred on lpc. 0: no. 1: yes. write 1 to clear. to enable smi generation, set bit 8 of this register to 1. this is the second level of status reporting. the top level status is reported in f1bar0+i/o offset 02h[3]. writing a 1 to this bit also clears the top level stat us bit as long as bit 6 of this register is cleared. 4 lpc multiple errors status. indicates whether or not multiple errors have occurred on lpc. 0: no. 1: yes. write 1 to clear. table 6-31. f0bar1+i/o offset: lpc interface configuration registers (continued) bit description
amd geode? sc3200 processor data book 251 core logic module - bridge, gpio, and lpc registers - function 0 revision 5.1 3 lpc timeout error status. indicates whether or not an error was generated by a timeout on lpc. 0: no. 1: yes. write 1 to clear. 2 lpc error write status. indicates whether or not an error was generated during a write operation on lpc. 0: no. 1: yes. write 1 to clear. 1 lpc error dma status. indicates whether or not an error was generated during a dma operation on lpc. 0: no. 1: yes. write 1 to clear. 0 lpc error memory status. indicates whether or not an error was generated during a memory operation on lpc. 0: no. 1: yes. write 1 to clear. offset 20h-23h lpc_err_add ? lpc error address register (ro) reset value: 00000000h 31:0 lpc error address. table 6-31. f0bar1+i/o offset: lpc interface configuration registers (continued) bit description
252 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 6.4.2 smi status and acpi registers - function 1 the register space designated as function 1 (f1) is used to configure the pci portion of support hardware for the smi status and acpi support registers. the bit formats for the pci header registers are given in table 6-32. located in the pci header registers of f1 are two base address registers (f1barx) used for pointing to the regis- ter spaces designated for smi status and acpi support, described later in this section. table 6-32. f1: pci header registers for smi status and acpi support bit description index 00h-01h vendor identification register (ro) reset value: 100bh index 02h-03h device identification register (ro) reset value: 0501h index 04h-05h pci command register (r/w) reset value: 0000h 15:1 reserved. (read only) 0 i/o space. allow the core logic module to res pond to i/o cycles from the pci bus. 0: disable. 1: enable. this bit must be enabled to access i/o offsets through f1bar0 and f1bar1 (see f1 index 10h and 40h). index 06h-07h pci status register (ro) reset value: 0280h index 08h device revision id register (ro) reset value: 00h index 09h-0bh pci class code register (ro) reset value: 068000h index 0ch pci cache line size register (ro) reset value: 00h index 0dh pci latency timer register (ro) reset value: 00h index 0eh pci header type (ro) reset value: 00h index 0fh pci bist register (ro) reset value: 00h index 10h-13h base address register 0 - f1bar0 (r/w) reset value: 00000001h this register allows access to i/o mapped smi status related registers. bits [7:0 ] are read only (0000 0001), indicating a 256- byte i/o address range. refer to table 6-33 on page 253 for bit form ats and reset values of the smi status registers. 31:8 smi status base address. 7:0 address range. (read only) index 14h-2bh reserved reset value: 00h index 2ch-2dh subsystem vendor id (ro) reset value: 100bh index 2eh-2fh subsystem id (ro) reset value: 0501h index 30h-3fh reserved reset value: 00h index 40h-43h base address register 1 - f1bar1 (r/w) reset value: 00000001h this register allows access to i/o mapped acpi related registers. bits [7:0] are read only (0000 0001), indicating a 256 byte a ddress range. refer to table 6-34 on page 263 for bit formats and reset values of the acpi registers. note: this base address register moved from its normal pci h eader space (f1 index 14h) to pr event plug and play software from relocating it after an facp table is built. 31:8 acpi base address. 7:1 address range. (read only) 0 enable. (write only) this bit must be set to 1 to enable access to acpi support registers. index 44h-ffh reserved reset value: 00h
amd geode? sc3200 processor data book 253 core logic module - smi status and acpi registers - function 1 revision 5.1 6.4.2.1 smi status support registers f1 index 10h, base address register 0 (f1bar0), points to the base address for smi status register locations. table 6-33 gives the bit formats of i/o mapped smi status registers accessed through f1bar0. the registers at f1bar0+i/o offset 50h-ffh can also be accessed f0 index 50h-ffh. the preferred method is to program these registers through the f0 register space. table 6-33. f1bar0+i/o offset: smi status registers bit description offset 00h-01h top level pme/smi status mirror register (ro) reset value: 0000h note: reading this register does not clear the status bits. for more information, see f1bar0+i/o offset 02h. 15 suspend modulation enable mirror. this bit mirrors the suspend mode configur ation bit (f0 index 96h[0]). it is used by the smi handler to determine if the smi speedup disable r egister (f1bar0+i/o offset 08h) must be cleared on exit. 14 smi source is usb. indicates whether or not an smi was caused by usb activity 0: no. 1: yes. to enable smi generation, set f5bar0+i/o offset 00h[20:19] to 11. 13 smi source is warm reset command. indicates whether or not an smi was caused by a warm reset command. 0: no. 1: yes. 12 smi source is nmi. indicates whether or not an smi was caused by nmi activity. 0: no. 1: yes. 11 smi source is irq2 of sio module. indicates whether or not an smi was caused by irq2 of the sio module. 0: no. 1: yes. the next level (second level) of smi status is reported in the superi/o module. for more information, see table 5-29 "banks 0 and 1 - common control and status registers" on page 134, offset 00h. 10 smi source is ext_smi[7:0]. indicates whether or not an smi was caused by a negative-edge event on ext_smi[7:0]. 0: no. 1: yes. the next level (second level) of smi stat us is at f1bar0+i/o offset 24h[23:8]. 9 smi source is gp timers/udef/pci/isa function trap. indicates if an smi was caused by: ? expiration of gp timer 1 or 2. ? trapped access to udef1, 2, or 3. ? trapped access to f1-f5 or isa legacy register space. 0: no. 1: yes. the next level (second level) of smi st atus is at f1bar0+i/o offset 04h/06h. 8 smi source is software generated. indicates whether or not an smi was caused by software. 0: no. 1: yes. 7 smi on an a20m# toggle. indicates whether or not an smi was caused by a write access to either port 92h or the key- board command which initiates an a20m# smi. 0: no. 1: yes. this method of controlling the internal a20m # in the gx1 module is used instead of a pin. to enable smi generation, set f0 index 53h[0] to 1.
254 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 6 smi source is a vga timer event. indicates whether or not an smi was caused by the expiration of the vga timer (f0 index 8eh). 0: no. 1: yes. to enable smi generation, set f0 index 83h[3] to 1. 5 smi source is video retrace. indicates whether or not an smi was caused by a video retrace event as decoded from the internal serial connection (pserial r egister, bit 7) from the gx1 module. 0: no. 1: yes. to enable smi generation, set f0 index 83h[2] to 1. 4 reserved. reads as 0. 3 smi source is lpc. indicates whether or not an smi was caused by the lpc interface. 0: no. 1: yes. the next level (second level) of smi stat us is at f0bar1+i/o offset 1ch[6:5]. 2 smi source is acpi. indicates whether or not an smi was caused by an ac cess (read or write) to one of the acpi registers (f1bar1). 0: no. 1: yes. the next level (second level) of smi status is at f1bar0+i/o offset 20h. 1 smi source is audio subsystem. indicates whether or not an smi was caused by the audio subsystem. 0: no. 1: yes. the next level (second level) of smi status is at f3bar0+memory offset 10h/12h. 0 smi source is power management event. indicates whether or not an smi was caused by one of the power management resources (except for gp timers, udefx and pci/is a function traps that are reported in bit 9). 0: no. 1: yes. the next level (second level) of smi status is at f0 index 84h-f4h/87h-f7h. offset 02h-03h top level pme/smi status register (ro/rc) reset value: 0000h note: reading this register clears all the smi stat us bits except for the ?read only? bits, bec ause they have a second level of statu s reporting. clearing the second level status bits also clears the top level (except for gpios). gpio smis have third level of smi status reporting at f0bar0+ i/o offset 0ch/1ch. clearing the third level gpio status bits also clears the second and top levels. a read-only ?mirror? version of this regist er exists at f1bar0+i/o offset 00h. if the value of the register must be read withou t clearing the smi source (and cons equently de-asserting smi), f1bar0+i/o offset 00h can be read instead. 15 suspend modulation enable mirror. (read to clear) this bit mirrors the suspend mode configuration bit (f0 index 96h[ 0]). it is used by the smi handler to determine if the smi speedup disable register (f1bar0+i/o o ffset 08h) must be cleared on exit. 14 smi source is usb. (read to clear) indicates whether or not an smi was caused by usb activity. 0: no. 1: yes. to enable smi generation, set f5bar0+i/o offset 00h[20:19] to 11. 13 smi source is warm reset command. (read to clear) indicates whether or not an smi was caused by warm reset command 0: no. 1: yes. table 6-33. f1bar0+i/o offset: smi status registers (continued) bit description
amd geode? sc3200 processor data book 255 core logic module - smi status and acpi registers - function 1 revision 5.1 12 smi source is nmi. (read to clear) indicates whether or not an smi was caused by nmi activity. 0: no. 1: yes. 11 smi source is irq2 of sio module. (read to clear) indicates whether or not an smi was caused by irq2 of the sio module. 0: no. 1: yes. the next level (second level) of smi status is reported in the superi/o module. see table 5-29 "banks 0 and 1 - common control and status registers" on page 134 for details. 10 smi source is ext_smi[7:0]. (read only. read does not clear) indicates whether or not an smi was caused by a neg- ative-edge event on ext_smi[7:0]. 0: no. 1: yes. the next level (second level) of smi stat us is at f1bar0+i/o offset 24h[23:8]. 9 smi source is general timers/traps. (read only, read does not clear) indicates whether or not an smi was caused by the expiration of one of the general purpose timers or one of the user defined traps. 0: no. 1: yes. the next level (second level) of smi st atus is at f1bar0+i/o offset 04h/06h. 8 smi source is software generated. (read to clear) indicates whether or not an smi was caused by software. 0: no. 1: yes. 7 smi on an a20m# toggle. (read to clear) indicates whether or not an smi was caus ed by an access to either port 92h or the keyboard command which initiates an a20m# smi 0: no. 1: yes. this method of controlling the internal a20m # in the gx1 module is used instead of a pin. to enable smi generation, set f0 index 53h[0] to 1. 6 smi source is a vga timer event. (read to clear) indicates whether or not an smi was caused by expiration of the vga timer (f0 index 8eh). 0: no. 1: yes. to enable smi generation, set f0 index 83h[3] to 1. 5 smi source is video retrace. (read to clear) indicates whether or not an smi was caused by a video retrace event as decoded from the internal serial connection ( pserial register, bit 7) from the gx1 module. 0: no. 1: yes. to enable smi generation, set f0 index 83h[2] to 1. 4 reserved. reads as 0. 3 smi source is lpc. (read only, read does not clear) indicates whether or not an sm i was caused by the lpc inter- face. 0: no. 1: yes. the next level (second level) of smi stat us is at f0bar1+i/o offset 1ch[6:5]. 2 smi source is acpi. (read only, read does not clear) indicates whether or not an smi was caused by an access (read or write) to one of the acpi registers (f1bar1). 0: no. 1: yes. the next level (second level) of smi status is at f1bar0+i/o offset 20h. table 6-33. f1bar0+i/o offset: smi status registers (continued) bit description
256 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 1 smi source is audio subsystem. (read only, read does not clear) indicates whether or not an smi was caused by the audio subsystem. 0: no. 1: yes. the second level of status is found in f3bar0+memory offset 10h/12h. 0 smi source is power management event. (read only, read does not clear) indicates whether or not an smi was caused by one of the power management resources (except for gp timers, udefx and pci/isa function traps which are reported in bit 9). 0: no. 1: yes. the next level (second level) of smi status is at f0 index 84h/f4h-87h/f7h. offset 04h-05h second level general traps & timers reset value: 0000h pme/smi status mirror register (ro) the bits in this register cont ain second level status reporting. top level status is reported at f1bar0+i/o offset 00h/02h[9]. reading this register does not clear the smi. for more information, see f1bar0+i/o offset 06h. 15:6 reserved. 5 pci/isa function trap. indicates whether or not an smi was caus ed by a trapped pci/isa configuration cycle. 0: no. 1: yes. to enable smi generation for: ? trapped access to isa legacy i/o register space set f0 index 41h[0] = 1. ? trapped access to f1 register space set f0 index 41h[1] = 1. ? trapped access to f2 register space set f0 index 41h[2] = 1. ? trapped access to f3 register space set f0 index 41h[3] = 1. ? trapped access to f4 register space set f0 index 41h[4] = 1. ? trapped access to f5 register space set f0 index 41h[5] = 1. 4 smi source is trapped access to user defined device 3. indicates whether or not an smi was caused by a trapped i/o or memory access to the user defined device 3 (f0 index c8h). 0: no. 1: yes. to enable smi generation, set f0 index 82h[6] = 1. 3 smi source is trapped access to user defined device 2. indicates whether or not an smi was caused by a trapped i/o or memory access to the user defined device 2 (f0 index c4h). 0: no. 1: yes. to enable smi generation, set f0 index 82h[5] = 1. 2 smi source is trapped access to user defined device 1. indicates whether or not an smi was caused by a trapped i/o or memory access to the user defined device 1 (f0 index c0h). 0: no. 1: yes. to enable smi generation, set f0 index 82h[4] = 1. 1 smi source is expired general purpose timer 2. indicates whether or not an smi wa s caused by the expiration of gen- eral purpose timer 2 (f0 index 8ah). 0: no. 1: yes. to enable smi generation, set f0 index 83h[1] = 1. table 6-33. f1bar0+i/o offset: smi status registers (continued) bit description
amd geode? sc3200 processor data book 257 core logic module - smi status and acpi registers - function 1 revision 5.1 0 smi source is expired general purpose timer 1. indicates whether or not an smi wa s caused by the expiration of gen- eral purpose timer 1 (f0 index 88h). 0: no. 1: yes. to enable smi generation, set f0 index 83h[0] = 1. offset 06h-07h second level general traps & ti mers status register (rc) reset value: 0000h the bits in this register cont ain second level of status reporting. top level status is reported in f1bar0+i/o offset 00h/02h[9 ]. reading this register clears the status at both the second and top levels. a read-only ?mirror? version of th is register exists at f1bar0+i/o offset 04h. if the value of this register must be read witho ut clearing the smi source (and consequently de-asserting sm i), f1bar0+i/o offset 04h can be read instead. 15:6 reserved. 5 pci/isa function trap. indicates whether or not an smi was caus ed by a trapped pci/isa configuration cycle 0: no. 1: yes. to enable smi generation for: ? trapped access to isa legacy i/o register space set f0 index 41h[0] = 1. ? trapped access to f1 register space set f0 index 41h[1] = 1. ? trapped access to f2 register space set f0 index 41h[2] = 1. ? trapped access to f3 register space set f0 index 41h[3] = 1. ? trapped access to f4 register space set f0 index 41h[4] = 1. ? trapped access to f5 register space set f0 index 41h[5] = 1. 4 smi source is trapped access to user defined device 3 (udef3). indicates whether or not an smi was caused by a trapped i/o or memory access to user defined device 3 (f0 index c8h). 0: no. 1: yes. to enable smi generation, set f0 index 82h[6] = 1. 3 smi source is trapped access to user defined device 2 (udef2). indicates whether or not an smi was caused by a trapped i/o or memory access to user defined device 2 (f0 index c4h). 0: no. 1: yes. to enable smi generation, set f0 index 82h[5] = 1. 2 smi source is trapped access to user defined device 1 (udef1). indicates whether or not an smi was caused by a trapped i/o or memory access to user defined device 1 (f0 index c0h). 0: no. 1: yes. to enable smi generation, set f0 index 82h[4] = 1. 1 smi source is expired general purpose timer 2. indicates whether or not an smi wa s caused by the expiration of gen- eral purpose timer 2 (f0 index 8ah). 0: no. 1: yes. to enable smi generation, set f0 index 83h[1] = 1. 0 smi source is expired general purpose timer 1. indicates whether or not an smi wa s caused by the expiration of gen- eral purpose timer 1 (f0 index 88h). 0: no. 1: yes. to enable smi generation, set f0 index 83h[0] = 1. table 6-33. f1bar0+i/o offset: smi status registers (continued) bit description
258 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 offset 08h-09h smi speedup disable register (read to enable) reset value: 0000h 15:0 smi speedup disable. if bit 1 in the suspend configuration register is se t (f0 index 96h[1] = 1), a read of this register invokes the smi handler to re-enable suspend modulation. the data read from this register can be ignored. if the suspend modulation feature is disabled, reading this i/o location has no effect. offset 0ah-1bh reserved reset value: 00h these addresses should not be written. offset 1ch-1fh acpi timer re gister (ro) reset value: xxxxxxxxh note: this register can also be r ead at f1bar1+i/o offset 1ch. 31:24 reserved. 23:0 tmr_val. this field returns the running count of the power management timer. offset 20h-21h second level acpi pme/smi reset value: 0000h status mirror register (ro) the bits in this register c ontain second level smi status reporting. top leve l status is reported in f1bar0+i/o offset 00h/02h[ 2]. reading this register does not cl ear the smi. for more information, see f1bar0+i/o offset 22h. 15:6 reserved. always reads 0. 5 acpi bios smi status. indicates whether or not an smi was caused by ac pi software raising an event to bios software. 0: no. 1: yes. to enable smi generation, set f1bar1+i/o offset 0ch[2] to 1, and f1bar1+i/o offset 0fh[0] to 1. 4 plvl3 smi status. indicates whether or not an smi was caused by a read of the acpi plvl3 register (f1bar1+i/o offset 05h). 0: no. 1: yes. to enable smi generation, set f1bar1+i/o offset 18h[11] to 1 (default). 3 reserved. 2 slp_en smi status. indicates whether or not an smi was caused by a write of 1 to the acpi slp_en bit (f1bar1+i/o offset 0ch[13]). 0: no. 1: yes. to enable smi generation, set f1bar1+i/o offset 18h[9] to 1 (default). 1 tht_en smi status. indicates whether or not an smi was caused by a write of 1 to the acpi tht_en bit (f1bar1+i/o offset 00h[4]). 0: no. 1: yes. to enable smi generation, set f1bar1+i/o offset 18h[8] to 1 (default). 0 smi_cmd smi status. indicates whether or not an smi was caused by a write to the acpi smi_cmd register (f1bar1+i/ o offset 06h). 0: no. 1: yes. a write to the acpi smi_cmd register always generates an smi. table 6-33. f1bar0+i/o offset: smi status registers (continued) bit description
amd geode? sc3200 processor data book 259 core logic module - smi status and acpi registers - function 1 revision 5.1 offset 22h-23h second level acpi pme/smi status register (rc) reset value: 0000h the bits in this register cont ain second level of smi status reporting. top le vel is reported in f1bar0+i/o offset 00h/02h[2]. reading this register clears the status at both the second and top levels. a read-only ?mirror? version of this regi ster exists at f1bar0+i/o offset 20h. if t he value of the register must be read withou t clearing the smi source (and consequently de -asserting smi), f1bar0+i/o offset 20h can be read instead. 15:6 reserved. always reads 0. 5 acpi bios smi status. indicates whether or not an smi was caused by ac pi software raising an event to bios software. 0: no. 1: yes. to enable smi generation, set f1bar1+i/o offset 0ch[2] to 1, and f1bar1+i/o offset 0fh[0] to 1. 4 plvl3 smi status. indicates whether or not an smi was caused by a re ad of the acpi plvl3 register (f1bar1+i/o offset 05h). 0: no. 1: yes. to enable smi generation, set f1bar1+i/o offset 18h[11] to 1 (default). 3 reserved. 2 slp_en smi status. indicates whether or not an smi was caused by a write of 1 to the acpi slp_en bit (f1bar1+i/o offset 0ch[13]). 0: no. 1: yes. to enable smi generation, set f1bar1+i/o offset 18h[9] to 1 (default). 1 tht_en smi status. indicates whether or not an smi was caused by a write of 1 to the acpi tht_en bit (f1bar1+i/o offset 00h[4]) 0: no. 1: yes. to enable smi generation, set f1bar1+i/o offset 18h[8] to 1 (default). 0 smi_cmd smi status. indicates whether or not an smi was caused by a write to the acpi smi_cmd register (f1bar1+i/ o offset 06h). 0: no. 1: yes. a write to the acpi smi_cmd register always generates an smi. offset 24h-27h external smi re gister (r/w) reset value: 00000000h note: ext_smi[7:0] are external smis, meaning external to the core logic module. bits [23:8] of this register contain sec ond level of smi status reporting. top level status is reported in f1bar0+i/o offset 00 h/ 02h[10]. reading bits [23:16] clears the second and top levels. if t he value of the status bits mu st be read without clearing t he smi source (and consequently de-asserting smi), bits [15:8] can be read instead. 31:24 reserved. must be set to 0. 23 ext_smi7 smi status. (read to clear) indicates whether or not an smi was caused by assertion of ext_smi7. 0: no. 1: yes. to enable smi generation, set bit 7 to 1. 22 ext_smi6 smi status. (read to clear) indicates whether or not an smi was caused by an assertion of ext_smi6 0: no. 1: yes. to enable smi generation, set bit 6 to 1. table 6-33. f1bar0+i/o offset: smi status registers (continued) bit description
260 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 21 ext_smi5 smi status. (read to clear) indicates whether or not an smi was caused by an assertion of ext_smi5. 0: no. 1: yes. to enable smi generation, set bit 5 to 1. 20 ext_smi4 smi status. (read to clear) indicates whether or not an smi was caused by an assertion of ext_smi4. 0: no. 1: yes. to enable smi generation, set bit 4 to 1. 19 ext_smi3 smi status. (read to clear) indicates whether or not an smi was caused by an assertion of ext_smi3. 0: no. 1: yes. to enable smi generation, set bit 3 to 1. 18 ext_smi2 smi status. (read to clear) indicates whether or not an smi was caused by an assertion of ext_smi2. 0: no. 1: yes. to enable smi generation, set bit 2 to 1. 17 ext_smi1 smi status. (read to clear) indicates whether or not an smi was caused by an assertion of ext_smi1. 0: no. 1: yes. to enable smi generation, set bit 1 to 1. 16 ext_smi0 smi status. (read to clear) indicates whether or not an smi was caused by an assertion of ext_smi0. 0: no. 1: yes. to enable smi generation, set bit 0 to 1. 15 ext_smi7 smi status. (read only) indicates whether or not an smi was caused by an assertion of ext_smi7. 0: no. 1: yes. to enable smi generation, set bit 7 to 1. 14 ext_smi6 smi status. (read only) indicates whether or not an smi was caused by an assertion of ext_smi6. 0: no. 1: yes. to enable smi generation, set bit 6 to 1. 13 ext_smi5 smi status. (read only) indicates whether or not an smi was caused by an assertion of ext_smi5. 0: no. 1: yes. to enable smi generation, set bit 5 to 1. 12 ext_smi4 smi status. (read only) indicates whether or not an smi was caused by an assertion of ext_smi4. 0: no. 1: yes. to enable smi generation, set bit 4 to 1. 11 ext_smi3 smi status. (read only) indicates whether or not an smi was caused by an assertion of ext_smi3. 0: no. 1: yes. to enable smi generation, set bit 3 to 1. table 6-33. f1bar0+i/o offset: smi status registers (continued) bit description
amd geode? sc3200 processor data book 261 core logic module - smi status and acpi registers - function 1 revision 5.1 10 ext_smi2 smi status. (read only) indicates whether or not an smi was caused by an assertion of ext_smi2. 0: no. 1: yes. to enable smi generation, set bit 2 to 1. 9 ext_smi1 smi status. (read only) indicates whether or not an smi was caused by an assertion of ext_smi1. 0: no. 1: yes. to enable smi generation, set bit 1 to 1. 8 ext_smi0 smi status. (read only) indicates whether or not an smi was caused by an assertion of ext_smi0. 0: no. 1: yes. to enable smi generation, set bit 0 to 1. 7 ext_smi7 smi enable. when this bit is asserted, allow ext_s mi7 to generate an smi on negative-edge events. 0: disable. 1: enable. top level smi status is reported at f1bar0+00h/02h[10]. second level smi status is reported at bits 23 (rc) and 15 (ro). 6 ext_smi6 smi enable. when this bit is asserted, allow ext_s mi6 to generate an smi on negative-edge events. 0: disable. 1: enable. top level smi status is reported at f1bar0+00h/02h[10]. second level smi status is reported at bits 22 (rc) and 14 (ro). 5 ext_smi5 smi enable. when this bit is asserted, allow ext_s mi5 to generate an smi on negative-edge events. 0: disable. 1: enable. top level smi status is reported at f1bar0+00h/02h[10]. second level smi status is reported at bits 21 (rc) and 13 (ro). 4 ext_smi4 smi enable. when this bit is asserted, allows ext_sm i4 to generate an smi on negative-edge events. 0: disable. 1: enable. top level smi status is reported at f1bar0+00h/02h[10]. second level smi status is reported at bits 20 (rc) and 12 (ro). 3 ext_smi3 smi enable. when this bit is asserted, allow ext_s mi3 to generate an smi on negative-edge events. 0: disable. 1: enable. top level smi status is reported at f1bar0+00h/02h[10]. second level smi status is reported at bits 19 (rc) and 11 (ro). 2 ext_smi2 smi enable. when this bit is asserted, allow ext_s mi2 to generate an smi on negative-edge events. 0: disable. 1: enable. top level smi status is reported at f1bar0+00h/02h[10]. second level smi status is reported at bits 18 (rc) and 10 (ro). 1 ext_smi1 smi enable. when this bit is asserted, allow ext_s mi1 to generate an smi on negative-edge events. 0: disable. 1: enable. top level smi status is reported at f1bar0+00h/02h[10]. second level smi status is reported at bits 17 (rc) and 9 (ro). table 6-33. f1bar0+i/o offset: smi status registers (continued) bit description
262 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 0 ext_smi0 smi enable. when this bit is asserted, allow ext_s mi0 to generate an smi on negative-edge events. 0: disable. 1: enable. top level smi status is reported at f1bar0+00h/02h[10]. second level smi status is reported at bits 16 (rc) and 8 (ro). offset 28h-4fh not used reset value: 00h offset 50h-ffh the i/o mapped registers located here (f1bar 0+i/o offset 50h-ffh) can also be acce ssed at f0 index 50h-ffh. the pre- ferred method is to program these registers through the f0 regi ster space. refer to table 6-29 "f0: pci header/bridge con- figuration registers for gpio and lpc support" on pag e 206 for more information about these registers. table 6-33. f1bar0+i/o offset: smi status registers (continued) bit description
amd geode? sc3200 processor data book 263 core logic module - smi status and acpi registers - function 1 revision 5.1 6.4.2.2 acpi support registers f1 index 40h, base address register 1 (f1bar1), points to the base address of wher e the acpi support registers are located. table 6-34 shows the i/o mapped acpi sup- port registers accessed through f1bar1. table 6-34. f1bar1+i/o offset: acpi support registers bit description offset 00h-03h p_cnt ? processor cont rol register (r/w) reset value: 00000000h 31:5 reserved. always reads 0. 4 tht_en (throttle enable). when this bit is asserted, it enables throttling of the clock based on the clk_val field (bits [2:0] of this register). 0: disable. 1: enable. if f1bar1+i/o offset 18h[8] =1, an smi is generated when this bit is set. top level smi status is reported at f1bar0+i/o offset 00h/02h[2]. second level smi status is report ed at f1bar0+i/o offset 20h/22h[1]. 3 reserved. always reads 0. 2:0 clk_val (clock throttling value). cpu duty cycle: 000: reserved 010: 25% 100: 50% 110: 75% 001: 12.5% 011: 37.5% 101: 62.5% 111: 87.5% offset 04h reserved reset value: 00h note: this register should not be read. it controls a reserved function of power management logic. offset 05h p_lvl3 ? enter c3 power state register (ro) reset value: xxh 7:0 p_lvl3 (power level 3). reading this 8-bit read only regist er causes the processor to enter the c3 power state. reads of p_lvl3 return 0. writes have no effect. the acpi state machine always waits for an smi (any smi) to be generated and serviced before transfer into c3 power state. a read of this register causes an smi if enabled: f1bar1+i/o offset 18h[11] = 1 (default). top level smi status is reported at f1bar0+i/o offset 00h/02h[2]. second level smi status is report ed at f1bar0+i/o offset 20h/22h[4]. offset 06h smi_cmd ? os/bios requests register (r/w) reset value: 00h 7:0 smi_cmd (smi command and os / bios requests). a write to this register stores data and a read returns the last data written. in addition, a write to this register always gener ates an smi. a read of this register does not generate an smi. top level smi status is reported at f1bar0+i/o offset 00h/02h[2]. second level smi status is report ed at f1bar0+i/o offset 20h/22h[0]. offset 07h acpi_fun_cnt ? acpi function control register (r/w) reset value: 00h 7:6 led_cnt (led output control). controls the blinking of an led when in the sl4 or sl5 sleep state 00: disable (led# signal, is hiz). 01: zero (led# signal is hiz). 10: blink @ 1 hz rate, when in sl4 and sl5 sleep states. duty cycle: led# is 10% pulled low, 90% hiz. 11: one (led# is pulled low, when in sl4 and sl5 sleep states) 5 reserved. must be set to 0. 4 intr_wu_sl1. enables wakeup on enabled interrupts in sleep state sl1. 0: disable wakeup from sl1, when an enabled interrupt is active. 1: enable wakeup from sl1, when an enabled interrupt is active. 3 gpwio_dbnc_dis (gpwio0 and gpwio1 debounce). when enabled, a high-to-low or lo w-to-high transition of greater than 15.8 ms is required for gpwio0 and gpwio1 to be recognized. 0: enable. (default) 1: disable. (no debounce) gpwio2 pin does not have debounce capability. 2:1 reserved. must be set to 0.
264 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 0 pwrbtn_dbnc_dis (power button debounce). when enabled, a high-to-low or low- to-high transition of greater than 15.8 ms is required on pwrbtn# before it is recognized. 0: enable. (default) 1: disable. (no debounce) offset 08h-09h pm1a_sts ? pm1a top level pm e/sci status register (r/w) reset value: 0000h notes: 1. this is the top level of pme/sci status r eporting for these events. there is no second level. 2. if sci generation is not desired, the stat us bits are still set by the described conditions and can be used for monitoring pu r- poses. 15 wak_sts (wakeup status). indicates whether or not an sci was caused by the occurrence of an enabled wakeup event. 0: no. 1: yes. this bit is set when the system is in any sleep state and an enabled wakeup event occurs (wakeup events are configured at f1bar1+i/o offset 0ah and 12h). after this bit is set, the system transitions to a working state. sci generation is always enabled. write 1 to clear. 14:12 reserved. must be set to 0. 11 pwrbtnor_sts (power button override status). indicates whether or not an sci was caused by the power button being active for greater than 4 seconds. 0: no. 1: yes. sci generation is always enabled. write 1 to clear. 10 rtc_sts (real-time clock status). indicates if a power management event (pme) was caused by the rtc generating an alarm (rtc irq signal is asserted). 0: no. 1: yes. for the pme to generate an sci, set f1bar1+i/o offset 0ah[10] to 1 and f1bar1+i/o offset 0ch[0] to 1. (see note 2 in the general description of this register.) write 1 to clear. 9 reserved. must be set to 0. 8 pwrbtn_sts (power button status). indicates if pme was caused by the pw rbtn# going low while the system is in a working state. 0: no. 1: yes. for the pme to generate an sci, set f1bar1+i/o offset 0ah[8] = 1 and f1bar1+i/o offset 0ch[0] = 1. (see note 2 in the general description of this register.) in a sleep state or the soft-off state, a wakeup event is generated when the power button is pressed (regardless of the pwrbtn_en bit, f1bar1+i/o offset 0ah[8], setting). write 1 to clear. 7:6 reserved. must be set to 0. 5 gbl_sts (global lock status). indicates if pme was caused by the bios releasing control of the global lock. 0: no. 1: yes. this bit is used by the bios to generate an sci. bios writes the bios_rls bit (f1bar1+i/o offset 0fh[1]) which in turns sets the gbl_sts bit and raises a pme. for the pme to generate an sci, set f1bar1+i/o offset 0ah[5] to 1 and f1bar1+i/o offset 0ch[0] to 1. (see note 2 in the general description of this register.) write 1 to clear. table 6-34. f1bar1+i/o offset: ac pi support registers (continued) bit description
amd geode? sc3200 processor data book 265 core logic module - smi status and acpi registers - function 1 revision 5.1 4 bm_sts (bus master status). indicates if pme was caused by a system bus master requesting the system bus. 0: no. 1: yes. for the pme to generate an sci, set f1bar1+i/o offset 0ch[1] = 1 and f1bar1+i/o offset 0ch[0] = 1. (see note 2 in the general description of this register.) write 1 to clear. 3:1 reserved. must be set to 0. 0 tmr_sts (timer carry status). indicates if sci was caused by an msb t oggle (msb changes from lo w-to-high or high-to- low) on the acpi timer (f1bar0+i/o offs et 1ch or f1bar1+i/o offset 1ch). 0: no. 1: yes. for the pme to generate an sci, set f1bar1+i/o offset 0ah[0] = 1 and f1bar1+i/o offset 0ch[0] = 1. (see note 2 in the general description of this register.) write 1 to clear. offset 0ah-0bh pm1a_en ? pm1a pme/sci enable register (r/w) reset value: 0000h in order for the acpi events described below to generate an sci, the sci_en bit must also be set (f1bar1+i/o offset 0ch[0] = 1) . the scis enabled via this regist er are globally enabled by setting f1bar1+i/o offset 08h. there is no second level of sci statu s report- ing for these bits. 15:11 reserved. must be set to 0. 10 rtc_en (real-time clock enable). allow sci generation when the rtc generates an alarm (rtc irq signal is asserted). 0: disable. 1: enable 9 reserved. must be set to 0. 8 pwrbtn_en (power button enable). allow sci generation when pwrbtn# goes lo w while the system is in a working state. 0: disable. 1: enable 7:6 reserved. must be set to 0. 5 gbl_en (global lock enable). allow sci generation when the bios releases c ontrol of the global lock via the bios_rls (f1bar1+i/o offset 0fh[1] and gbl_st s (f1bar1+i/o offset 08h[5]) bits. 0: disable. 1: enable 4:1 reserved. must be set to 0. 0 tmr_en (acpi timer enable). allow sci generation for msb toggles (msb c hanges from low-to-high or high-to-low) on the acpi timer (f1bar0+i/o offset 1ch or f1bar1+i/o offset 1ch). 0: disable. 1: enable offset 0ch-0dh pm1a_cnt ? pm1a control register (r/w) reset value: 0000h 15:14 reserved. must be set to 0. table 6-34. f1bar1+i/o offset: ac pi support registers (continued) bit description
266 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 13 slp_en (sleep enable). (write only) allow the system to sequence into the sl eeping state associated with the slp_typx (bits [12:10]). 0: disable. 1: enable. this is a write only bit and reads of this bit always return a 0. the acpi state machine always waits for an smi (any smi) to be generated and serviced before transitioning into a sleep state. if f1bar1+i/o offset 18h[9] = 1, an smi is generated when slp_en is set. top level smi status is reported at f1bar0+i/o offset 00h/02h[2]. second level smi status is report ed at f1bar0+i/o offset 20h/22h[2]. 12:10 slp_typx (sleep type). defines the type of sleep state the system enters when slp_en (bit 13) is set. 000: sleep state s0 (full on) 100: sleep state sl4 001: sleep state sl1 101: sleep state sl5 (soft off) 010: sleep state sl2 110: reserved 011: sleep state sl3 111: reserved 9:3 reserved. set to 0. 2 gbl_rls (global release). (write only) this write only bit is used by acpi software to raise an event to the bios soft- ware (i.e., it generates an smi to pass execution control to the bios). 0: disable. 1: enable. this is a write only bit and reads of this bit always return a 0. to generate an smi, acpi software writes the gbl_rls bit whic h in turn sets the bios_sts bit (f1bar1+i/o offset 0eh[0]) and raises a pme. for the pme to generate an sm i, set bios_en (f1bar1+i/o offset 0fh[0] to 1). the top level smi status is reported at f1bar0+i/o offset 00h/02h. second level status is at f1bar0+i/o offset 22h[5]. 1 bm_rld (bus master rld). if the processor is in the c3 state and a bus master request is generated, force the processor to transition to the c0 state. 0: disable. 1: enable 0 sci_en (system control interrupt enable). globally selects power management ev ents (pmes) reported in pm1a_sts and gpe0_sts (f1bar1+i/o offset 08h and 10h) to be either an sci or smi type of interrupt. 0: apm mode, generates an smi and status is reported at f1bar0+i/o offset 00h/02h[0]. 1: acpi mode, generates an sci if the corresponding pme enable bit is set and status is reported at f1bar1+i/o offset 08h and 10h. note: this bit enables the acpi state machine. offset 0eh acpi_bios_sts regi ster (r/w) reset value: 00h 7:1 reserved. must be set to 0. 0 bios_sts (bios status release). when 1 is written to the glb_rls bit (f1bar 1+i/o offset 0ch[2]), this bit is also set to 1. write 1 to clear. table 6-34. f1bar1+i/o offset: ac pi support registers (continued) bit description
amd geode? sc3200 processor data book 267 core logic module - smi status and acpi registers - function 1 revision 5.1 offset 0fh acpi_bios_en register (r/w) reset value: 00h 7:2 reserved. must be set to 0. 1 bios_rls (bios release). (write only) when this bit is asserted, allow the bios to release control of the global lock. 0: disable. 1: enable. this is a write only bit and reads of this bit always return a 0. to generate an sci, the bios writes the bios_rls bit which in turn sets the gbl_sts bit (f1bar1+i/o offset 08h[5]) and raises a pme. for the pme to generate an sci, se t gbl_en (f1bar1+i/o offset 0ah[5] to 1). 0 bios_en (bios enable). when this bit is asserted, allow smi generati on by acpi software via writes to gbl_rls (f1bar1+i/o offset 0ch[2]). 0: disable. 1: enable offset 10h-11h gpe0_sts ? general purpose event 0 pme/sci status register (r/w) reset value: xxxxh notes: 1) this is the top level of pme/sci status reporting. there is no second level except for bit 3 (gpios) where the next level of status is reported at f0bar0+i/o offset 0ch/1ch. 2) if sci generation is not desired, the stat us bits are still set by the described conditions and can be used for monitoring pu r- poses. 15:12 reserved. must be set to 0. 11 reserved. 10 gpwio2_sts. indicates if pme was caused by activity on gpwio2. 0: no. 1: yes. write 1 to clear. for the pme to generate an sci: 1) ensure that gpwio2 is enabled as an input (f1bar1+i/o offset 15h[2] = 0) 2) set f1bar1+i/o offset 12h[10] = 1 and f1bar1+i/o offset 0ch[ 0] = 1. (see note 2 in the general description of this register above.) if f1bar1+i/o offset 15h[6] = 1 it overrides these settings and gpwio2 generates an smi and the status is reported in f1bar0+00h/02h[0]. 9 gpwio1_sts. indicates if pme was caused by activity on gpwio1. 0: no. 1: yes. write 1 to clear. for the pme to generate an sci: 1) ensure that gpwio1 is enabled as an input (f1bar1+i/o offset 15h[1] = 0) 2) set f1bar1+i/o offset 12h[9] = 1 and f1bar1+i/o offset 0ch[ 0] = 1. (see note 2 in the general description of this register above.) if f1bar1+i/o offset 15h[5] = 1 it overrides these settings and gpwio1 generates an smi and the status is reported in f1bar0+00h/02h[0]. 8 gpwio0_sts. indicates if pme was caused by activity on gpwio0. 0: no. 1: yes. write 1 to clear. for the pme to generate an sci: 1) ensure that gpwio0 is enabled as an input (f1bar1+i/o offset 15h[0] = 0) 2) set f1bar1+i/o offset 12h[8] = 1 and f1bar1+i/o offset 0ch[ 0] = 1. (see note 2 in the general description of this register above). if f1bar1+i/o offset 15h[4] = 1 it overrides these settings and gpwio0 generates an smi and the status is reported in f1bar0+00h/02h[0]. table 6-34. f1bar1+i/o offset: ac pi support registers (continued) bit description
268 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 7 reserved. must be set to 0. 6 usb_sts. indicates if pme was caused by a usb interrupt event. 0: no. 1: yes. write 1 to clear. for the pme to generate an sci, set f1bar1+i/o offset 12h[6] = 1 and f1bar1+i/o offset 0ch[0] = 1. (see note 2 in the general description of this register above.) 5 thrm_sts. indicates if pme was caused by activity on thrm#. 0: no. 1: yes. write 1 to clear. for the pme to generate an sci, set f1bar1+i/o offset 12h[5] = 1 and f1bar1+i/o offset 0ch[0] = 1, (see note 2 in the general description of this register above,) 4 smi_sts. indicates if pme was caused by activity on the internal smi# signal. 0: no. 1: yes. write 1 to clear. for the pme to generate an sci, set f1bar1+i/o offset 12h[4] = 1 and f1bar1+i/o offset 0ch[0] = 1. (see note 2 in the general description of this register above.) 3 gpio_sts. indicates if pme was caused by activity on any of t he gpios (gpio47-gpio 32 and gpio15-gpio0). 0: no. 1: yes. write 1 to clear. for the pme to generate an sci, set f1bar1+i/o offset 12h[3] = 1 and f1bar1+i/o offset 0ch[0] = 1. (see note 2 in the general description of this register above). f0bar0+i/o offset 08h/18h selects which gpios are enabled to generate a pme. in addition, the selected gpio must be enabled as an input (f0bar 0+i/o offset 20h and 24h). 2:1 reserved. reads as 0. 0 pwr_u_req_sts. indicates if pme was caused by a powe r-up request event from the superi/o module. 0: no. 1: yes. write 1 to clear. for the pme to generate an sci, set f1bar1+i/o offset 12h[0] = 1 and f1bar1+i/o offset 0ch[0] = 1. (see note 2 in the general description of this register above.) table 6-34. f1bar1+i/o offset: ac pi support registers (continued) bit description
amd geode? sc3200 processor data book 269 core logic module - smi status and acpi registers - function 1 revision 5.1 offset 12h-13h gpe0_en ? general purpose e vent 0 enable register (r/w) reset value: 0000h in order for the acpi events described below to generate an sci, the sci_en bit must also be set (f1bar1+i/o offset 0ch[0] = 1) . the scis enabled in this register are globally enabled by setting f1bar1+i/o offset 0ch[0] to 1. the status of the scis is repo rted in f1bar1+i/o offset 10h. 15:12 reserved. 11 reserved. 10 gpwio2_en. allow gpwio2 to generate an sci. 0: disable. 1: enable. a fixed high-to-low or low-to-high trans ition (debounce period) of 31 s exists in order for gpwio2 to be recognized. the setting of this bit can be overridden vi a f1bar1+i/o offset 15h[6] to force an smi. 9 gpwio1_en. allow gpwio1 to generate an sci. 0: disable. 1: enable. see f1bar1+i/o offset 07h[3] for debounce information. the setting of this bit can be overridden vi a f1bar1+i/o offset 15h[5] to force an smi. 8 gpwio0_en. allow gpwio0 to generate an sci. 0: disable. 1: enable. see f1bar1+i/o offset 07h[3] for debounce information. the setting of this bit can be overridden vi a f1bar1+i/o offset 15h[4] to force an smi. 7 reserved. must be set to 0 6 usb_en. allow usb events to generate a sci. 0: disable. 1: enable 5 thrm_en. allow thrm# to generate an sci. 0: disable. 1: enable 4 smi_en. allow smi events to generate an sci. 0: disable. 1: enable 3 gpio_en. allow gpios (gpio47-gp io32 and gpio15-gpio0) to generate an sci. 0: disable. 1: enable. f0bar0+i/o offset 08h/18h selects which gpios are enabled for pme generation. this bit (gpio_en) globally enables those selected gpios for generation of an sci. 2:1 reserved. must be set to 0. 0 pwr_u_req_en. allow power-up request events from the superi/o module to generate an sci. 0: disable. 1: enable. a power-up request event is defined as any of the following events/activities: modem, tel ephone, keyboard, mouse, ceir (consumer electronic infrared) table 6-34. f1bar1+i/o offset: ac pi support registers (continued) bit description
270 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 offset 14h gpwio control register 1 (r/w) reset value: 00h 7:4 reserved. must be set to 0. 3 reserved. 2 gpwio2_pol. select gpwio2 polarity. 0: active high 1: active low 1 gpwio1_pol. select gpwio1 polarity. 0: active high 1: active low 0 gpwio0_pol. select gpwio0 polarity. 0: active high 1: active low offset 15h gpwio control register 2 (r/w) reset value: 00h 7 reserved. 6 gpwio_smien2. allow gpwio2 to generate an smi. 0: disable. (default) 1: enable. a fixed high-to-low or low-to-high trans ition (debounce period) of 31 s exists in order for gpwio2 to be recognized. bit 2 of this register must be set to 0 (input) for gpwio2 to be able to generate an smi. if asserted, this bit overrides the setting of f1bar1+i/o offs et 12h[10] and its status is reported in f1bar0+i/o offset 00h/ 02h[0]. 5 gpwio_smien1. allow gpwio1 to generate an smi. 0: disable. (default) 1: enable. see f1bar1+i/o offset 07h[3] for debounce information. bit 1 of this register must be set to 0 (input) for gpwio1 to be able to generate an smi. if asserted, this bit overrides the setti ng of f1bar1+i/o offset 12h[9] and its stat us is reported in f1bar0+i/o offset 00h/ 02h[0]. 4 gpwio_smien0. allow gpwio0 to generate an smi. 0: disable. (default) 1: enable. see f1bar1+i/o offset 07h[3] for debounce information. bit 0 of this register must be set to 0 (input) for gpwio0 to be able to generate an smi. if enabled, this bit overrides the setting of f1bar1+i/o offset 12h[8] and its status is reported in f1bar0+i/o offset 00h/ 02h[0]. 3 reserved. 2 gpwio2_dir. selects the direction of gpwio2. 0: input. 1: output. 1 gpwio1_dir. selects the direction of gpwio1. 0: input. 1: output. 0 gpwio0_dir. selects the direction of the gpwio0. 0: input. 1: output. table 6-34. f1bar1+i/o offset: ac pi support registers (continued) bit description
amd geode? sc3200 processor data book 271 core logic module - smi status and acpi registers - function 1 revision 5.1 offset 16h gpwio data register (r/w) reset value: 00h this register contains the direct values of the gpwio2-gpwio0 pins. write operations are valid only for bits defined as outputs . reads from this register read the last written value if the pin is an output. the pins ar e configured as inputs or outputs in f1bar1+ i/o offset 15h. 7:4 reserved. must be set to 0. 3 reserved. 2 gpwio2_data. reflects the level of gpwio2. 0: low. 1: high. a fixed high-to-low or low-to-high trans ition (debounce period) of 31 s exists in order for gpwio2 to be recognized. 1 gpwio1_data. reflects the level of gpwio1. 0: low. 1: high. see f1bar1+i/o offset 07h[3] for debounce information. 0 gpwio0_data. reflects the level of gpwio0. 0: low. 1: high. see f1bar1+i/o offset 07h[3] for debounce information. offset 17h reserved reset value: 00h offset 18h-1bh acpi sci_routing re gister (r/w) reset value: 00000f00h 31:17 reserved. 16 pctl_delayen. allow staggered delays on the activation and deacti vation of the power control pins pwrcnt1, pwrcnt2, and onctl# by 2 ms each. 0: disable. (default) 1: enable. 15:12 reserved. must be set to 0. 11 plvl3_smien. allow smi generation when the plvl3 regi ster (f1bar1+i/o offset 05h) is read. 0: disable. 1: enable. (default) top level smi status is reported at f1bar0+i/o offset 00h/02h[2]. second level smi status is report ed at f1bar0+i/o offset 20h/22h[4]. 10 reserved. must be set to 0. 9 slp_smien. allow smi generation when the slp_en bit (f1bar1+i/o offset 0ch[13]) is set. 0: disable. 1: enable. (default) top level smi status is reported at f1bar0+i/o offset 00h/02h[2]. second level smi status is report ed at f1bar0+i/o offset 20h/22h[2]. 8 tht_smien. allow smi generation when the tht_en bit (f1bar1+i/o offset 00h[4]) is set. 0: disable. 1: enable. (default) top level smi status is reported at f1bar0+i/o offset 00h/02h[2]. second level smi status is report ed at f1bar0+i/o offset 20h/22h[1]. 7:4 reserved. must be set to 0. table 6-34. f1bar1+i/o offset: ac pi support registers (continued) bit description
272 amd geode? sc3200 processor data book core logic module - smi status and acpi registers - function 1 revision 5.1 3:0 sci_irq_route. sci is routed to: 0000: disable 0100: irq4 1000: irq8 1100: irq12 0001: irq1 0101: irq5 1001: irq9 1101: irq13 0010: reserved 0010: irq6 1010: irq10 1110: irq14 0011: irq3 0011: irq7 1011: irq11 1111: irq15 for more details see section 6.2.6.3 "programmable interrupt controller" on page 171. offset 1ch-1fh acpi timer re gister (ro) reset value: xxxxxxxxh note: this register can also be r ead at f1bar0+i/o offset 1ch. 31:24 reserved. 23:0 tmr_val. (read only) this bit field contains the running count of the power management timer. offset 20h pm2_cnt ? pm2 control register (r/w) reset value: 00h 7:1 reserved. 0 arbiter disable. disables the pci arbiter when set by the os. used during c3 transition. 0: arbiter not disabled. (default) 1: disable arbiter. offset 21h-ffh reserved reset value: 00h the read value for these registers is undefined. table 6-34. f1bar1+i/o offset: ac pi support registers (continued) bit description
amd geode? sc3200 processor data book 273 core logic module - ide controller registers - function 2 revision 5.1 6.4.3 ide controller registers - function 2 the register space designated as function 2 (f2) is used to configure channels 0 and 1 and the pci portion of sup- port hardware for the ide controllers. the bit formats for the pci header/channels 0 and 1 registers are given in table 6-35. located in the pci header registers of f2 is a base address register (f2bar4) used for pointing to the regis- ter space designated for support of the ide controllers, described later in this section. table 6-35. f2: pci header/channels 0 and 1 registers for ide controller configuration bit description index 00h-01h vendor identification register (ro) reset value: 100bh index 02h-03h device identification register (ro) reset value: 0502h index 04h-05h pci command register (r/w) reset value: 0000h 15:3 reserved. (read only) 2 bus master. allow the core logic module bus mastering capabilities. 0: disable. 1: enable. (default) this bit must be set to 1. 1 reserved. (read only) 0 i/o space. allow the core logic module to res pond to i/o cycles from the pci bus. 0: disable. 1: enable. this bit must be enabled, in order to access i/o offset s through f2bar4 (for more information see f2 index 20h). index 06h-07h pci status register (ro) reset value: 0280h index 08h device revision id register (ro) reset value: 01h index 09h-0bh pci class code register (ro) reset value: 010180h index 0ch pci cache line size register (ro) reset value: 00h index 0dh pci latency timer register (ro) reset value: 00h index 0eh pci header type (ro) reset value: 00h index 0fh pci bist register (ro) reset value: 00h index 10h-13h base address register 0 - f2bar0 (ro) reset value: 00000000h reserved. reserved for possible future use by the core logic module. index 14h-17h base address register 1 - f2bar1 (ro) reset value: 00000000h reserved. reserved for possible future use by the core logic module. index 18h-1bh base address register 2 - f2bar2 (ro) reset value: 00000000h reserved. reserved for possible future use by the core logic module. index 1ch-1fh base address register 3 - f2bar3 (ro) reset value: 00000000h reserved. reserved for possible future use by the core logic module. index 20h-23h base address register 4 - f2bar4 (r/w) reset value: 00000001h base address 0 register. this register allows ac cess to i/o mapped bus mastering ide regist ers. bits [3:0] are read only (0001), indi- cating a 16-byte i/o address range. refer to table 6-36 on page 277 for the ide controller register bit formats and reset value s. 31:4 bus mastering ide base address. 3:0 address range. (read only) index 24h-2bh reserved reset value: 00h index 2ch-2dh subsystem vendor id (ro) reset value: 100bh index 2eh-2fh subsystem id (ro) reset value: 0502h
274 amd geode? sc3200 processor data book core logic module - ide controller registers - function 2 revision 5.1 index 30h-3fh reserved reset value: 00h index 40h-43h channel 0 drive 0 pi o register (r/w) reset value: 00009172h if index 44h[31] = 0, format 0. bits [15:0] configure the same timing control for both command and data. format 0 settings for a fast-pci clock frequency of 33.3 mhz: ? pio mode 0 = 00009172h ? pio mode 1 = 00012171h ? pio mode 2 = 00020080h ? pio mode 3 = 00032010h ? pio mode 4 = 00040010h format 0 settings for a fast-pci clock frequency of 66.7 mhz: ? pio mode 0 = 0000fff4h ? pio mode 1 = 0001f353h ? pio mode 2 = 00028141h ? pio mode 3 = 00034231h ? pio mode 4 = 00041131h note: all references to "cycle" in the following bi t descriptions are to a fast-pci clock cycle. 31:20 reserved. must be set to 0. 19:16 piomode. pio mode. 15:12 t2i. recovery time (value + 1 cycle). 11:8 t3. ide_iow# data setup time (value + 1 cycle). 7:4 t2w. ide_iow# width minus t3 (value + 1 cycle). 3:0 t1. address setup time (value + 1 cycle). if index 44h[31] = 1, format 1. bits [31:0] allow independent timing control for both command and data. format 1 settings for a fast-pci clock frequency of 33.3 mhz: ? pio mode 0 = 9172d132h ? pio mode 1 = 21717121h ? pio mode 2 = 00803020h ? pio mode 3 = 20102010h ? pio mode 4 = 00100010h format 1 settings for a fast-pci clock frequency of 66.7 mhz: ? pio mode 0 = f8e4f8e4h ? pio mode 1 = 53f3f353h ? pio mode 2 = 13f18141h ? pio mode 3 = 42314231h ? pio mode 4 = 11311131h note: all references to "cycle" in the following bi t descriptions are to a fast-pci clock cycle. 31:28 t2ic. command cycle recovery ti me (value + 1 cycle). 27:24 t3c. command cycle ide_iow# data setup (value + 1 cycle). 23:20 t2wc. command cycle ide_iow# pulse wi dth minus t3 (value + 1 cycle). 19:16 t1c. command cycle address setup time (value + 1 cycle). 15:12 t2id. data cycle recovery time (value + 1 cycle). 11:8 t3d. data cycle ide_iow# data setup (value + 1 cycle). 7:4 t2wd. data cycle ide_iow# pulse widt h minus t3 (value + 1 cycle). 3:0 t1d. data cycle address setup time (value + 1 cycle). table 6-35. f2: pci header/channels 0 and 1 registers for ide controller configuration (continued) bit description
amd geode? sc3200 processor data book 275 core logic module - ide controller registers - function 2 revision 5.1 index 44h-47h channel 0 drive 0 dma c ontrol register (r /w) reset value: 00077771h the structure of this register depends on the value of bit 20. if bit 20 = 0, multiword dma settings for a fast-pci clock frequency of 33.3 mhz: ? multiword dma mode 0 = 00077771h ? multiword dma mode 1 = 00012121h ? multiword dma mode 2 = 00002020h settings for a fast-pci clock frequency of 66.7 mhz: ? multiword dma mode 0 = 000ffff3h ? multiword dma mode 1 = 00035352h ? multiword dma mode 2 = 00015151h note: all references to "cycle" in the following bi t descriptions are to a fast-pci clock cycle. 31 pio mode format. this bit sets the pio mode format for all channels and drives. bit 31 of offsets 2ch, 34h, and 3ch are r/ w, but have no function so are defined as reserved. 0: format 0. 1 format 1. 30:21 reserved. must be set to 0. 20 dma select. selects type of dma operation. 0: multiword dma 19:16 tkr. ide_ior# recovery time (4-bit) (value + 1 cycle). 15:12 tdr. ide_ior# pulse width (value + 1 cycle). 11:8 tkw . ide_iow# recovery time (4-bit) (value + 1 cycle). 7:4 tdw . ide_iow# pulse width (value + 1 cycle). 3:0 tm. ide_cs[1:0]# to ide_ior#/iow# setup; ide_cs[1:0]# setup to ide_dack0#/dack1#. if bit 20 = 1, ultradma settings for a fast-pci clock frequency of 33.3 mhz: ? ultradma mode 0 = 00921250h ? ultradma mode 1 = 00911140h ? ultradma mode 2 = 00911030h settings for a fast-pci clock frequency of 66.7 mhz: ? ultradma mode 0 = 009436a1h ? ultradma mode 1 = 00933481h ? ultradma mode 2 = 00923261h note: all references to "cycle" in the following bi t descriptions are to a fast-pci clock cycle. 31 pio mode format. this bit sets the pio mode format for all channels and drives. bit 31 of offsets 2ch, 34h, and 3ch are r/ w, but have no function so are defined as reserved. 0: format 0 1: format 1 30:24 reserved. must be set to 0. 23:21 bsize. input buffer threshold. 20 dma select. selects type of dma operation. 1: ultradma. 19:16 tcrc. crc setup udma in ide_dack# (value + 1 cycle) (for host terminate crc setup = tmli + tss). 15:12 tss. udma out (value + 1 cycle). 11:8 tcyc. data setup and cycle time udma out (value + 2 cycles). 7:4 trp. ready to pause time (value + 1 cycle). note: trfs + 1 trp on next clock. 3:0 tack. ide_cs[1:0]# setup to ide_dack0#/dack1# (value + 1 cycle). table 6-35. f2: pci header/channels 0 and 1 registers for ide controller configuration (continued) bit description
276 amd geode? sc3200 processor data book core logic module - ide controller registers - function 2 revision 5.1 index 48h-4bh channel 0 drive 1 pio register (r/w) reset value: 00009172h channel 0 drive 1 programmed i/o control register. see f2 index 40h for bit descriptions. index 4ch-4fh channel 0 drive 1 dma c ontrol register (r /w) reset value: 00077771h channel 0 drive 1 mdma/udma control register. see f2 index 44h for bit descriptions. note: the pio mode format is selected in f2 index 44h[31 ], bit 31 of this register is defined as reserved. index 50h-53h channel 1 drive 0 pi o register (r/w) reset value: 00009172h channel 1 drive 0 programmed i/o control register . see f2 index 40h for bit descriptions. index 54h-57h channel 1 drive 0 dma c ontrol register (r /w) reset value: 00077771h channel 1 drive 0 mdma/udma control register. see f2 index 44h for bit descriptions. note: the pio mode format is selected in f2 index 44h[31 ], bit 31 of this register is defined as reserved. index 58h-5bh channel 1 drive 1 pio register (r/w) reset value: 00009172h channel 1 drive 1 programmed i/o control register. see f2 index 40h for bit descriptions. index 5ch-5fh channel 1 drive 1 dma c ontrol register (r /w) reset value: 00077771h channel 1 drive 1 mdma/udma control register. see f2 index 44h for bit descriptions. note: the pio mode format is selected in f2 index 44h[31 ], bit 31 of this register is defined as reserved. index 60h-ffh reserved reset value: 00h table 6-35. f2: pci header/channels 0 and 1 registers for ide controller configuration (continued) bit description
amd geode? sc3200 processor data book 277 core logic module - ide controller registers - function 2 revision 5.1 6.4.3.1 ide controller support registers f2 index 20h, base address register 4 (f2bar4), points to the base address of where the registers for ide control- ler configuration are located. table 6-36 gives the bit for- mats of the i/o mapped ide controller configuration registers that are accessed through f2bar4. table 6-36. f2bar4+i/o offset: ide controller configuration registers bit description offset 00h ide bus master 0 command register ? primary (r/w) reset value: 00h 7:4 reserved. must be set to 0. must return 0 on reads. 3 read or write control. sets the direction of bus master transfers. 0: pci reads performed. 1: pci writes performed. this bit should not be changed when the bus master is active. 2:1 reserved. must be set to 0. must return 0 on reads. 0 bus master control. controls the state of the bus master. 0: disable master. 1: enable master. bus master operations can be halted by setting this bit to 0. once an operation has been halted, it cannot be resumed. if this bit is set to 0 while a bus master operation is active, the co mmand is aborted and the data transf erred from the drive is dis- carded. this bit should be reset after completion of data transfer. offset 01h not used offset 02h ide bus master 0 status regi ster ? primary (r/w) reset value: 00h 7 simplex mode. (read only) indicates if both the primary and secondary channel operate independently. 0: yes. 1: no (simplex mode). 6 drive 1 dma enable. when asserted, allows drive 1 to perform dma transfers. 0: disable. 1: enable. 5 drive 0 dma enable. when asserted, allows drive 0 to perform dma transfers. 0: disable. 1: enable. 4:3 reserved. must be set to 0. must return 0 on reads. 2 bus master interrupt. indicates if the bus master detected an interrupt. 0: no. 1: yes. write 1 to clear. 1 bus master error. indicates if the bus master detected an error during data transfer. 0: no. 1: yes. write 1 to clear. 0 bus master active. indicates if the bus master is active. 0: no. 1: yes. offset 03h not used offset 04h-07h ide bus master 0 prd tabl e address ? primary (r/w) reset value: 00000000h 31:2 pointer to the physical region descriptor table. this bit field contains a prd ta ble pointer for ide bus master 0. when written, this field points to the first entry in a prd table. once ide bus master 0 is enabled (command register bit 0 = 1), it loads the pointer and updates this field (by adding 08h) so that is points to the next prd. when read, this register points to the next prd. 1:0 reserved. must be set to 0.
278 amd geode? sc3200 processor data book core logic module - ide controller registers - function 2 revision 5.1 offset 08h ide bus master 1 command regi ster ? secondary (r/w) reset value: 00h 7:4 reserved. must be set to 0. must return 0 on reads. 3 read or write control. sets the direction of bus master transfers. 0: pci reads are performed. 1: pci writes are performed. this bit should not be changed when the bus master is active. 2:1 reserved. must be set to 0. must return 0 on reads. 0 bus master control. controls the state of the bus master. 0: disable master. 1: enable master. bus master operations can be halted by setting this bit to 0. once an operation has been halted, it cannot be resumed. if this bit is set to 0 while a bus master operation is active, the co mmand is aborted and the data transf erred from the drive is dis- carded. this bit should be reset after completion of data transfer. offset 09h not used offset 0ah ide bus master 1 status regi ster ? secondary (r/w) reset value: 00h 7 reserved. (read only) 6 drive 1 dma capable. allow drive 1 to perform dma transfers. 0: disable. 1: enable. 5 drive 0 dma capable. allow drive 0 to perform dma transfers. 0: disable. 1: enable. 4:3 reserved. must be set to 0. must return 0 on reads. 2 bus master interrupt. indicates if the bus master detected an interrupt. 0: no. 1: yes. write 1 to clear. 1 bus master error. indicates if the bus master detected an error during data transfer. 0: no. 1: yes. write 1 to clear. 0 bus master active. indicates if the bus master is active. 0: no. 1: yes. offset 0bh not used offset 0ch-0fh ide bus master 1 prd tabl e address ? secondary (r/w) reset value: 00000000h 31:2 pointer to the physical region descriptor table. this bit field contains a prd ta ble pointer for ide bus master 1. when written, this field points to the first entry in a prd table. once ide bus master 1 is enabled (command register bit 0 = 1), it loads the pointer and updates this field (by adding 08h) so that is points to the next prd. when read, this register points to the next prd. 1:0 reserved. must be set to 0. table 6-36. f2bar4+i/o offset: ide controll er configuration registers (continued) bit description
amd geode? sc3200 processor data book 279 core logic module - audio registers - function 3 revision 5.1 6.4.4 audio registers - function 3 the register designated as func tion 3 (f3) is used to con- figure the pci portion of support hardware for the audio registers. the bit formats for the pci header registers are given in table 6-37. a base address register (f 3bar0), located in the pci header registers of f3, is used for pointing to the register space designated for support of audio, described later in this section. table 6-37. f3: pci header registers for audio configuration bit description index 00h-01h vendor identification register (ro) reset value: 100bh index 02h-03h device identification register (ro) reset value: 0503h index 04h-05h pci command register (r/w) reset value: 0000h 15:3 reserved. (read only) 2 bus master. allow the core logic module bus mastering capabilities. 0: disable. 1: enable. (default) this bit must be set to 1. 1 memory space. allow the core logic module to respond to memory cycles from the pci bus. 0: disable. 1: enable. this bit must be enabled to access memory offsets through f3bar0 (see f3 index 10h). 0 reserved. (read only) index 06h-07h pci status register (ro) reset value: 0280h index 08h device revision id register (ro) reset value: 00h index 09h-0bh pci class code register (ro) reset value: 040100h index 0ch pci cache line size register (ro) reset value: 00h index 0dh pci latency timer register (ro) reset value: 00h index 0eh pci header type (ro) reset value: 00h index 0fh pci bist register (ro) reset value: 00h index 10h-13h base address register - f3bar0 (r/w) reset value: 00000000h this register sets the base address of t he memory mapped audio interface control regist er block. this is a 128-byte block of re gisters used to control the audio fifo and codec interface, as well as to support vsa smis. bits [11:0] are read only (0000 0000 0000), indicat- ing a 4 kb memory address range. refer to table 6-38 on page 280 for the audio configuration regi ster bit formats and reset val ues. 31:12 audio interface base address 11:0 address range. (read only) index 14h-2bh reserved reset value: 00h index 2ch-2dh subsystem vendor id (ro) reset value: 100bh index 2eh-2fh subsystem id (ro) reset value: 0503h index 30h-ffh reserved reset value: 00h
280 amd geode? sc3200 processor data book core logic module - audio registers - function 3 revision 5.1 6.4.4.1 audio support registers f3 index 10h, base address register 0 (f3bar0), points to the base address of where the registers for audio sup- port are located. table 6-38 gives the bit formats of the memory mapped audio configuration registers that are accessed through f3bar0. table 6-38. f3bar0+memory offset: audio configuration registers bit description offset 00h-03h codec gpio status register (r/w) reset value: 00000000h 31 codec gpio interface. 0: disable. 1: enable. 30 codec gpio smi. when asserted, allows codec gp io interrupt to generate an smi. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[1]. second level smi status is reported at f3bar0+memory offset 10h/12h[1]. 29:21 reserved. must be set to 0. 20 codec gpio status valid. (read only) indicates if the status read is valid. 0: yes. 1: no. 19:0 codec gpio pin status. (read only) this field indicates the gpio pin status that is received from the codec in slot 12 on the sdata_in signal. offset 04h-07h codec gpio contro l register (r/w) reset value: 00000000h 31:20 reserved. must be set to 0. 19:0 codec gpio pin data. this field indicates the gpio pin data that is s ent to the codec in slot 12 on the sdata_out signal. offset 08h-0bh codec status register (r/w) reset value: 00000000h 31:24 codec status address. (read only) address of the register for which status is being returned. this address comes from slot 1 bits [19:12]. 23 codec serial int enable. when asserted, allows codec serial interrupt to cause an smi. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[1]. second level smi status is reported at f3bar0+memory offset 10h/12h[1]. 22 sync pin. sets sync high or low. 0: low. 1: high. 21 sdata_in2_en. when enabled, allows use of sdata_in2 input. 0: disable. 1: enable. 20 audio bus master 5 ac97 slot select. selects slot for audio bus master 5 to receive data. 0: slot 6. 1: slot 11. 19 audio bus master 4 ac97 slot select. selects slot for audio bus master 4 to transmit data. 0: slot 6. 1: slot 11. 18 reserved. must be set to 0. 17 status tag. (read only) the codec status data in bits [15:0] of this r egister is updated in the current ac97 frame. (codec ready, slot1 and slot2 bits in tag slot are all set in current ac97 frame). 0: not new. 1: new, updated in current frame.
amd geode? sc3200 processor data book 281 core logic module - audio registers - function 3 revision 5.1 16 codec status valid. (read only) indicates if the status in bits [15:0] of this r egister is valid. this bi t is high during slots 3 to 11 of the ac97 frame (i.e., for approximately 14.5 s), for every frame. 0: no. 1: yes. 15:0 codec status. (read only) this is the codec status data that is received from the codec in slot 2 on sdata_in. only bits [19:4] are used from slot 2. if this regist er is read with both bits 16 and 17 of this register set to 1, this field is updated in the current ac97 frame, and codec status data is valid. this bit field is updated only if the codec sent status data. offset 0ch-0fh codec command register (r/w) reset value: 00000000h 31:24 codec command address. address of the codec control register for wh ich the command is being sent. this address goes in slot 1 bits [19:12] on sdata_out. 23:22 codec communication. indicates the codec that the core logic module is communicating with. 00: primary codec 01: secondary codec 10: third codec 11: fourth codec only 00 and 01 are valid setti ngs for this bit field. 21:17 reserved. must be set to 0. 16 codec command valid. (read only) indicates if the command in bits [ 15:0] of this register is valid. 0: no. 1: yes. this bit is set by hardware when a codec command is written to the codec command register. it remains set until the com- mand has been sent to the codec. 15:0 codec command. this is the command being sent to the codec in bits [19:4] of slot 2 on sdata_out. offset 10h-11h second level audio smi status register (rc) reset value: 0000h the bits in this register cont ain second level smi status reporting. top level is reported at f1bar0+i/o offset 00h/02h[1]. rea ding this register clear s the status bits at both the second and top levels. note that bit 0 has a third level of status reporting which also must be "read to clear". a read-only ?mirror? version of th is register exists at f3bar0+i/o memory offset 12h. if the valu e of the register must be read without clearing the smi source (and conse quently de-asserting smi), f3bar0+me mory offset 12h can be read instead. 15:8 reserved. must be set to 0. 7 audio bus master 5 smi status. indicates if an smi was caused by an event occurring on audio bus master 5. 0: no. 1: yes. smi generation is enabled when audio bus master 5 is enabled (f3bar0+memory offset 48h[0] = 1). an smi is then generated when the end of page bit is set in the audio bus master 5 smi status register (f3bar0+memory offset 49h[0] = 1). 6 audio bus master 4 smi status. indicates if an smi was caused by an event occurring on audio bus master 4. 0: no. 1: yes. smi generation is enabled when audio bus master 4 is enabled (f3bar0+memory offset 40h[0] = 1). an smi is then generated when the end of page bit is set in the audio bus master 4 smi status register (f3bar0+memory offset 41h[0] = 1). 5 audio bus master 3 smi status. indicates if an smi was caused by an event occurring on audio bus master 3. 0: no. 1: yes. smi generation is enabled when audio bus master 3 is enabled (f3bar0+memory offset 38h[0] = 1). an smi is then generated when the end of page bit is set in the audio bus master 3 smi status register (f3bar0+memory offset 39h[0] = 1). table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
282 amd geode? sc3200 processor data book core logic module - audio registers - function 3 revision 5.1 4 audio bus master 2 smi status. indicates if an smi was caused by an event occurring on audio bus master 2. 0: no. 1: yes. smi generation is enabled when audio bus master 2 is enabled (f3bar0+memory offset 30h[0] = 1). an smi is then generated when the end of page bit is set in the audio bus master 2 smi status register (f3bar0+memory offset 31h[0] = 1). 3 audio bus master 1 smi status. indicates if an smi was caused by an event occurring on audio bus master 1. 0: no. 1: yes. smi generation is enabled when audio bus master 1 is enabled (f3bar0+memory offset 28h[0] = 1). an smi is then generated when the end of page bit is set in the audio bus master 1 smi status register (f3bar0+memory offset 29h[0] = 1). 2 audio bus master 0 smi status. indicates if an smi was caused by an event occurring on audio bus master 0. 0: no. 1: yes. smi generation is enabled when audio bus master 0 is enabled (f3bar0+memory offset 20h[0] = 1). an smi is then generated when the end of page bit is set in the audio bus master 0 smi status register (f3bar0+memory offset 21h[0] = 1). 1 codec serial or gpio interrupt smi status. indicates if an smi was caused by a serial or gpio interrupt from codec. 0: no. 1: yes. smi generation enabling for codec serial interrupt: f3bar0+memory offset 08h[23] = 1. smi generation enabling for codec gpio interrupt: f3bar0+memory offset 00h[30] = 1. 0 i/o trap smi status. indicates if an smi was caused by an i/o trap. 0: no. 1: yes. the next level (third level) of smi status reporting is at f3bar0+memory offset 14h. offset 12h-13h second level audio smi status mirror register (ro) reset value: 0000h note: the bits in this register contain second level smi status re porting. top level is reported at f1bar0+i/o offset 00h/02h[1]. reading this register does not clear the st atus bits. see f3bar0+memory offset 10h. 15:8 reserved. must be set to 0. 7 audio bus master 5 smi status. indicates if an smi was caused by an event occurring on audio bus master 5. 0: no. 1: yes. smi generation is enabled when audio bus master 5 is enabl ed (f3bar0+memory offset 48h[0] = 1). an smi is then gen- erated when the end of page bit is set in the smi status regist er (f3bar0+memory offset 49h[0] = 1). the end of page bit must be cleared before this bit can be cleared. 6 audio bus master 4 smi status. indicates if an smi was caused by an event occurring on audio bus master 4. 0: no. 1: yes. smi generation is enabled when audio bus master 4 is enabl ed (f3bar0+memory offset 40h[0] = 1). an smi is then gen- erated when the end of page bit is set in the smi status regist er (f3bar0+memory offset 41h[0] = 1). the end of page bit must be cleared before this bit can be cleared. 5 audio bus master 3 smi status. indicates if an smi was caused by an event occurring on audio bus master 3. 0: no. 1: yes. smi generation is enabled when audio bus master 3 is enabl ed (f3bar0+memory offset 38h[0] = 1). an smi is then gen- erated when the end of page bit is set in the smi status regist er (f3bar0+memory offset 39h[0] = 1). the end of page bit must be cleared before this bit can be cleared. table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
amd geode? sc3200 processor data book 283 core logic module - audio registers - function 3 revision 5.1 4 audio bus master 2 smi status. indicates if an smi was caused by an event occurring on audio bus master 2. 0: no. 1: yes. smi generation is enabled when audio bus master 2 is enabl ed (f3bar0+memory offset 30h[0] = 1). an smi is then gen- erated when the end of page bit is set in the smi status regist er (f3bar0+memory offset 31h[0] = 1). the end of page bit must be cleared before this bit can be cleared. 3 audio bus master 1 smi status. indicates if an smi was caused by an event occurring on audio bus master 1. 0: no. 1: yes. smi generation is enabled when audio bus master 1 is enabl ed (f3bar0+memory offset 28h[0] = 1). an smi is then gen- erated when the end of page bit is set in the smi status regist er (f3bar0+memory offset 29h[0] = 1). the end of page bit must be cleared before this bit can be cleared. 2 audio bus master 0 smi status. indicates if an smi was caused by an event occurring on audio bus master 0. 0: no. 1: yes. smi generation is enabled when audio bus master 0 is enabl ed (f3bar0+memory offset 20h[0] = 1). an smi is then gen- erated when the end of page bit is set in the smi status regist er (f3bar0+memory offset 21h[0] = 1). the end of page bit must be cleared before this bit can be cleared. 1 codec serial or gpio interrupt smi status. indicates if an smi was caused by a serial or gpio interrupt from codec. 0: no. 1: yes. smi generation enabling for codec serial interrupt: f3bar0+memory offset 08h[23] = 1. smi generation enabling for codec gpio interrupt: f3bar0+memory offset 00h[30] = 1. 0 i/o trap smi status. indicates if an smi was caused by an i/o trap. 0: no. 1: yes. the next level (third level) of smi status reporting is at f3bar0+memory offset 14h. offset 14h-17h i/o trap smi and fast writ e status register (ro/rc) reset value: 00000000h note: for the four smi status bits (bits [13:10 ]), if the activity was a fast write to an even address, no smi is generated regardles s of the dma, mpu, or sound card status. if the activity was a fa st write to an odd address, an smi is generated but bit 13 is set t o a 1. 31:24 fast path write even access data. (read only) this bit field contains the data from the last fast path write even access. these bits change only on a fast write to an even address. 23:16 fast path write odd access data. (read only) this bit field contains the data from the last fast path write odd access. these bits change on a fast write to an odd address, and also on any non-fast write. 15 fast write a1. (read only) this bit contains the a1 value for the last fast write access. 14 read or write i/o access. (read only) indicates if the last trapped i/o access was a read or a write. 0: read. 1: write. 13 sound card or fm trap smi status. (read to clear) indicates if an smi was caused by a trapped i/o access to the sound card or fm i/o trap. 0: no. 1: yes. (see the note included in the general description of this register above.) fast path write must be enabled, f3bar0+memory offset 18h[11] = 1, for the smi to be reported here. if fast path write is disabled, the smi is reported in bit 10 of this register. this is the third level of smi status reporting. second level smi status is reported at f3bar0+memory offset 10h/12h[0]. top level is reported at f1bar0+i/o offset 00h/02h[1]. smi generation enabling is at f3bar0+memory offset 18h[2]. table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
284 amd geode? sc3200 processor data book core logic module - audio registers - function 3 revision 5.1 12 dma trap smi status. (read to clear) indicates if an smi was caused by a trapped i/o access to the dma i/o trap. 0: no. 1: yes. (see the note included in the general description of this register above.) this is the third level of smi status reporting. second level smi status is reported at f3bar0+memory offset 10h/12h[0]. top level is reported at f1bar0+i/o offset 00h/02h[1]. smi generation enabling is at f3bar0+memory offset 18h[8:7]. 11 mpu trap smi status. (read to clear) indicates if an smi was caused by a tr apped i/o access to the mpu i/o trap. 0: no. 1: yes. (see the note included in the general description of this register above.) this is the third level of smi status reporting. second level of smi status is reported at f3bar0+memory offset 10h/12h[0]. top level is reported at f1bar0+i/o offset 00h/02h[1]. smi generation enabling is at f3bar0+memory offset 18h[6:5]. 10 sound card or fm trap smi status. (read to clear) indicates if an smi was caused by a trapped i/o access to the sound card or fm i/o trap. 0: no. 1: yes. (see the note included in the general description of this register above.) fast path write must be disabled, f3bar0+memory offset 18h[11] = 0, for the smi to be reported here. if fast path write is enabled, the smi is reported in bit 13 of this register. this is the third level of smi status reporting. second level of smi status is reported at f3bar0+memory offset 10h/12h[0]. top level is reported at f1bar0+i/o offset 00h/02h[1]. smi generation enabling is at f3bar0+memory offset 18h[2]. 9:0 x-bus address (read only). this bit field] contains the c aptured ten bits of x-bus address. offset 18h-19h i/o trap smi enable register (r/w )reset value: 0000h 15:12 reserved. must be set to 0. 11 fast path write enable. fast path write (an smi is not generated on certain writes to specified addresses). 0: disable. 1: enable. in fast path write, the core logic module responds to writes to addresses: 388h, 38ah, 38b, 2x0h, 2x2h, and 2x8h. 10:9 fast read. these two bits hold part of the response that the core logic module returns for reads to several i/o locations. 8 high dma i/o trap. if this bit is enabled and an access occurs at i/o port c0h-dfh, an smi is generated. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[1]. second level smi status is reported at f3bar0+memory offset 10h/12h[0]. third level smi status is reported at f3bar0+memory offset 14h[12]. 7 low dma i/o trap. if this bit is enabled and an access occurs at i/o port 00h-0fh, an smi is generated. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[1]. second level smi status is reported at f3bar0+memory offset 10h/12h[0]. third level smi status is reported at f3bar0+memory offset 14h[12]. 6 high mpu i/o trap. if this bit is enabled and an access occu rs at i/o port 330h-331h, an smi is generated. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[1]. second level smi status is reported at f3bar0+memory offset 10h/12h[0]. third level smi status is reported at f3bar0+memory offset 14h[11]. table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
amd geode? sc3200 processor data book 285 core logic module - audio registers - function 3 revision 5.1 5 low mpu i/o trap. if this bit is enabled and an access occurs at i/o port 300h-301h, an smi is generated. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[1]. second level smi status is reported at f3bar0+memory offset 10h/12h[0]. third level smi status is reported at f3bar0+memory offset 14h[11]. 4 fast path read enable/smi disable. when asserted, read fast path (an smi is not generated on reads from specified addresses). 0: disable. 1: enable. in fast path read the core logic module responds to reads of addresses: 388h-38bh; 2x0h, 2x1, 2x2h, 2x3, 2x8 and 2x9h. if neither sound card nor fm i/o mapping is enab led, then status read trapping is not possible. 3 fm i/o trap. if this bit is enabled and an access occurs at i/o port 388h-38bh, an smi is generated. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[1]. second level smi status is reported at f3bar0+memory offset 10h/12h[0]. 2 sound card i/o trap. if this bit is enabled and an access occurs in the addr ess ranges selected by bits [1:0], an smi is generated. 0: disable. 1: enable. top level smi status is reported at f1bar0+i/o offset 00h/02h[1]. second level smi status is reported at f3bar0+memory offset 10h/12h[0]. third level smi status is reported at f3bar0+memory offset 14h[10]. 1:0 sound card address range select. these bits select the address range for the sound card i/o trap. 00: i/o port 220h-22fh 10: i/o port 260h-26fh 01: i/o port 240h-24fh 11: i/o port 280h-28fh offset 1ah-1bh internal irq enable register (r/w) reset value: 0000h 15 irq15 internal. configures irq15 for internal (so ftware) or external (hardware) use. 0: external. 1: internal. 14 irq14 internal. configures irq14 for internal (so ftware) or external (hardware) use. 0: external. 1: internal. 13 reserved. must be set to 0. 12 irq12 internal. configures irq12 for internal (so ftware) or external (hardware) use. 0: external. 1: internal. 11 irq11 internal. configures irq11 for internal (software) or external (hardware) use. 0: external. 1: internal. 10 irq10 internal. configures irq10 for internal (so ftware) or external (hardware) use. 0: external. 1: internal. 9 irq9 internal. configures irq9 for internal (so ftware) or external (hardware) use. 0: external. 1: internal. 8 reserved. must be set to 0. table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
286 amd geode? sc3200 processor data book core logic module - audio registers - function 3 revision 5.1 7 irq7 internal. configures irq7 for internal (so ftware) or external (hardware) use. 0: external. 1: internal. 6 reserved. must be set to 0. 5 irq5 internal. configures irq5 for internal (so ftware) or external (hardware) use. 0: external. 1: internal. 4 irq4 internal. configures irq4 for internal (so ftware) or external (hardware) use. 0: external. 1: internal. 3 irq3 internal. configures irq3 for internal (so ftware) or external (hardware) use. 0: external. 1: internal. 2 reserved. must be set to 0. 1 irq1 internal. configures irq1 for internal (so ftware) or external (hardware) use. 0: external. 1: internal. 0 reserved. must be set to 0. offset 1ch-1fh internal irq contro l register (r/w) reset value: 00000000h note: bits 31:16 of this register are write only. r eads to these bits always return a value of 0. 31 mask internal irq15. (write only) 0: disable. 1: enable. 30 mask internal irq14. (write only) 0: disable. 1: enable. 29 reserved. (write only) must be set to 0. 28 mask internal irq12. (write only) 0: disable. 1: enable. 27 mask internal irq11. (write only) 0: disable. 1: enable. 26 mask internal irq10. (write only) 0: disable. 1: enable. 25 mask internal irq9. (write only) 0: disable. 1: enable. 24 reserved. (write only) must be set to 0. 23 mask internal irq7. (write only) 0: disable. 1: enable. 22 reserved. (write only) must be set to 0. 21 mask internal irq5. (write only) 0: disable. 1: enable. table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
amd geode? sc3200 processor data book 287 core logic module - audio registers - function 3 revision 5.1 20 mask internal irq4. (write only) 0: disable. 1: enable. 19 mask internal irq3. (write only) 0: disable. 1: enable. 18 reserved. (write only) must be set to 0. 17 mask internal irq1. (write only) 0: disable. 1: enable. 16 reserved. (write only) must be set to 0. 15 assert masked internal irq15. 0: disable. 1: enable. 14 assert masked internal irq14. 0: disable. 1: enable. 13 reserved. set to 0. 12 assert masked internal irq12. 0: disable. 1: enable. 11 assert masked internal irq11. 0: disable. 1: enable. 10 assert masked internal irq10. 0: disable. 1: enable. 9 assert masked internal irq9. 0: disable. 1: enable. 8 reserved. set to 0. 7 assert masked internal irq7. 0: disable. 1: enable. 6 reserved. set to 0. 5 assert masked internal irq5. 0: disable. 1: enable. 4 assert masked internal irq4. 0: disable. 1: enable. 3 assert masked internal irq3. 0: disable. 1: enable. 2 reserved. must be set to 0. table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
288 amd geode? sc3200 processor data book core logic module - audio registers - function 3 revision 5.1 1 assert masked internal irq1. 0: disable. 1: enable. 0 reserved. must be set to 0. offset 20h audio bus master 0 command register (r/w) reset value: 00h audio bus master 0: output to codec; 32-bit; left and right channels; slots 3 and 4. 7:4 reserved. must be set to 0. must return 0 on reads. 3 read or write control. sets the transfer direction of the audio bus master. 0: pci reads are performed. 1: pci writes are performed. this bit must be set to 0 (read), and should not be changed when the bus master is active. 2:1 reserved. must be set to 0. must return 0 on reads. 0 bus master control. controls the state of the audio bus master. 0: disable. 1: enable. setting this bit to 1 enables the bus master to begin data transfers. when writing 0 to this bit, the bus master must either be paused, or reach eot. writing 0 to this bit while the bus master is operating may result in unpredictable behavi or (and may crash the bus master state ma chine). the only recovery from such unpredictable behavior is a pci reset. offset 21h audio bus master 0 smi status register (rc) reset value: 00h audio bus master 0: output to codec; 32-bit; left and right channels; slots 3 and 4. 7:2 reserved. 1 bus master error. indicates if hardware encountered a second eop before software has cleared the first. 0: no. 1: yes. if hardware encounters a second eop (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 end of page. indicates if the bus master transferred data which is marked by eop bit in the prd table (bit 30). 0: no. 1: yes. offset 22h-23h not used offset 24h-27h audio bus master 0 p rd table address (r/w) reset value: 00000000h audio bus master 0: output to codec; 32-bit; left and right channels; slots 3 and 4. 31:2 pointer to the physical region descriptor table. this bit field contains a prd tabl e pointer for audio bus master 0. when written, this register points to the first entry in a prd table. once audio bus master 0 is enabled (command register bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next prd. when read, this register points to the next prd. 1:0 reserved. must be set to 0. note: the physical region descriptor (prd) tabl e consists of one or more entries - eac h describing a memory region to or from which data is to be transferred. ea ch entry consists of two dwords. dword 0: [31:0] = memory region physical base address dword 1: 31 = end of table flag 30 = end of page flag 29 = loop flag (jmp) [28:16] = reserved (0) [15:0] = byte count of the region (size) table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
amd geode? sc3200 processor data book 289 core logic module - audio registers - function 3 revision 5.1 offset 28h audio bus master 1 command register (r/w) reset value: 00h audio bus master 1: input from codec; 32-bit; left and right channels; slots 3 and 4. 7:4 reserved. must be set to 0. must return 0 on reads. 3 read or write control. set the transfer direction of audio bus master 1. 0: pci reads are performed. 1: pci writes are performed. this bit must be set to 1 (write) and should not be changed when the bus master is active. 2:1 reserved. must be set to 0. must return 0 on reads. 0 bus master control. controls the state of the audio bus master 1. 0: disable. 1: enable. setting this bit to 1 enables the bus master to begin data transfe rs. when writing this bit to 0, the bus master must be either paused or reached eot. writing this bi t to 0 while the bus master is operating results in unpredictable behavior (and may cause a crash of the bus master st ate machine). the only recovery from this condition is a pci reset. offset 29h audio bus master 1 smi status register (rc) reset value: 00h audio bus master 1: input from codec; 32-bit; left and right channels; slots 3 and 4. 7:2 reserved. 1 bus master error. indicates if hardware encountered a second eop before software has cleared the first. 0: no. 1: yes. if hardware encounters a second eop (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 end of page. indicates if the bus master transferred data which is marked by eop bit in the prd table (bit 30). 0: no. 1: yes. offset 2ah-2bh not used offset 2ch-2fh audio bus master 1 prd table address (r/w) reset value: 00000000h audio bus master 1: input from codec; 32-bit; left and right channels; slots 3 and 4. 31:2 pointer to the physical region descriptor table. this bit field is a prd table pointer for audio bus master 1. when written, this register points to the first entry in a prd table. once audio bus master 1 is enabled (command register bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next prd. when read, this register points to the next prd. 1:0 reserved. must be set to 0. note: the physical region descriptor (prd) tabl e consists of one or more entries - eac h describing a memory region to or from which data is to be transferred. ea ch entry consists of two dwords. dword 0: [31:0] = memory region physical base address dword 1: 31 = end of table flag 30 = end of page flag 29 = loop flag (jmp) [28:16] = reserved (0) [15:0] = byte count of the region (size) table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
290 amd geode? sc3200 processor data book core logic module - audio registers - function 3 revision 5.1 offset 30h audio bus master 2 command register (r/w) reset value: 00h audio bus master 2: output to codec; 16-bit; slot 5. 7:4 reserved. must be set to 0. must return 0 on reads. 3 read or write control. sets the transfer direction of audio bus master 2. 0: pci reads are performed. 1: pci writes are performed. this bit must be set to 0 (read) and should not be changed when the bus master is active. 2:1 reserved. must be set to 0. must return 0 on reads. 0 bus master control. controls the state of the audio bus master 2. 0: disable. 1: enable. setting this bit to 1 enables the bus master to begin data transfe rs. when writing 0 to this bit, the bus master must be either paused or reached eot. writing 0 to this bit while the bus master is operating results in unpredictable behavior (and may crash the bus master state machine). the only re covery from this condition is a pci reset. offset 31h audio bus master 2 smi status register (rc) reset value: 00h audio bus master 2: output to codec; 16-bit; slot 5. 7:2 reserved. 1 bus master error. indicates if hardware encountered a second eop before software has cleared the first. 0: no. 1: yes. if hardware encounters a second eop (end of page) before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 end of page. indicates if the bus master transferred data which is marked by the eop bit in the prd table (bit 30). 0: no. 1: yes. offset 32h-33h not used reset value: 00h offset 34h-37h audio bus master 2 p rd table address (r/w) reset value: 00000000h audio bus master 2: output to codec; 16-bit; slot 5. 31:2 pointer to the physical region descriptor table. this bit field contains a prd tabl e pointer for audio bus master 2. when written, this field points to the first entry in a prd ta ble. once audio bus master 2 is enabled (command register bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next prd. when read, this register points to the next prd. 1:0 reserved. must be set to 0. note: the physical region descriptor (prd) tabl e consists of one or more entries - eac h describing a memory region to or from which data is to be transferred. ea ch entry consists of two dwords. dword 0: [31:0] = memory region physical base address dword 1: 31 = end of table flag 30 = end of page flag 29 = loop flag (jmp) [28:16] = reserved (0) [15:0] = byte count of the region (size) table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
amd geode? sc3200 processor data book 291 core logic module - audio registers - function 3 revision 5.1 offset 38h audio bus master 3 command register (r/w) reset value: 00h audio bus master 3: input from codec; 16-bit; slot 5. 7:4 reserved. must be set to 0. must return 0 on reads. 3 read or write control. sets the transfer direction of audio bus master 3. 0: pci reads are performed. 1: pci writes are performed. this bit must be set to 1 (write) and should not be changed when the bus master is active. 2:1 reserved. must be set to 0. must return 0 on reads. 0 bus master control. controls the state of the audio bus master 3. 0: disable. 1: enable. setting this bit to 1 enables the bus master to begin data transfe rs. when writing 0 to this bit, the bus master must be either paused or have reached eot. writing 0 to this bit while t he bus master is operating resu lts in unpredictable behavior (and may crash the bus master state machine). the only recovery from this condition is a pci reset. offset 39h audio bus master 3 smi status register (rc) reset value: 00h audio bus master 3: input from codec; 16-bit; slot 5. 7:2 reserved. 1 bus master error. indicates if hardware encountered a sec ond eop before software cleared the first. 0: no. 1: yes. if hardware encounters a second eop (end of page) before softwar e cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 end of page. indicates if the bus master transferred data which is marked by the eop bit in the prd table (bit 30). 0: no. 1: yes. offset 3ah-3bh not used offset 3ch-3fh audio bus master 3 prd table address (r/w) reset value: 00000000h audio bus master 3: input from codec; 16-bit; slot 5. 31:2 pointer to the physical region descriptor table. this bit field contains is a prd table pointer for audio bus master 3. when written, this field points to the first entry in a prd ta ble. once audio bus master 3 is enabled (command register bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next prd. when read, this register points to the next prd. 1:0 reserved. must be set to 0. note: the physical region descriptor (prd) tabl e consists of one or more entries - eac h describing a memory region to or from which data is to be transferred. ea ch entry consists of two dwords. dword 0: [31:0] = memory region physical base address dword 1: 31 = end of table flag 30 = end of page flag 29 = loop flag (jmp) [28:16] = reserved (0) [15:0] = byte count of the region (size) table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
292 amd geode? sc3200 processor data book core logic module - audio registers - function 3 revision 5.1 offset 40h audio bus master 4 command register (r/w) reset value: 00h audio bus master 4: output to codec; 16-bit; slot 6 or 11 (f3bar0+memory offset 08h[19] selects slot). 7:4 reserved. must be set to 0. must return 0 on reads. 3 read or write control. set the transfer direction of audio bus master 4. 0: pci reads are performed. 1: pci writes are performed. this bit must be set to 0 (read) and should not be changed when the bus master is active. 2:1 reserved. must be set to 0. must return 0 on reads. 0 bus master control. controls the state of the audio bus master 4. 0: disable. 1: enable. setting this bit to 1 enables the bus master to begin data transfe rs. when writing 0 to this bit, the bus master must be either paused or have reached eot. writing 0 to this bit while t he bus master is operating, results in unpredictable behavior (and may crash the bus master state machine). the only recovery from this condition is a pci reset. offset 41h audio bus master 4 smi status register (rc) reset value: 00h audio bus master 4: output to codec; 16-bit; slot 6 or 11 (f3bar0+memory offset 08h[19] selects slot). 7:2 reserved. 1 bus master error. indicates if hardware encountered a sec ond eop before software cleared the first. 0: no. 1: yes. if hardware encounters a second eop (end of page) before softwar e cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 end of page. bus master transferred data which is marked by the eop bit in the prd table (bit 30). 0: no. 1: yes. offset 42h-43h not used offset 44h-47h audio bus master 4 p rd table address (r/w) reset value: 00000000h audio bus master 4: output to codec; 16-bit; slot 6 or 11 (f3bar0+memory offset 08h[19] selects slot). 31:2 pointer to the physical region descriptor table. this register is a prd table pointer for audio bus master 4. when written, this register points to the first entry in a prd table. once audio bus master 4 is enabled (command register bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next prd. when read, this register points to the next prd. 1:0 reserved. must be set to 0. note: the physical region descriptor (prd) tabl e consists of one or more entries - eac h describing a memory region to or from which data is to be transferred. ea ch entry consists of two dwords. dword 0: [31:0] = memory region physical base address dword 1: 31 = end of table flag 30 = end of page flag 29 = loop flag (jmp) [28:16] = reserved (0) [15:0] = byte count of the region (size) table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
amd geode? sc3200 processor data book 293 core logic module - audio registers - function 3 revision 5.1 offset 48h audio bus master 5 command register (r/w) reset value: 00h audio bus master 5: input from codec; 16-bit; slot 6 or 11 (f3bar0+memory offset 08h[20] selects slot). 7:4 reserved. must be set to 0. must return 0 on reads. 3 read or write control. set the transfer direction of audio bus master 5. 0: pci reads are performed. 1: pci writes are performed. this bit must be set to 1 (write) and should not be changed when the bus master is active. 2:1 reserved. must be set to 0. must return 0 on reads. 0 bus master control. controls the state of the audio bus master 5. 0: disable. 1: enable. setting this bit to 1 enables the bus master to begin data transfe rs. when writing 0 to this bit, the bus master must be either paused or have reached eot. writing 0 to this bit while t he bus master is operating, results in unpredictable behavior (and may crash the bus master state machine). the only recovery from this condition is a pci reset. offset 49h audio bus master 5 smi status register (rc) reset value: 00h audio bus master 5: input from codec; 16-bit; slot 6 or 11 (f3bar0+memory offset 08h[20] selects slot). 7:2 reserved. 1 bus master error. indicates if hardware encountered a sec ond eop before software cleared the first. 0: no. 1: yes. if hardware encounters a second eop (end of page) before softwar e cleared the first, it causes the bus master to pause until this register is read to clear the error. 0 end of page. indicates if the bus master transferred data which is marked by the eop bit in the prd table (bit 30). 0: no. 1: yes. offset 4ah-4bh not used offset 4ch-4fh audio bus master 5 prd table address (r/w) reset value: 00000000h audio bus master 5: input from codec; 16-bit; slot 6 or 11 (f3bar0+memory offset 08h[20] selects slot). 31:2 pointer to the physical region descriptor table. this bit field contains a prd tabl e pointer for audio bus master 5. when written, this register points to the first entry in a prd table. once audio bus master 5 is enabled (command register bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next prd. when read, this register points to the next prd. 1:0 reserved. must be set to 0. note: the physical region descriptor (prd) tabl e consists of one or more entries - eac h describing a memory region to or from which data is to be transferred. ea ch entry consists of two dwords. dword 0: [31:0] = memory region physical base address dword 1: 31 = end of table flag 30 = end of page flag 29 = loop flag (jmp) [28:16] = reserved (0) [15:0] = byte count of the region (size) table 6-38. f3bar0+memory offset: audio configuration registers (continued) bit description
294 amd geode? sc3200 processor data book core logic module - x-bus expansion interface - function 5 revision 5.1 6.4.5 x-bus expansion interface - function 5 the register space designated as function 5 (f5) is used to configure the pci portion of support hardware for accessing the x-bus expansion support registers. the bit formats for the pci header registers are given in table 6- 39. located in the pci header registers of f5 are six base address registers (f5barx) used for pointing to the regis- ter spaces designated for x-bus expansion support, described later in this section. table 6-39. f5: pci header registers for x-bus expansion bit description index 00h-01h vendor identification register (ro) reset value: 100bh index 02h-03h device identification register (ro) reset value: 0505h index 04h-05h pci command register (r/w) reset value: 0000h 15:2 reserved. (read only) 1 memory space. allow the core logic module to respond to memory cycles from the pci bus. 0: disable. 1: enable. if f5bar0, f5bar1, f5bar2, f5bar3, f5bar4, and f5bar5 (f5 index 10h, 14h, 18h, 1ch, 20h, and 24h) are defined as allowing access to memory mapped registers, this bit must be set to 1. bar configuration is programmed through the corre- sponding mask register (see f5 index 40h, 44h, 48h, 4ch, 50h, and 54h) 0 i/o space. allow the core logic module to re spond to i/o cycle from the pci bus. 0: disable. 1: enable. if f5bar0, f5bar1, f5bar2, f5bar3, f5bar4, and f5bar5 (f5 index 10h, 14h, 18h, 1ch, 20h, and 24h) are defined as allowing access to i/o mapped registers, this bit must be se t to 1. bar configuration is programmed through the corre- sponding mask register (see f5 index 40h, 44h, 48h, 4ch, 50h, and 54h) index 06h-07h pci status register (ro) reset value: 0280h index 08h device revision id register (ro) reset value: 00h index 09h-0bh pci class code register (ro) reset value: 068000h index 0ch pci cache line size register (ro) reset value: 00h index 0dh pci latency timer register (ro) reset value: 00h index 0eh pci header type (ro) reset value: 00h index 0fh pci bist register (ro) reset value: 00h index 10h-13h base address register 0 - f5bar0 (r/w) reset value: 00000000h x-bus expansion address space. this register allows pci acce ss to i/o mapped x-bus expansion s upport registers. bits [5:0] must be set to 000001, indicating a 64-byte aligned i/o address space. refer to table 6-40 on page 298 for the x-bus expansion confi gura- tion register bit formats and reset values. note: the size and type of accessed offsets can be reprog rammed through f5bar0 mask register (f5 index 40h). 31:6 x-bus expansion base address. 5:0 address range. this bit field must be set to 000001 for this register to operate correctly. index 14h-17h base address register 1 - f5bar1 (r/w) reset value: 00000000h reserved. reserved for possible future use by the core logic module. configuration of this regist er is programmed through the f5bar1 mask register (f5 index 44h) index 18h-1bh base address register 2 - f5bar2 (r/w) reset value: 00000000h reserved. reserved for possible future use by the core logic module. configuration of this regist er is programmed through the f5bar1 mask register (f5 index 48h)
amd geode? sc3200 processor data book 295 core logic module - x-bus expansion interface - function 5 revision 5.1 index 1ch-1fh base address register 3 - f5bar3 (r/w) reset value: 00000000h reserved. reserved for possible future use by the core logic module. configuration of this register is programmed th rough the f5bar3 mask register (f5 index 4ch). index 20h-23h base address register 4 - f5bar4 (r/w) reset value: 00000000h reserved. reserved for possible future use by the core logic module. configuration of this register is programmed through the f5bar4 mask register (f5 index 50h). index 24h-27h base address register 5 - f5bar5 (r/w) reset value: 00000000h reserved. reserved for possible future use by the core logic module. configuration of this register is programmed through the f5bar5 mask register (f5 index 54h). index 28h-2bh reserved reset value: 00h index 2ch-2dh subsystem vendor id (ro) reset value: 100bh index 2eh-2fh subsystem id (ro) reset value: 0505h index 30h-3fh reserved reset value: 00h index 40h-43h f5bar0 mask address register (r/w) reset value: ffffffc1h to use f5bar0, the mask register should be programmed first. the mask register def ines the size of f5bar0 and whether the accessed offset registers are memory or i/o mapped. note: whenever a value is written to this mask register, f5bar0 must also be written (even if the value for f5bar0 has not changed). memory base address register (bit 0 = 0) 31:4 address mask. determines the size of the bar. ? every bit that is a 1 is programmable in the bar. ? every bit that is a 0 is fixed 0 in the bar. since the address mask goes down to bit 4, the smallest memory region is 16 bytes, however, the pci specification sug- gests not using less than a 4 kb address range. 3 prefetchable . indicates whether or not the data in me mory is prefetchable. this bit should be set to 1 only if all the following are true: ? there are no side-effects from reads (i.e., the data at the location is not changed as a result of the read). ? the device returns all bytes regardless of the byte enables. ? host bridges can merge processor writes into this range without causing errors. ? the memory is not cached from the host processor. 0: data is not prefetchable. this value is recommended if one or more of the above listed conditions is not true. 1: data is prefetchable. 2:1 type. 00: located anywhere in the 32-bit address space 01: located below 1 mb 10: located anywhere in the 64-bit address space 11: reserved 0 this bit must be set to 0, to indicate memory base address register. i/o base address register (bit 0 = 1) 31:2 address mask. determines the size of the bar. ? every bit that is a 1 is programmable in the bar. ? every bit that is a 0 is fixed 0 in the bar. since the address mask goes down to bit 2, the smallest i/o region is 4 bytes, howe ver, the pci specification suggests not using less than a 4 kb address range. 1 reserved. must be set to 0. 0 this bit must be set to 1, to i ndicate an i/o base address register. table 6-39. f5: pci header registers for x-bus expansion (continued) bit description
296 amd geode? sc3200 processor data book core logic module - x-bus expansion interface - function 5 revision 5.1 index 44h-47h f5bar1 mask address register (r/w) reset value: 00000000h to use f5bar1, the mask register should be programmed first. the mask register def ines the size of f5bar1 and whether the accessed offset registers are memory or i/o mapped. see f5 index 40h (f5bar0 mask address register) above for bit descriptions. note: whenever a value is written to this mask register, f5bar1 must also be written (even if the value for f5bar1 has not changed). index 48h-4bh f5bar2 mask address register (r/w) reset value: 00000000h to use f5bar2, the mask register should be programmed first. the mask register def ines the size of f5bar2 and whether the accessed offset registers are memory or i/o mapped. see f5 index 40h (f5bar0 mask address register) above for bit descriptions. note: whenever a value is written to this mask register, f5bar2 must also be written (even if the value for f5bar2 has not changed). index 4ch-4fh f5bar3 mask address register (r/w) reset value: 00000000h to use f5bar3, the mask register should be programmed first. the mask register def ines the size of f5bar3 and whether the accessed offset registers are memory or i/o mapped. see f5 index 40h (f5bar0 mask address register) above for bit descriptions. note: whenever a value is written to this mask register, f5bar3 must also be written (even if the value for f5bar3 has not changed). index 50h-53h f5bar4 mask address register (r/w) reset value: 00000000h to use f5bar4, the mask register should be programmed first. the mask register def ines the size of f5bar4 and whether the accessed offset registers are memory or i/o mapped. see f5 index 40h (f5bar0 mask address register) above for bit descriptions. note: whenever a value is written to this mask register, f5bar4 must also be written (even if the value for f5bar4 has not changed). index 54h-57h f5bar5 mask address register (r/w) reset value: 00000000h to use f5bar5, the mask register should be programmed first. the mask register def ines the size of f5bar5 and whether the accessed offset registers are memory or i/o mapped. see f5 index 40h (f5bar0 mask address register) above for bit descriptions. note: whenever a value is written to this mask register, f5bar5 must also be written (even if the value for f5bar5 has not changed). index 58h f5barx initialized register (r/w) reset value: 00h 7:6 reserved. must be set to 0. 5 f5bar5 initialized. this bit indicates if f5bar5 (f5 index 24h) has been initialized. at reset this bit is cleared (0). writing f5bar5 sets this bit to 1. if this bit pr ogrammed to 0, the decoding of f5bar5 is dis - abled until either this bit is set to 1 or f5bar5 is written (which causes this bit to be set to 1). 4 f5bar4 initialized. this bit indicates if f5bar4 (f5 index 28h) has been initialized. at reset this bit is cleared (0). writing f5bar4 sets this bit to 1. if this bit pr ogrammed to 0, the decoding of f5bar4 is dis - abled until either this bit is set to 1 or f5bar4 is written (which causes this bit to be set to 1). 3 f5bar3 initialized. this bit indicates if f5bar3 (f5 index 1ch) has been initialized. at reset this bit is cleared (0). writing f5bar3 sets this bit to 1. if this bit pr ogrammed to 0, the decoding of f5bar3 is dis - abled until either this bit is set to 1 or f5bar3 is written (which causes this bit to be set to 1). 2 f5bar2 initialized. this bit indicates if f5bar2 (f5 index 18h) has been initialized. at reset this bit is cleared (0). writing f5bar2 sets this bit to 1. if this bit pr ogrammed to 0, the decoding of f5bar2 is dis - abled until either this bit is set to 1 or f5bar2 is written (which causes this bit to be set to 1). 1 f5bar1 initialized. this bit indicates if f5bar1 (f5 index 14h) has been initialized. at reset this bit is cleared (0). writing f5bar1 sets this bit to 1. if this bit pr ogrammed to 0, the decoding of f5bar1 is dis - abled until either this bit is set to 1 or f5bar1 is written (which causes this bit to be set to 1). 0 f5bar0 initialized. this bit indicates if f5bar0 (f5 index 10h) has been initialized. at reset this bit is cleared (0). writing f5bar0 sets this bit to 1. if this bit pr ogrammed to 0, the decoding of f5bar0 is dis - abled until either this bit is set to 1 or f5bar0 is written (which causes this bit to be set to 1). index 59h-5fh reserved reset value: xxh index 60h-63h scratchpad: usually used for device number (r/w) reset value: 00000000h bios writes a value, of the device number. expected value: 00003200h. table 6-39. f5: pci header registers for x-bus expansion (continued) bit description
amd geode? sc3200 processor data book 297 core logic module - x-bus expansion interface - function 5 revision 5.1 index 64h-67h scratchpad: usually used for co nfiguration block address (r/w) reset value: 00000000h bios writes a value, of t he configuration block address. index 68h-ffh reserved table 6-39. f5: pci header registers for x-bus expansion (continued) bit description
298 amd geode? sc3200 processor data book core logic module - x-bus expansion interface - function 5 revision 5.1 6.4.5.1 x-bus expansio n support registers f5 index 10h, base address register 0 (f5bar0) set the base address that allows pci access to additional i/o con- trol support registers. table 6-40 shows the support regis- ters accessed through f5bar0. table 6-40. f5bar0+i/o offset: x-bus expansion registers bit description offset 00h-03h i/o control regist er 1 (r/w) reset value: 010c0007h 31:28 reserved. 27 io_enable_sio_ir (enable integrated sio infrared). 0: disable. 1: enable. 26:25 io_siocfg_in (integrated sio input configuration). these two bits can be used to disable the integrated sio totally or limit/control the base address. 00: integrated sio disable. 01: integrated sio configuration access disable. 10: integrated sio base address 02eh/02fh enable. 11: integrated sio base address 015ch/015dh enable. 24 io_enable_sio_driving_isa_bus (enable integrated sio isa bus control). allow the integrated sio to drive the internal isa bus. 0: disable. 1: enable. (default) 23:21 reserved. set to 0. 20 io_usb_smi_pwm_en (usb internal smi). route usb-generated smi to smi status register in f1bar0+i/o offset 00h/02h[14]. 0: disable. 1: enable. 19 io_usb_smi_en (usb smi configuration). allow usb-generated smis. 0: disable 1: enable. if bits 19 and 20 are enabled, the smi generated by the usb is reported via the top level smi status register at f1bar0+i/ o offset 00h/02h[14]. if only bit 19 is enabled, the usb can generate an smi but there is no status reporting. 18 io_usb_pci_en (usb). enables usb ports. 0: disable. 1: enable. 17:0 reserved.
amd geode? sc3200 processor data book 299 core logic module - x-bus expansion interface - function 5 revision 5.1 offset 04h-07h i/o control regi ster 2 (r/w) reset value: 00000002h 31:2 reserved. write as read. 1 video processor access enable. allows access to video processor using f4bar0. 0: disable. 1: enable. (default) note: this bit is readable after the register (f5bar0+offset 04h) has been written once. 0 io_strap_idsel_select (i dsel strap override). 0: idsel: ad28 for chipset register space (f0- f5), ad29 for usb register space (pciusb). 1: idsel: ad26 for chipset register space (f0- f5), ad27 for usb register space (pciusb). offset 08h-0bh i/o control regi ster 3 (r/w) reset value: 00009000h 31:16 reserved. write as read. 15:13 io_usb_xcvr_vadj (usb voltage adjustment connection). these bits connect to the voltage adjustment interface on the three usb transceivers. default = 100. 12:8 io_usb_xcvt_cadj (usb current adjustment). these bits connect to the current adjustment interface on the three usb transceivers. default = 10000. 7 io_test_port_en (debug test port enable). 0: disable 1: enable 6:0 io_test_port_reg (debug port pointer). these bits are used to point to the 16-bit slice of the test port bus. table 6-40. f5bar0+i/o offset: x-bus expansion registers (continued) bit description
300 amd geode? sc3200 processor data book core logic module - usb controller registers - pciusb revision 5.1 6.4.6 usb controller registers - pciusb the registers designated as pciusb are 32-bit registers decoded from the pci address bits [7:2] and c/be[3:0]#, when idsel is high, ad[10:8] select the appropriate func- tion, and ad[1:0] are 00. the pci configuration registers are listed in table 6-41. they can be accessed as any number of bytes within a sin- gle 32-bit aligned unit. they are selected by the pci-stan- dard index and byte-enable method. in the pci configuration space, there is one base address register (bar), at index 10h, which is used to map the usb host controller's operational register set into a 4k memory space. once the bar register has been initialized, and the pci command register at index 04h has been set to enable the memory space decoder, these ?usb control- ler? registers are accessible. the memory-mapped usb controller registers are listed in table 6-42. they follow the open host controller interface (ohci) specification. regist ers marked as ?reserved?, and reserved bits within a register, should not be changed by software. table 6-41. pciusb: usb pc i configuration registers bit description index 00h-01h vendor identification register (ro) reset value: 0e11h index 02h-03h device identification register (ro) reset value: a0f8h index 04h-05h command register (r/w) reset value: 00h 15:10 reserved. must be set to 0. 9 fast back-to-back enable. (read only) usb only acts as a master to a single device, so this functionality is not needed. it is always disabled (i.e., this bit must always be set to 0). 8 serr#. when this bit is enabled, usb asserts ser r# when it detects an address parity error. 0: disable. 1: enable. 7 wait cycle control. usb does not need to insert a wait state between the address and data on the ad lines. it is always disabled (i.e., this bit is set to 0). 6 parity error. usb asserts perr# when it is the agent rece iving data and it detects a data parity error. 0: disable. 1: enable. 5 vga palette snoop enable. (read only) usb does not support this function. it is al ways disabled (i.e., this bit is set to 0). 4 memory write and invalidate. allow usb to run memory write and invalidate commands. 0: disable. 1: enable. the memory write and invalidate command only occurs if the ca che-line size is set to 32 bytes and the memory write is exactly one cache line. this bit must be set to 0. 3 special cycles. usb does not run special cycles on pci. it is al ways disabled (i.e., this bit is set to 0). 2 pci master enable . allow the usb to run pci master cycles. 0: disable. 1: enable. 1 memory space. allow the usb to respond as a target to memory cycles from the pci bus. 0: disable. 1: enable. 0 i/o space. allow the usb to respond as a target to i/o cycles from the pci bus. 0disable. 1: enable.
amd geode? sc3200 processor data book 301 core logic module - usb controller registers - pciusb revision 5.1 index 06h-07h status register (r/w) reset value: 0280h the pci specification defines this register to record status information for pci rela ted events. this is a read/write register. however, writes can only reset bits. a bit is reset whenever the regist er is written and the data in t he corresponding bit location is a 1. 15 detected parity error . this bit is set to 1 whenever the usb detects a parity error, even if the parity error (response) detection enable bit (command register, bit 6) is disabled. write 1 to clear. 14 serr# status. this bit is set whenever the usb detects a pci address error. write 1 to clear. 13 received master abort status. this bit is set when the usb, acting as a pci master, aborts a pci bus memory cycle. write 1 to clear. 12 received target abort status. this bit is set when a usb generated pci c ycle (usb is the pci master) is aborted by a pci target. write 1 to clear. 11 signaled target abort status. this bit is set whenever the usb signals a target abort. write 1 to clear. 10:9 devsel# timing. (read only) these bits indicate the devsel# timing when performing a positive decode. since devsel# is asserted to meet the medium timing, these bits are encoded as 01b. 8 data parity reported. (read only) this bit is set to 1 if the parity error response bit (command register bit 6) is set, and the usb detects perr# asserted while acting as pci master (whether or not perr# was driven by usb). 7 fast back-to-back capable. the usb supports fast back-to-back transactions when the transactions are not to the same agent. this bit is always 1. 6:0 reserved . must be set to 0. index 08h device revision id register (ro) reset value: 08h index 09h-0bh pci class code register (ro) reset value: 0c0310h this register identifies the generic function of the usb the spec ific register level programming interface. the base class is 0 ch (serial bus controller). the sub class is 03h (universal se rial bus). the programming interface is 10h (openhci). index 0ch cache line size register (r/w) reset value: 00h this register identifies the system cache- line size in units of 32-bit words. the u sb only stores the value of bit 3 in this re gister since the cache-line size of 32 bytes is the only value applicable to the design. any value other than 08h written to this register i s read back as 00h. index 0dh latency timer register (r/w) reset value: 00h this register identifies the value of the latency timer in pci cl ocks for pci bus master cycles. bits [2:0] of this register ar e always set to 0. index 0eh header type register (ro) reset value: 00h this register identifies the type of the predefined header in the configuration space. since the usb is a single function devic e and not a pci-to-pci bridge, this byte should be read as 00h. index 0fh bist register (ro) reset value: 00h this register identifies the control and status of built-in self -test (bist). the usb does not implement bist, so this register is read only. index 10h-13h base address register - usb_bar0 (r/w) reset value: 00000000h 31:12 base address. post writes the value of the memory base address to this register. 11:4 always 0. indicates that a 4 kb address range is requested. 3 always 0. indicates that there is no support for prefetchable memory. 2:1 always 0. indicates that the base register is 32-bits wide and can be placed anywhere in 32-bit memory space. 0 always 0. indicates that the operational registers are mapped into memory space. table 6-41. pciusb: usb pci conf iguration registers (continued) bit description
302 amd geode? sc3200 processor data book core logic module - usb controller registers - pciusb revision 5.1 index 14h-2bh reserved reset value: 00h index 2ch-2dh subsystem vendor id (ro) reset value: 0e11h index 2eh-2fh subsystem id (ro) reset value: a0f8h index 30h-3bh reserved reset value: 00h index 3ch interrupt line register (r/w) reset value: 00h this register identifies the system interrupt controllers to whic h the device?s interrupt pin is connected. the value of this r egister is used by device drivers and has no direct meaning to usb. index 3dh interrupt pin register (r/w) reset value: 01h this register selects which interrupt pin the device uses. usb uses inta# after reset. intb#, intc# or intd# can be selected by writ- ing 2, 3 or 4, respectively. index 3eh min. grant register (ro) reset value: 00h this register specifies how long a burst is needed by the usb, assu ming a clock rate of 33 mhz. the value in this register spec ifies a period of time in units of 1/4 microsecond. index 3fh max. latency register (ro) reset value: 50h this register specifies how often (in units of 1/4 microsecond) the usb needs access to the pci bus assuming a clock rate of 33 mhz. index 40h-43h asic test mode enable register (r/w) reset value: 000f0000h used for internal debug and test purposes only. index 44h asic operational mode enable register (r/w) reset value: 00h 7:1 write only. read as 0s. 0 data buffer region 16 0: the size of the region for the data buffer is 32 bytes. 1: the size of the region for the data buffer is 16 bytes. index 45h-ffh reserved reset value: 00h table 6-41. pciusb: usb pci conf iguration registers (continued) bit description
amd geode? sc3200 processor data book 303 core logic module - usb controller registers - pciusb revision 5.1 table 6-42. usb_bar+memory offset: usb controller registers bit description offset 00h-03h hcrevision register (ro) reset value = 00000110h 31:8 reserved. read/write 0s. 7:0 revision (read only). indicates the open hci specification revision number implemented by the hardware. usb sup- ports 1.0 specification. (x.y = xyh). offset 04h-07h hccontrol register (r/w) reset value = 00000000h 31:11 reserved. read/write 0s. 10 remotewakeupconnectedenable. if a remote wakeup signal is supported, this bit enables that operation. since there is no remote wakeup signal supported, this bit is ignored. 9 remotewakeupconnected (read only). this bit indicated whether the hc suppor ts a remote wakeup signal. this imple- mentation does not support any such signal. the bit is hard-coded to 0. 8 interruptrouting. this bit is used for interrupt routing: 0: interrupts routed to normal interrupt mechanism (int). 1: interrupts routed to smi. 7:6 hostcontrollerfunctionalstate. this field sets the hc state. the hc may force a state change from usbsuspend to usbresume after detecting resume signaling from a downstream port. states are: 00: usbreset 01: usbresume 10: usboperational 11: usbsuspend 5 bulklistenable. when set, this bit enables proc essing of the bulk list. 4 controllistenable. when set, this bit enables processing of the control list. 3 isochronousenable. when clear, this bit disables the is ochronous list when the periodic li st is enabled (so interrupt eds may be serviced). while processing the periodic list, the hc will check this bit when it finds an isochronous ed. 2 periodiclistenable. when set, this bit enables processing of the periodic (interrupt and isochronous) list. the hc checks this bit prior to attempting any periodic transfers in a frame. 1:0 controlbulkserviceratio. specifies the number of control endpoints servic ed for every bulk endpoint. encoding is n-1 where n is the number of control endpoints (i.e ., 00: 1 control endpoint; 11: 3 control endpoints). offset 08h-0bh hccommandstatus register (r/w) reset value = 00000000h 31:18 reserved. read/write 0s. 17:16 scheduleoverruncount. this field increments every time the schedul ingoverrun bit in hcinterruptstatus is set. the count wraps from 11 to 00. 15:4 reserved. read/write 0s. 3 ownershipchangerequest. when set by software, this bit sets the owner shipchange field in hcinterruptstatus. the bit is cleared by software. 2 bulklistfilled. set to indicate there is an active ed on the bulk list. the bit may be set by either software or the hc and cleared by the hc each time it begins processing the head of the bulk list. 1 controllistfilled. set to indicate there is an active ed on the contro l list. it may be set by either software or the hc and cleared by the hc each time it begins pr ocessing the head of the control list. 0 hostcontrollerreset. this bit is set to initiate a software reset. this bit is cleared by the hc upon completion of the reset operation. offset 0ch-0fh hcinter ruptstatus register (r/w) reset value = 00000000h 31 reserved. read/write 0s. 30 ownershipchange. this bit is set when the ownershipchangerequest bit of hccommandstatus is set. 29:7 reserved. read/write 0s.
304 amd geode? sc3200 processor data book core logic module - usb controller registers - pciusb revision 5.1 6 roothubstatuschange. this bit is set when the content of hcrhstatus or the content of any hcrhportstatus register has changed. 5 framenumberoverflow. set when bit 15 of framenumber changes value. 4 unrecoverableerror (read only). this event is not implemented and is hard-coded to 0. writes are ignored. 3 resumedetected. set when hc detects resume signaling on a downstream port. 2 startofframe. set when the frame management block signals a start of frame event. 1 writebackdonehead. set after the hc has written hcdonehead to hccadonehead. 0 schedulingoverrun. set when the list processor determ ines a schedule overrun has occurred. note: all bits are set by hardware and cleared by software. offset 10h-13h hcinterruptenable register (r/w) reset value = 00000000h 31 masterinterruptenable. this bit is a global interrupt enable. a write of 1 allows interrupts to be enabled via the specific enable bits listed above. 30 ownershipchangeenable. 0: ignore. 1: enable interrupt generation due to ownership change. 29:7 reserved. read/write 0s. 6 roothubstatuschangeenable. 0: ignore. 1: enable interrupt generation due to root hub status change. 5 framenumberoverflowenable. 0: ignore. 1: enable interrupt generation due to frame number overflow. 4 unrecoverableerrorenable. this event is not implemented. all writes to this bit are ignored. 3 resumedetectedenable. 0: ignore. 1: enable interrupt generation due to resume detected. 2 startofframeenable. 0: ignore. 1: enable interrupt generation due to start of frame. 1 writebackdoneheadenable. 0: ignore. 1: enable interrupt generation due to writeback done head. 0 schedulingoverrunenable. 0: ignore. 1: enable interrupt generation due to scheduling overrun. note: writing a 1 to a bit in this register sets the co rresponding bit, while writing a 0 leaves the bit unchanged. offset 14h-17h hcinterruptdisable register (r/w) reset value = 00000000h 31 masterinterruptenable. global interrupt disable. a write of 1 disables all interrupts. 30 ownershipchangeenable. 0: ignore. 1: disable interrupt generation due to ownership change. 29:7 reserved. read/write 0s. table 6-42. usb_bar+memory offset: usb controller registers (continued) bit description
amd geode? sc3200 processor data book 305 core logic module - usb controller registers - pciusb revision 5.1 6 roothubstatuschangeenable. 0: ignore. 1: disable interrupt generation due to root hub status change. 5 framenumberoverflowenable. 0: ignore. 1: disable interrupt generation due to frame number overflow. 4 unrecoverableerrorenable. this event is not implemented. al l writes to this bit will be ignored. 3 resumedetectedenable. 0: ignore. 1: disable interrupt generation due to resume detected. 2 startofframeenable. 0: ignore. 1: disable interrupt generation due to start of frame. 1 writebackdoneheadenable. 0: ignore. 1: disable interrupt generation due to writeback done head. 0 schedulingoverrunenable. 0: ignore. 1: disable interrupt generation due to scheduling overrun. note: writing a 1 to a bit in this register clears the correspo nding bit, while writing a 0 to a bit leaves the bit unchanged. offset 18h-1bh hchcca register (r/w) reset value = 00000000h 31:8 hcca. pointer to hcca base address. 7:0 reserved. read/write 0s. offset 1ch-1fh hcperiodcurrented register (r/w) reset value = 00000000h 31:4 periodcurrented. pointer to the current periodic list ed. 3:0 reserved. read/write 0s. offset 20h-23h hccontrolheaded re gister (r/w) reset value = 00000000h 31:4 controlheaded. pointer to the control list head ed. 3:0 reserved. read/write 0s. offset 24h-27h hccontrolcurrented register (r/w) reset value = 00000000h 31:4 controlcurrented. pointer to the current control list ed. 3:0 reserved. read/write 0s. offset 28h-2bh hcbulkheaded register (r/w) reset value = 00000000h 31:4 bulkheaded. pointer to the bulk list head ed. 3:0 reserved. read/write 0s. offset 2ch-2fh hcbulkcurrented register (r/w) reset value = 00000000h 31:4 bulkcurrented. pointer to the current bulk list ed. 3:0 reserved. read/write 0s. offset 30h-33h hcdonehead register (r/w) reset value = 00000000h 31:4 donehead. pointer to the current done list head ed. 3:0 reserved. read/write 0s. table 6-42. usb_bar+memory offset: usb controller registers (continued) bit description
306 amd geode? sc3200 processor data book core logic module - usb controller registers - pciusb revision 5.1 offset 34h-37h hcfminterval register (r/w) reset value = 00002edfh 31 frameintervaltoggle (read only). this bit is toggled by hcd when it loads a new value into frameinterval. 30:16 fslargestdatapacket (read only). this field specifies a value which is loade d into the largest data packet counter at the beginning of each frame. 15:14 reserved. read/write 0s. 13:0 frameinterval. this field specifies the length of a frame as (bit ti mes - 1). for 12,000 bit times in a frame, a value of 11,999 is stored here. offset 38h-3bh hcframeremaining register (ro) reset value = 00000000h 31 frameremainingtoggle (read only). loaded with frameintervaltoggle when frameremaining is loaded. 30:14 reserved. read 0s. 13:0 frameremaining (read only). when the hc is in the usboperational stat e, this 14-bit field decrements each 12 mhz clock period. when the count reaches 0, ( end of frame) the counter reloads with frameinterval. in addition, the counter loads when the hc transitions into usboperational. offset 3ch-3fh hcfmnumber register (ro) reset value = 00000000h 31:16 reserved. read 0s. 15:0 framenumber (read only). this 16-bit incrementing counter field is incremented coincident with the loading of framer- emaining. the count rolls over from ffffh to 0h. offset 40h-43h hcperiodicstart re gister (r/w) reset value = 00000000h 31:14 reserved. read/write 0s. 13:0 periodicstart. this field contains a value used by the list processor to determine where in a frame the periodic list pro- cessing must begin. offset 44h-47h hclsthreshold register (r/w) reset value = 00000628h 31:12 reserved. read/write 0s. 11:0 lsthreshold. this field contains a value used by the frame ma nagement block to determine whether or not a low speed transaction can be started in the current frame. offset 48h-4bh hcrhdescriptora re gister (r/w) reset value = 01000003h 31:24 powerontopowergoodtime. this field value is represented as the number of 2 ms intervals, ensuring that the power switching is effective within 2 ms. only bits [25:24] are implemented as r/w. the re maining bits are read only as 0. it is not expected that these bits be written to anything other than 1h, bu t limited adjustment is provided. this field should be written to support system implementation. this fiel d should always be written to a non-zero value. 23:13 reserved. read/write 0s. 12 noovercurrentprotection. this bit should be written to support the exte rnal system port over-current implementation. 0: over-current status is reported. 1: over-current status is not reported. 11 overcurrentprotectionmode. this bit should be written 0 and is only va lid when noovercurrentprotection is cleared. 0: global over-current. 1: individual over-current 10 devicetype (read only). usb is not a compound device. 9 nopowerswitching. this bit should be written to support the exter nal system port power switching implementation. 0: ports are power switched. 1: ports are always powered on. 8 powerswitchingmode. this bit is only valid when nopowerswitchi ng is cleared. this bit should be written 0. 0: global switching. 1: individual switching table 6-42. usb_bar+memory offset: usb controller registers (continued) bit description
amd geode? sc3200 processor data book 307 core logic module - usb controller registers - pciusb revision 5.1 7:0 numberdownstreamports (read only). usb supports three downstream ports. note: this register is only reset by a power-on reset (pcirst#). it is written during system initialization to configure the root hub . these bit should not be written during normal operation. offset 4ch-4fh hcrhdescriptorb re gister (r/w) reset value = 00000000h 31:16 portpowercontrolmask. global-power switching. this field is only valid if nopowe rswitching is cleared and power- switchingmode is set (individual port sw itching). when set, the port only responds to individual port power switching com- mands (set/clearportpower). when clear ed, the port only responds to gl obal power switching commands (set/ clearglobalpower). 0: device not removable. 1: global-power mask. port bit relationship - unimplemented ports are reserved, read/write 0. 0 = reserved 1 = port 1 2 = port 2 ... 15 = port 15 15:0 deviceremoveable. usb ports default to removable devices. 0: device not removable. 1: device removable. port bit relationship 0 = reserved 1 = port 1 2 = port 2 ... 15 = port 15 unimplemented ports are reserved, read/write 0. note: this register is only reset by a power-on reset (pcirst#). it is written during system initialization to configure the root hub . these bit should not be written during normal operation. offset 50h-53h hcrhstatus register (r/w) reset value = 00000000h 31 clearremotewakeupenable (write only). writing a 1 to this bit clears deviceremotewakeupenable. writing a 0 has no effect. 30:18 reserved. read/write 0s. 17 overcurrentindicatorchange. this bit is set when overcurrentindicator change s. writing a 1 clears this bit. writing a 0 has no effect. 16 read: localpowerstatuschange. not supported. always read 0. write: setglobalpower. write a 1 issues a setglobalpower command to the ports. writing a 0 has no effect. 15 read: deviceremotewakeupenable. this bit enables ports' connectstatuschange as a remote wakeup event. 0: disabled. 1: enabled. write: setremotewakeupenable. writing a 1 sets deviceremotewakeupenable. writing a 0 has no effect. 14:2 reserved. read/write 0s. 1 overcurrentindicator. this bit reflects the state of the ovrcur pin. th is field is only valid if noovercurrentprotection and overcurrentprotec tionmode are cleared. 0: no over-current condition. 1:over-current condition. 0 read: localpowerstatus. not supported. always read 0. write: clearglobalpower. writing a 1 issues a clearglobalpower comm and to the ports. writing a 0 has no effect. note: this register is reset by the usbreset state. table 6-42. usb_bar+memory offset: usb controller registers (continued) bit description
308 amd geode? sc3200 processor data book core logic module - usb controller registers - pciusb revision 5.1 offset 54h-57h hcrhportstatus[1] register (r/w) reset value = 00000000h 31:21 reserved. read/write 0s. 20 portresetstatuschange. this bit indicates that the port reset signal has completed. 0: port reset is not complete. 1: port reset is complete. 19 portovercurrentindicatorchange. this bit is set when overcurrentindicator changes. writing a 1 clears this bit. writing a 0 has no effect. 18 portsuspendstatuschange. this bit indicates the completion of t he selective resume sequence for the port. 0: port is not resumed. 1: port resume is complete. 17 portenablestatuschange. this bit indicates that the port has been di sabled due to a hardware event (cleared portena- blestatus). 0: port has not been disabled. 1: portenablestatus has been cleared. 16 connectstatuschange. this bit indicates a connect or disconnect event has been detect ed. writing a 1 clears this bit. writing a 0 has no effect. 0: no connect/disconnect event. 1: hardware detection of connect/disconnect event. if deviceremoveable is set, this bit resets to 1. 15:10 reserved. read/write 0s. 9 read: lowspeeddeviceattached. this bit defines the speed (and bud idle) of the attached device. it is only valid when currentconnectstatus is set. 0: full speed device. 1: low speed device. write: clearportpower. writing a 1 clears portpowerstatus. writing a 0 has no effect. 8 read: portpowerstatus. this bit reflects the power state of the port regardless of the power switching mode. 0: port power is off. 1: port power is on. if nopowerswitching is set, this bit is always read as 1. write: setportpower. writing a 1 sets portpowerstatus. writing a 0 has no effect. 7:5 reserved. read/write 0s. 4 read: portresetstatus. 0: port reset signal is not active. 1: port reset signal is active. write: setportreset. writing a 1 sets portresetstatus. writing a 0 has no effect. 3 read: portovercurrentindicator. this bit reflects the state of the ovrcur pi n dedicated to this port. this field is only valid if noovercurrentprotection is clear ed and overcurrentprotectionmode is set. 0: no over-current condition. 1: over-current condition. write: clearportsuspend. writing a 1 initiates the selective resume sequence for the port. writing a 0 has no effect. 2 read: portsuspendstatus. 0: port is not suspended. 1: port is selectively suspended. write: setportsuspend. writing a 1 sets portsuspendstatus. writing a 0 has no effect. table 6-42. usb_bar+memory offset: usb controller registers (continued) bit description
amd geode? sc3200 processor data book 309 core logic module - usb controller registers - pciusb revision 5.1 1 read: portenablestatus. 0: port disabled. 1: port enabled. write: setportenable. writing a 1 sets portenablestatus. writing a 0 has no effect. 0 read: currentconnectstatus. 0: no device connected. 1: device connected. if deviceremoveable is set (not removable) this bit is always 1. write: clearportenable. writing 1 a clears portenablestatus. writing a 0 has no effect. note: this register is reset by the usbreset state. offset 58h-5bh hcrhportstatus[2] register (r/w) reset value = 00000000h 31:21 reserved. read/write 0s. 20 portresetstatuschange. this bit indicates that the port reset signal has completed. 0: port reset is not complete. 1: port reset is complete. 19 portovercurrentindicatorchange. this bit is set when overcurrentindicator changes. writing a 1 clears this bit. writing a 0 has no effect. 18 portsuspendstatuschange. this bit indicates the completion of t he selective resume sequence for the port. 0: port is not resumed. 1: port resume is complete. 17 portenablestatuschange. this bit indicates that the port has been di sabled due to a hardware event (cleared portena- blestatus). 0: port has not been disabled. 1: portenablestatus has been cleared. 16 connectstatuschange. this bit indicates a connect or disconnect event has been detect ed. writing a 1 clears this bit. writing a 0 has no effect. 0: no connect/disconnect event. 1: hardware detection of connect/disconnect event. if deviceremoveable is set, this bit resets to 1. 15:10 reserved. read/write 0s. 9 read: lowspeeddeviceattached. this bit defines the speed (and bud idle) of the attached device. it is only valid when currentconnectstatus is set. 0: full speed device. 1: low speed device. write: clearportpower. writing a 1 clears portpowerstatus. writing a 0 has no effect. 8 read: portpowerstatus. this bit reflects the power state of the port regardless of the power switching mode. 0: port power is off. 1: port power is on. if nopowerswitching is set, this bit is always read as 1. write: setportpower. writing a 1 sets portpowerstatus. writing a 0 has no effect. 7:5 reserved. read/write 0s. 4 read: portresetstatus. 0: port reset signal is not active. 1: port reset signal is active. write: setportreset. writing a 1 sets portresetstatus. writing a 0 has no effect. table 6-42. usb_bar+memory offset: usb controller registers (continued) bit description
310 amd geode? sc3200 processor data book core logic module - usb controller registers - pciusb revision 5.1 3 read: portovercurrentindicator. this bit reflects the state of the ovrcur pi n dedicated to this port. this field is only valid if noovercurrentprotection is clear ed and overcurrentprotectionmode is set. 0: no over-current condition. 1: over-current condition. write: clearportsuspend. writing a 1 initiates the selective resume sequence for the port. writing a 0 has no effect. 2 read: portsuspendstatus. 0: port is not suspended. 1: port is selectively suspended. write: setportsuspend. writing a 1 sets portsuspendstatus. writing a 0 has no effect. 1 read: portenablestatus. 0: port disabled. 1: port enabled. write: setportenable. writing a 1 sets portenablestatus. writing a 0 has no effect. 0 read: currentconnectstatus. 0: no device connected. 1: device connected. if deviceremoveable is set (not removable) this bit is always 1. write: clearportenable. writing 1 a clears portenablestatus. writing a 0 has no effect. note: this register is reset by the usbreset state. offset 5ch-5fh hcrhportstatus[3] register (r/w) reset value = 00000000h 31:21 reserved. read/write 0s. 20 portresetstatuschange. this bit indicates that the port reset signal has completed. 0: port reset is not complete. 1: port reset is complete. 19 portovercurrentindicatorchange. this bit is set when overcurrentindicator changes. writing a 1 clears this bit. writing a 0 has no effect. 18 portsuspendstatuschange. this bit indicates the completion of t he selective resume sequence for the port. 0: port is not resumed. 1: port resume is complete. 17 portenablestatuschange. this bit indicates that the port has been di sabled due to a hardware event (cleared portena- blestatus). 0: port has not been disabled. 1: portenablestatus has been cleared. 16 connectstatuschange. this bit indicates a connect or disconnect event has been detect ed. writing a 1 clears this bit. writing a 0 has no effect. 0: no connect/disconnect event. 1: hardware detection of connect/disconnect event. if deviceremoveable is set, this bit resets to 1. 15:10 reserved. read/write 0s. 9 read: lowspeeddeviceattached. this bit defines the speed (and bud idle) of the attached device. it is only valid when currentconnectstatus is set. 0: full speed device. 1: low speed device. write: clearportpower. writing a 1 clears portpowerstatus. writing a 0 has no effect. table 6-42. usb_bar+memory offset: usb controller registers (continued) bit description
amd geode? sc3200 processor data book 311 core logic module - usb controller registers - pciusb revision 5.1 8 read: portpowerstatus. this bit reflects the power state of the port regardless of the power switching mode. 0: port power is off. 1: port power is on. if nopowerswitching is set, this bit is always read as 1. write: setportpower. writing a 1 sets portpowerstatus. writing a 0 has no effect. 7:5 reserved. read/write 0s. 4 read: portresetstatus. 0: port reset signal is not active. 1: port reset signal is active. write: setportreset. writing a 1 sets portresetstatus. writing a 0 has no effect. 3 read: portovercurrentindicator. this bit reflects the state of the ovrcur pi n dedicated to this port. this field is only valid if noovercurrentprotection is clear ed and overcurrentprotectionmode is set. 0: no over-current condition. 1: over-current condition. write: clearportsuspend. writing a 1 initiates the selective resume sequence for the port. writing a 0 has no effect. 2 read: portsuspendstatus. 0: port is not suspended. 1: port is selectively suspended. write: setportsuspend. writing a 1 sets portsuspendstatus. writing a 0 has no effect. 1 read: portenablestatus. 0: port disabled. 1: port enabled. write: setportenable. writing a 1 sets portenablestatus. writing a 0 has no effect. 0 read: currentconnectstatus. 0: no device connected. 1: device connected. if deviceremoveable is set (not removable) this bit is always 1. write: clearportenable. writing 1 a clears portenablestatus. writing a 0 has no effect. note: this register is reset by the usbreset state. offset 60h-9fh reserved reset value = xxh offset 100h-103h hcecontrol register (r/w) reset value = 00000000h 31:9 reserved. read/write 0s. 8 a20state. indicates current state of gate a20 on keyboard c ontroller. compared against value written to 60h when gatea20sequence is active. 7 irq12active. indicates a positive transition on irq12 from keyboard c ontroller occurred. software writes this bit to 1 to clear it (set it to 0); a 0 write has no effect. 6 irq1active. indicates a positive transition on irq1 from keyboard controller occurred. so ftware writes this bit to 1 to clear it (set it to 0); a 0 write has no effect. 5 gatea20sequence. set by hc when a data value of d1h is written to i/o port 64h. cleared by hc on write to i/o port 64h of any value other than d1h. 4 externalirqen. when set to 1, irq1 and irq12 from the keyboard co ntroller cause an emulation interrupt. the function controlled by this bit is independent of the setting of the emulationenable bit in this register. 3 irqen. when set, the hc generates irq1 or irq12 as long as the ou tputfull bit in hcestatus is set to 1. if the auxout- putfull bit of hcestatus is 0, irq1 is generated: if 1, then an irq12 is generated. 2 characterpending. when set, an emulation interrupt will be generated when the outputfull bit of t he hcestatus register is set to 0. table 6-42. usb_bar+memory offset: usb controller registers (continued) bit description
312 amd geode? sc3200 processor data book core logic module - usb controller registers - pciusb revision 5.1 1 emulationinterrupt (read only). this bit is a static decode of the emulation interrupt condition. 0 emulationenable. when set to 1 the hc is enabled for legacy emul ation and will decode accesses to i/o registers 60h and 64h and generate irq1 and/or irq12 when appropriate. the hc also generates an emulation interrupt at appropriate times to invoke the emulation software. note: this register is used to enable and control the emul ation hardware and report various status information. offset 104h-107h hceinput regist er (r/w) reset value = 000000xxh 31:8 reserved. read/write 0s. 7:0 inputdata. this register holds data wr itten to i/o ports 60h and 64h. note: this register is the emulation side of the legacy input buffer register. offset 108h-10bh hceout put register (r/w) reset value = 000000xxh 31:8 reserved. read/write 0s. 7:0 outputdata. this register hosts data that is returned when an i/o read of port 60h is performed by application software. note: this register is the emulation side of the legacy output buff er register where keyboard and mouse data is to be written by soft - ware. offset 10ch-10fh hcestatus register (r/w) reset value = 00000000h 31:8 reserved. read/write 0s. 7 parity. indicates parity error on keyboard/mouse data. 6 timeout. used to indicate a time-out 5 auxoutputfull. irq12 is asserted whenever this bit is set to 1 and outputfull is set to 1 and the irqen bit is set. 4 inhibit switch. this bit reflects the state of the keyboard inhibit switch and is se t if the keyboard is not inhibited. 3 cmddata. the hc will set this bit to 0 on an i/o write to port 60h a nd on an i/o write to port 64h the hc will set this bit to 1. 2 flag. nominally used as a system flag by softw are to indicate a warm or cold boot. 1 inputfull. except for the case of a gate a20 sequence, this bit is set to 1 on an i/o write to address 60h or 64h. while this bit is set to 1 and emulation is enabled, an emulation interrupt condition exists. 0 outputfull. the hc will set this bit to 0 on a read of i/o port 60h. if irqen is set and auxoutputfull is set to 0 then an irq1 is generated as long as this bit is set to 1. if irqen is set and auxoutputfull is set to 1 then and irq12 will be gen- erated a long as this bit is set to 1. while this bit is 0 and characterpending in hcecontrol is set to 1, an emulation inter - rupt condition exists. note: this register is the emulation si de of the legacy status register. table 6-42. usb_bar+memory offset: usb controller registers (continued) bit description
amd geode? sc3200 processor data book 313 core logic module - isa legacy register space revision 5.1 6.4.7 isa legacy register space the isa legacy registers reside in the isa i/o address space in the address range from 000h to fffh and are accessed through typical input/ output instructions (i.e., cpu direct r/w) with the designated i/o port address and 8-bit data. the bit formats for the isa legacy i/o registers plus two chipset-specific configuration registers used for interrupt mapping in the core logic module are given in this section. the isa legacy registers are separated into the following dma channel control registers, see table 6-43 dma page registers, see table 6-44 programmable interval timer registers, see table 6-45 programmable interrupt controller registers, see table 6-46 keyboard controller registers, see table 6-47 real-time clock registers, see table 6-48 miscellaneous registers, see table 6-49 (includes 4d0h and 4d1h interrupt edge/level select registers) table 6-43. dma channel control registers bit description i/o port 000h dma channel 0 address register (r/w) written as two successive bytes, byte 0, 1. i/o port 001h dma channel 0 transfer count register (r/w) written as two successive bytes, byte 0, 1. i/o port 002h dma channel 1 address register (r/w) written as two successive bytes, byte 0, 1. i/o port 003h dma channel 1 transfer count register (r/w) written as two successive bytes, byte 0, 1. i/o port 004h dma channel 2 address register (r/w) written as two successive bytes, byte 0, 1. i/o port 005h dma channel 2 transfer count register (r/w) written as two successive bytes, byte 0, 1. i/o port 006h dma channel 3 address register (r/w) written as two successive bytes, byte 0, 1. i/o port 007h dma channel 3 transfer count register (r/w) written as two successive bytes, byte 0, 1. i/o port 008h (r/w) read dma status register, channels 3:0 7 channel 3 request. indicates if a request is pending. 0: no. 1: yes. 6 channel 2 request. indicates if a request is pending. 0: no. 1: yes. 5 channel 1 request. indicates if a request is pending. 0: no. 1: yes. 4 channel 0 request. indicates if a request is pending. 0: no. 1: yes. 3 channel 3 terminal count. indicates if tc was reached. 0: no. 1: yes.
314 amd geode? sc3200 processor data book core logic module - isa legacy register space revision 5.1 2 channel 2 terminal count. indicates if tc was reached. 0: no. 1: yes. 1 channel 1 terminal count. indicates if tc was reached. 0: no. 1: yes. 0 channel 0 terminal count. indicates if tc was reached. 0: no. 1: yes. write dma command register, channels 3:0 7 dack sense. 0: active low. 1: active high. 6 dreq sense. 0: active high. 1: active low. 5 write selection. 0: late write. 1: extended write. 4 priority mode. 0: fixed. 1: rotating. 3 timing mode. 0: normal. 1: compressed. 2 channels 3:0. 0: disable. 1: enable. 1:0 reserved. must be set to 0. i/o port 009h software dma request register, channels 3:0 (w) 7:3 reserved. must be set to 0. 2 request type. 0: reset. 1: set. 1:0 channel number request select 00: channel 0. 01: channel 1. 10: channel 2. 11: channel 3. i/o port 00ah dma channel mask register, channels 3:0 (wo) 7:3 reserved. must be set to 0. 2 channel mask. 0: not masked. 1: masked. 1:0 channel number mask select. 00: channel 0. 01: channel 1. 10: channel 2. 11: channel 3. table 6-43. dma channel control registers (continued) bit description
amd geode? sc3200 processor data book 315 core logic module - isa legacy register space revision 5.1 i/o port 00bh dma channel mode register, channels 3:0 (wo) 7:6 transfer mode. 00: demand. 01: single. 10: block. 11: cascade. 5 address direction. 0: increment. 1: decrement. 4 auto-initialize. 0: disable. 1: enable. 3:2 transfer type. 00: verify. 01: write transfer (i/o to memory). 10: read transfer (memory to i/o). 11: reserved. 1:0 channel number mode select. 00: channel 0. 01: channel 1. 10: channel 2. 11: channel 3. i/o port 00ch dma clear byte pointer command, channels 3:0 (w) i/o port 00dh dma master clear command, channels 3:0 (w) i/o port 00eh dma clear mask register command, channels 3:0 (w) i/o port 00fh dma write mask register command, channels 3:0 (w) i/o port 0c0h dma channel 4 address register (r/w) not used. i/o port 0c2h dma channel 4 transfer count register (r/w) not used. i/o port 0c4h dma channel 5 address register (r/w) not supported. i/o port 0c6h dma channel 5 transfer count register (r/w) not supported. i/o port 0c8h dma channel 6 address register (r/w) not supported. i/o port 0cah dma channel 6 transfer count register (r/w) not supported. i/o port 0cch dma channel 7 address register (r/w) not supported. i/o port 0ceh dma channel 7 transfer count register (r/w) not supported. table 6-43. dma channel control registers (continued) bit description
316 amd geode? sc3200 processor data book core logic module - isa legacy register space revision 5.1 i/o port 0d0h (r/w) read dma status register, channels 7:4 note: channels 5, 6, and 7 are not supported. 7 channel 7 request. indicates if a request is pending. 0: no. 1: yes. 6 channel 6 request. indicates if a request is pending. 0: no. 1: yes. 5 channel 5 request. indicates if a request is pending. 0: no. 1: yes. 4 undefined. 3 channel 7 terminal count. indicates if tc was reached. 0: no. 1: yes. 2 channel 6 terminal count. indicates if tc was reached. 0: no. 1: yes. 1 channel 5 terminal count. indicates if tc was reached. 0: no. 1: yes. 0 undefined. write dma command register, channels 7:4 note: channels 5, 6, and 7 are not supported. 7 dack sense. 0: active low. 1: active high. 6 dreq sense. 0: active high. 1: active low. 5 write selection. 0: late write. 1: extended write. 4 priority mode. 0: fixed. 1: rotating. 3 timing mode. 0: normal. 1: compressed. 2 channels 7:4. 0: disable. 1: enable. 1:0 reserved. must be set to 0. table 6-43. dma channel control registers (continued) bit description
amd geode? sc3200 processor data book 317 core logic module - isa legacy register space revision 5.1 i/o port 0d2h software dma request register, channels 7:4 (w) note: channels 5, 6, and 7 are not supported. 7:3 reserved. must be set to 0. 2 request type. 0: reset. 1: set. 1:0 channel number request select. 00: illegal. 01: channel 5. 10: channel 6. 11: channel 7. i/o port 0d4h dma channel mask register, channels 7:4 (wo) note: channels 5, 6, and 7 are not supported. 7:3 reserved. must be set to 0. 2 channel mask. 0: not masked. 1: masked. 1:0 channel number mask select. 00: channel 4. 01: channel 5. 10: channel 6. 11: channel 7. i/o port 0d6h dma channel mode register, channels 7:4 (wo) note: channels 5, 6, and 7 are not supported. 7:6 transfer mode. 00: demand. 01: single. 10: block. 11: cascade. 5 address direction. 0: increment. 1: decrement. 4 auto-initialize. 0: disabled 1: enable 3:2 transfer type. 00: verify. 01: write transfer (i/o to memory). 10: read transfer (memory to i/o). 11: reserved. 1:0 channel number mode select. 00: channel 4. 01: channel 5. 10: channel 6. 11: channel 7. channel 4 must be programmed in cascade mode. this mode is not the default. i/o port 0d8h dma clear byte pointer command, channels 7:4 (w) note: channels 5, 6, and 7 are not supported. i/o port 0dah dma master clear command, channels 7:4 (w) note: channels 5, 6, and 7 are not supported. i/o port 0dch dma clear mask register command, channels 7:4 (w) note: channels 5, 6, and 7 are not supported. table 6-43. dma channel control registers (continued) bit description
318 amd geode? sc3200 processor data book core logic module - isa legacy register space revision 5.1 i/o port 0deh dma write mask register command, channels 7:4 (w) note: channels 5, 6, and 7 are not supported. table 6-43. dma channel control registers (continued) bit description table 6-44. dma page registers bit description i/o port 081h dma channel 2 low page register (r/w) address bits [23:16] (byte 2). i/o port 082h dma channel 3 low page register (r/w) address bits [23:16] (byte 2). i/o port 083h dma channel 1 low page register (r/w) address bits [23:16] (byte 2). i/o port 087h dma channel 0 low page register (r/w) address bits [23:16] (byte 2). i/o port 089h dma channel 6 low page register (r/w) nor supported. i/o port 08ah dma channel 7 low page register (r/w) not supported. i/o port 08bh dma channel 5 low page register (r/w) not supported. i/o port 08fh isa refresh low page register (r/w) refresh address. i/o port 481h dma channel 2 high page register (r/w) address bits [31:24] (byte 3). note: this register is reset to 00h on any access to port 081h. i/o port 482h dma channel 3 high page register (r/w) address bits [31:24] (byte 3). note: this register is reset to 00h on any access to port 082h. i/o port 483h dma channel 1 high page register (r/w) address bits [31:24] (byte 3). note: this register is reset to 00h on any access to port 083h. i/o port 487h dma channel 0 high page register (r/w) address bits [31:24] (byte 3). note: this register is reset to 00h on any access to port 087h. i/o port 489h dma channel 6 high page register (r/w) not supported i/o port 48ah dma channel 7 high page register (r/w) not spported i/o port 48bh dma channel 5 high page register (r/w) not supported
amd geode? sc3200 processor data book 319 core logic module - isa legacy register space revision 5.1 table 6-45. programmable interval timer registers bit description i/o port 040h write pit timer 0 counter 7:0 counter value. read pit timer 0 status 7 counter output. state of counter output signal. 6 counter loaded. indicates if the last count written is loaded. 0: yes. 1: no. 5:4 current read/write mode. 00: counter latch command. 01: r/w lsb only. 10: r/w msb only. 11: r/w lsb, followed by msb. 3:1 current counter mode. 0-5. 0 bcd mode. 0: binary. 1: bcd (binary coded decimal). i/o port 041h write pit timer 1 counter (refresh) 7:0 counter value. read pit timer 1 status (refresh) 7 counter output. state of counter output signal. 6 counter loaded. indicates if the last count written is loaded. 0: yes. 1: no. 5:4 current read/write mode. 00: counter latch command. 01: r/w lsb only. 10: r/w msb only. 11: r/w lsb, followed by msb. 3:1 current counter mode. 0-5. 0 bcd mode. 0: binary. 1: bcd (binary coded decimal).
320 amd geode? sc3200 processor data book core logic module - isa legacy register space revision 5.1 i/o port 042h write pit timer 2 counter (speaker) 7:0 counter value. read pit timer 2 status (speaker) 7 counter output. state of counter output signal. 6 counter loaded. indicates if the last count written is loaded. 0: yes. 1: no. 5:4 current read/write mode. 00: counter latch command. 01: r/w lsb only. 10: r/w msb only. 11: r/w lsb, followed by msb. 3:1 current counter mode. 0-5. 0 bcd mode. 0: binary. 1: bcd (binary coded decimal). i/o port 043h (r/w) pit mode control word register notes: 1. if bits [7:6] = 11: register functions as read status command and: bit 5 = latch count bit 4 = latch status bit 3 = select counter 2 bit 2 = select counter 1 bit 1 = select counter 0 bit 0 = reserved 2. if bits [5:4] = 00: register f unctions as counter latch command and: bits [7:6] = selects counter bits [3:0] = don?t care 7:6 counter select. 00: counter 0. 01: counter 1. 10: counter 2. 11: read-back command (note 1). 5:4 current read/write mode. 00: counter latch command. 01: r/w lsb only. 10: r/w msb only. 11: r/w lsb, followed by msb. 3:1 current counter mode. 0-5. 0 bcd mode. 0: binary. 1: bcd (binary coded decimal). table 6-45. programmable interval timer registers (continued) bit description
amd geode? sc3200 processor data book 321 core logic module - isa legacy register space revision 5.1 table 6-46. programmable interrupt controller registers bit description i/o port 020h / 0a0h master / slave pic icw1 (wo) 7:5 reserved. must be set to 0. 4 reserved. must be set to 1. 3 trigger mode . 0: edge. 1: level. 2 vector address interval 0: 8 byte intervals. 1: 4 byte intervals. 1 reserved. must be set to 0 (cascade mode). 0 reserved. must be set to 1 (icw4 must be programmed). i/o port 021h / 0a1h master / slave pic icw2 (after icw1 is written) (wo) 7:3 a[7:3]. address lines [7:3] for base vector for interrupt controller. 2:0 reserved. must be set to 0. i/o port 021h / 0a1h master / slave pic icw3 (after icw2 is written) (wo) master pic icw3 7:0 cascade irq. must be 04h. slave pic icw3 7:0 slave id. must be 02h. i/o port 021h / 0a1h master / slave pic icw4 (after icw3 is written) (wo) 7:5 reserved. must be set to 0. 4 special fully nested mode. 0: disable. 1: enable. 3:2 reserved. must be set to 0. 1 auto eoi. 0: normal eoi. 1: auto eoi. 0 reserved. must be set to 1 (8086/8088 mode). i/o port 021h / 0a1h (r/w) master / slave pic ocw1 (except immediately after icw1 is written) 7 irq7 / irq15 mask. 0: not masked. 1: mask. 6 irq6 / irq14 mask. 0: not masked. 1: mask. 5 irq5 / irq13 mask. 0: not masked. 1: mask. 4 irq4 / irq12 mask. 0: not masked. 1: mask. 3 irq3 / irq11 mask. 0: not masked. 1: mask.
322 amd geode? sc3200 processor data book core logic module - isa legacy register space revision 5.1 2 irq2 / irq10 mask. 0: not masked. 1: mask. 1 irq1 / irq9 mask. 0: not masked. 1: mask. 0 irq0 / irq8 mask. 0: not masked. 1: mask. i/o port 020h / 0a0h master / slave pic ocw2 (wo) 7:5 rotate/eoi codes. 000: clear rotate in auto eoi mode 100: set rotate in auto eoi mode 001: non-specific eoi 101: ro tate on non-specific eoi command 010: no operation 110: set priority command (bits [2:0] must be valid) 011: specific eoi (bits [2:0] must be valid) 111: rotate on specific eoi command 4:3 reserved. must be set to 0. 2:0 irq number (000-111). i/o port 020h / 0a0h master / slave pic ocw3 (wo) 7 reserved. must be set to 0. 6:5 special mask mode. 00: no operation. 01: no operation. 10: reset special mask mode. 11: set special mask mode. 4 reserved. must be set to 0. 3 reserved. must be set to 1. 2 poll command. 0: disable. 1: enable. 1:0 register read mode. 00: no operation. 01: no operation. 10: read interrupt request register on next read of port 20h. 11: read interrupt service register on next read of port 20h. i/o port 020h / 0a0h master / slave pic interrupt request and service registers for ocw3 commands (ro) the function of this regi ster is set with bits [1:0] in a write to 020h. interrupt request register 7 irq7 / irq15 pending. 0: yes. 1: no. 6 irq6 / irq14 pending. 0: yes. 1: no. 5 irq5 / irq13 pending. 0: yes. 1: no. 4 irq4 / irq12 pending. 0: yes. 1: no. table 6-46. programmable interrupt controller registers (continued) bit description
amd geode? sc3200 processor data book 323 core logic module - isa legacy register space revision 5.1 3 irq3 / irq11 pending. 0: yes. 1: no. 2 irq2 / irq10 pending. 0: yes. 1: no. 1 irq1 / irq9 pending. 0: yes. 1: no. 0 irq0 / irq8 pending. 0: yes. 1: no. interrupt service register 7 irq7 / irq15 in-service. 0: no. 1: yes. 6 irq6 / irq14 in-service. 0: no. 1: yes. 5 irq5 / irq13 in-service. 0: no. 1: yes. 4 irq4 / irq12 in-service. 0: no. 1: yes. 3 irq3 / irq11 in-service. 0: no. 1: yes. 2 irq2 / irq10 in-service. 0: no. 1: yes. 1 irq1 / irq9 in-service. 0: no. 1: yes. 0 irq0 / irq8 in-service. 0: no. 1: yes. table 6-46. programmable interrupt controller registers (continued) bit description
324 amd geode? sc3200 processor data book core logic module - isa legacy register space revision 5.1 table 6-47. keyboard controller registers bit description i/o port 060h external keyboard controller data register (r/w) keyboard controller data register. all accesses to this port are passed to the isa bus. if the fast keyboard gate a20 and reset fea- tures are enabled through bit 7 of the rom/at logic control regist er (f0 index 52h[7]), the respective sequences of writes to t his port assert the a20m# signal or cause a warm cpu reset. i/o port 061h port b control register (r/w) reset value: 00x01100b 7 perr#/serr# status. (read only) indicates if a pci bus error (perr#/serr#) was asserted by a pci device or by the sc3200. 0: no. 1: yes. this bit can only be set if err_en (bit 2) is set 0. this bit is set 0 after a write to err_en with a 1 or after reset. 6 iochk# status. (read only) indicates if an i/o device is reporting an error to the sc3200. 0: no. 1: yes. this bit can only be set if iochk_en (bit 3) is set 0. this bit is set 0 after a write to iochk_en with a 1 or after reset. 5 pit out2 state. (read only) this bit reflects the current status of the of the pit counter 2 (out2). 4 toggle. (read only) this bit toggles on every fall ing edge of counter 1 (out1). 3i ochk# enable. 0: generates an nmi if iochk# is driven low by an i/o devi ce to report an error. note that nmi is under smi control. 1: ignores the iochk# input signal and does not generate nmi. 2 perr/ serr enable. generate an nmi if perr#/serr# is driven active to report an error. 0: enable. 1: disable. 1 pit counter2 (spkr). 0: forces counter 2 output (out2) to zero. 1: allows counter 2 output (out2) to pass to the speaker. 0 pit counter2 enable. 0: sets gate2 input low. 1: sets gate2 input high. i/o port 062h external keyboard controller mailbox register (r/w) keyboard controller mailbox register. i/o port 064h external keyboard controller command register (r/w) keyboard controller command register. all accesses to this port are passed to the isa bus. if the fast keyboard gate a20 and reset features are enabled through bit 7 of the rom/at logic control regist er (f0 index 52h[7]), the respective sequences of writes t o this port assert the a20m# signal or cause a warm cpu reset. i/o port 066h external keyboard controller mailbox register (r/w) keyboard controller mailbox register. i/o port 092h port a control register (r/w) reset value: 02h 7:2 reserved. must be set to 0. 1 a20m# assertion. assert a20# (internally). 0: enable. 1: disable. this bit reflects a20# status and ca n be changed by keyboard command monitoring. an smi event is generated when this bit is changed, if enabled by f0 index 53h[0]. the smi status is reported in f1bar0+i/ o offset 00h/02h[7]. 0 fast cpu reset. wm_rst smi is asserted to the bios. 0: disable. 1: enable. this bit must be cleared before the generation of another reset.
amd geode? sc3200 processor data book 325 core logic module - isa legacy register space revision 5.1 table 6-48. real-time clock registers bit description i/o port 070h rtc address register (wo) this register is shadowed within the core logic module and is read through the rtc shadow register (f0 index bbh). 7 nmi mask . 0: enable. 1: mask. 6:0 rtc register index. a write of this register sends the data out on the isa bus and also causes rtcale to be triggered. (rtcale is an internal signal between the core logic module and the internal rtc controller.) i/o port 071h rtc data register (r/w) a read of this register returns the value of t he register indexed by the rtc address register. a write of this register sets the value into the register indexed by the rtc address register i/o port 072h rtc extended address register (wo) 7 reserved. 6:0 rtc register index. a write of this register sends the data out on the isa bus and also causes rtcale to be triggered. (rtcale is an internal signal between the core logic module and the internal rtc controller.) i/o port 073h rtc data register (r/w) aa read of this register returns the value of the re gister indexed by the rtc extended address register. a write of this register sets the value into the register indexed by the rtc extended address register table 6-49. miscellaneous registers bit description i/o port 0f0h, 0f1h coprocessor erro r register (w) reset value: f0h a write to either port when the internal ferr# signal is assert ed causes the core logic module to assert internal ignne#. ignne # remains asserted until the ferr# de-asserts. i/o ports 170h-177h/376h-377h secondary ide registers (r/w) when the local ide functions are enabled, reads or writes to these registers cause the local ide interface signals to operate a ccording to their configuration rather than generating standard isa bus cycles. i/o ports 1f0h-1f7h/3f6h-3f7h primary ide registers (r/w) when the local ide functions are enabled, reads or writes to these registers cause the local ide interface signals to operate a ccording to their configuration rather than generating standard isa bus cycles. i/o port 4d0h interrupt edge/level select register 1 (r/w) reset value: 00h notes: 1. if icw1 - bit 3 in the pic is set as level, it overrides the setting for bits [7:3] in this register. 2. bits [7:3] in this register are used to configure a pci interrupt mapped to irq[ x] on the pic as level-sensitive (shared). 7 irq7 edge or level sensitive select. selects pic irq7 sensitivity configuration. 0: edge. 1: level. 6 irq6 edge or level sensitive select. selects pic irq6 sensitivity configuration. 0: edge. 1: level. 5 irq5 edge or level sensitive select. selects pic irq5 sensitivity configuration. 0: edge. 1: level. 4 irq4 edge or level sensitive select. selects pic irq4 sensitivity configuration. 0: edge. 1: level.
326 amd geode? sc3200 processor data book core logic module - isa legacy register space revision 5.1 3 irq3 edge or level sensitive select. selects pic irq3 sensitivity configuration. 0: edge. 1: level. 2:0 reserved . must be set to 0. i/o port 4d1h interrupt edge/level select register 2 (r/w) reset value: 00h notes: 1. if icw1 - bit 3 in the pic is set as level, it over rides the setting for bits 7:6 and 4:1 in this register. 2. bits [7:6] and [4:1] in this register are used to configure a pci interrupt mapped to irq[x] on the pic as level-sensitive (shared). 7 irq15 edge or level sensitive select. selects pic irq15 sensitivity configuration. 0: edge. 1: level. 6 irq14 edge or level sensitive select. selects pic irq14 sensitivity configuration. 0: edge. 1: level. 5 reserved . must be set to 0. 4 irq12 edge or level sensitive select. selects pic irq12 sensitivity configuration. 0: edge. 1: level. 3 irq11 edge or level sensitive select. selects pic irq11 sensitivity configuration. 0: edge. 1: level. 2 irq10 edge or level sensitive select. selects pic irq10 sensitivity configuration. 0: edge. 1: level. 1 irq9 edge or level sensitive select. selects pic irq9 sensitivity configuration. 0: edge. 1: level. 0 reserved. must be set to 0. table 6-49. miscellaneous registers (continued) bit description
amd geode? sc3200 processor data book 327 7 video processor module revision 5.1 7.0 video processor module the video processor module contains a high performance video back-end accelerator, a video/graphics mixer/ blender, a video input port (vip), supporting a tft inter- face. the back-end accelerator functions include horizontal and vertical scaling and filtering of the video stream. the mixer/blender function includes color space conversion, gamma correction, and mixing or alpha blending the video and graphics streams. general features hardware video acceleration graphics/video overlay and blending integrated pll - programmable up to 135 mhz selection of interlaced and progressive video from the gx1 module and the direct video port video input port (vip) ccir-656 compatible capture video/vbi modes direct video/vbi modes hardware video acceleration arbitrary x and y interpolation using three line-buffers yuv-to-rgb color space conversion horizontal filtering and downscaling supports 4:2:2, 4:2:0 yu v formats and rgb 5:6:5 format graphics-video over lay and blending overlay of video up to 16 bpp supports chroma key and color key for both graphics and video streams supports alpha-blending with up to three alpha windows that can overlap one another 8-bit alpha values with automatic increment or decre- ment on each frame optional gamma correction for video or graphics compatibility supports microsoft?s directdraw?/direct video and display control interface (dci) version 2.0 for full motion playback acceleration compliant with pc98 and pc99 v0.7 compatible with vesa, vga, dpms, and ddc2 standards for enhanced display control and power management tft interface tft modes: ? tft on ide: fpclk max is 40 mhz ? tft on parallel port: fpclk max is 80 mhz ? 640x480x16 bpp at 60-85 hz vertical refresh rates ? 800x600x16 bpp at 60-85 hz vertical refresh rates ? 1024x768x16 bpp at 60-75 hz vertical refresh rates ? 1280x1024x8 bpp at 60 hz vertical refresh rate
328 amd geode? sc3200 processor data book video processor module revision 5.1 7.1 module architecture figure 7-1 shows a top-level block diagram of the video processor. for information about the relationship between the video processor and the other modules of the sc3200, see section 2.2 on page 22. the video processor module includes the following functions: video input port ? ccir-656 decoder ? capture video/vbi modes ? direct video mode video formatter ? asynchronous video interface ? horizontal/vertical scalers ?filters mixer/blender ? overlay with color/chroma key ? gamma correction ? color space converters ? alpha blender tft interface dot clock pll the following subsections describe each block in detail. figure 7-1. video processor block diagram vip capture video/vbi bus master, video formatter horizontal downscaler, line buffer, horizontal and vertical upscalers, and filters mixer/blender overlay with gamma ram and alpha blending capture video/vbi data to gx1 video frame buffer vip data video data from gx1 video port video mux video data tft_if controller and direct video/vbi controller gx1 graphics data
amd geode? sc3200 processor data book 329 video processor module revision 5.1 7.2 functional description to understand why the video processor functions as it does, it is first important to understand the difference between video and graphics. video is pictures in motion, which usually starts out in an encoded format (i.e., mpeg2, avi, mpeg4) or is a tv broadcast. these pic- tures or frames are generally dynamic and are drawn 24 to 30 frames per second. conversely, graphic data is rela- tively static and is drawn - usually using hardware accelera- tors. most ia devices need to support both video and graphics displayed at the same time. for some ia devices, such as set-top boxes, video is dominant. while for other devices, such as consumer access devices and thin clients, graphics is dominant. what this means for the video pro- cessor is that for video cent ric devices, graphics overlays the video; and for graphics centric devices, video overlays the graphics. video support the sc3200 gets video from tw o sources, either the vip block or the gx1 module?s video frame buffer. the vip block supports the ccir-656 data protocol. the ccir-656 protocol supports tv data (ntsc or pal) and defines the format for active video data and vertical blanking interval (vbi) data. conforming ccir-656 data matches exactly what is needed for a tv: full frame, interlaced, 27 mhz pixel clock, and 50 or 60 hz refresh rate. full frame pixel resolution and the refresh rate depends on the tv stan- dard: ntsc, pal, or secam. if the vip input data is full frame (conforming data), the data can go directly from the vip block to the video for- matter. this is known as direct video mode. in this mode, the data never leaves the video processor module. direct video mode can only be used under very specific condi- tions which will be explained later. if the vip data is less than full frame (non conforming data), the vip block will bus master the video data to the gx1 module?s video frame buffer. the gx1 module?s display controller then moves the video data out of the video frame buffer and sends it to the video formatter. using this method the temporal (refresh rate) and/or spatial (image less then full screen) differences between the vip data and the output device are reconciled. this method is known as capture video mode. how each mode is setup and operates is explained further in section 7.2.1 on page 331. vbi support vbi (vertical blanking interval) data is placed in the video data stream during a portion of the vertical retrace period. the vertical retrace period physically consists of several horizontal lines (24 for ntsc and 25 for pal systems) of non-active video. data can be placed on some of these lines for other uses. the active video and vertical retrace period horizontal lines are logically defined into 23 types: logical line 2 through logical line 24 (no logical line 1). logical lines 2 through 23 occur during the vertical retrace period and logical line 24 represents all the active video lines. logical lines 10 through 21 for ntsc and 6 through 23 for pal are the nominal vbi lines. the rest of the logical lines, 2 through 9, 22, and 23 for ntsc and 2 through 6 for pal occur during the vertical retrace period but do not normally carry user data. an example of vbi usage is closed captioning, which occupies vbi logical line 21 for ntsc. figure 7-2 and figure 7-3 on page 330 show the (relationship between the) physical scan lines and logical scan lines for the odd and even fields in the ntsc format.
330 amd geode? sc3200 processor data book video processor module revision 5.1 figure 7-2. ntsc 525 lines, 60 hz, odd field figure 7-3. ntsc 525 lines, 60 hz, even field vertical retrace - logical lines 4-9 ? scan lines 4-9 vertical retrace - logical lines 10-21 ? scan lines 10-21 vertical retrace - logical lines 22, 23 ? scan lines 22, 23 active video logical line 24 ? scan lines 24-263 vertical retrace - logical line 24 ? scan line 1 vertical retrace - logical lines 2, 3 ? scan lines 2, 3 vsync start vbi_total_count_odd vbi_line_offset_odd (not normally user data) (nominal vbi lines) (not normally user data) (not normally user data) vsync end vertical retrace - logical lines 4-9 ? scan lines 267-272 nominal vbi lines 10-21 ? scan lines 273-284 vertical retrace - logical lines 22,23 ? scan lines 285, 286 (not normally user data) active video logical line 24 ? scan lines 287-525 vertical retrace - logical line 24 ? scan line 264 vertical retrace - logical lines 2, 3 ? scan lines 265, 266 (not normally user data) vsync end vbi_total_count_even vbi_line_offset_even (not normally user data) (nominal vbi lines) vsync start
amd geode? sc3200 processor data book 331 video processor module revision 5.1 7.2.1 video input port (vip) the vip block is designed to interface the sc3200 with external video processors (e.g., philips pnx1300 or sigma designs em8400) or external tv decoders (e.g., philips saa7114). it inputs ccir-656 video and raw vbi data sourced by those devices, decodes the data, and delivers the data directly to the video formatter (direct video mode) or to the gx1 module?s video frame buffer (capture video/vbi modes). figure 7-4 shows a diagram of the vip block. from the vip block?s perspective, direct video mode is always on. there are no regi sters that enable/disable direct video mode. the data source selected at the video mux (f4bar0+memory offset 400h[1:0]) determines if the data from the vip interface is moved directly or must be captured. two fifos in the vip block su pport the efficient movement of video and vbi data. for capture video/vbi modes, a 128-byte fifo buffers both vi deo and raw vbi data pro- cessed by the ccir-656 decoder. for direct video mode, there is a 2048-byte fifo that buffer the ccir-656 decoder?s video data. the fifo s are also used to provide clock domain changes. the vip interface clock (nominally 27 mhz) is the input clock domain for both fifos. for the capture video/vbi fifo, the data is clocked out using the fpci clock (33 or 66 mhz). for the direct video fifo, the video data is clocked out using the gx1?s video port clock (75, 116, or 133 mhz gx1 core clock divided by 2 or 4). 7.2.1.1 direct video mode as stated previously, direct video mode is on by default so no registers need to be programmed to support this mode other than to select the dire ct video data at the video mux. the video mux control register is located at f4bar0+mem- ory offset 400h[1:0]. direct video mode while supported is not an optimal mode of operation. this mode supports only one vertical resolu- tion and refresh rate, which is that of the incoming data. horizontal resolution can be scaled if desired. since the incoming data has odd and even fields, incoming line must be doubled for it to display properly. this is equivalent to the bob technique which is explained later in this section. genlock because video input data from the vip is sent directly, with- out significant buffering fram e-to-field synchronization is required with the gx1 module?s graphics data. this syn- chronization is known as g enlock. the genlock registers are located at f4bar0+memory offset 420h and 424h. figure 7-4. vip block diagram ccir-656 decoder capture video/vbi direct video capture video/vbi controller and capture video/vbi data fast-pci clock bus master fifo fifo fast x-bus to fast-pci bridge gx1 module fast-pci direct video/vbi controller vip data vip clock gx1 video clock direct video data f4bar2 control registers video mux to video formatter video or vbi data genlock control stop dclk vsync vip_vsync vip
332 amd geode? sc3200 processor data book video processor module revision 5.1 the genlock control hardware is used to synchronize the video input?s field with the gx1 module?s graphics frame. the graphics data is always sent full frame. for the gen- lock function to perform correctly, the gx1 module?s dis- play controller must be programmed to have a slightly faster frame time then the video input?s field time. this is best accomplished by programming the gx1 module?s dis- play controller with a few less (three to five) horizontal lines then the vip interface. genlock is accomplished by stop- ping the clock driving the gx1 module?s graphics frame until the vip vertical sync occurs (plus some additional delay, via f4bar0+memory offset 424h). the genlock function provides a timeout feature (genlock_tout_en, f4bar0 +memory offset 420h[4]) in case the video port input clock stops due to a problem with incoming video. 7.2.1.2 capture video mode capture video mode is a process for bus mastering video data received from the vip block to the gx1 module?s video frame buffer. the gx1 module?s display controller then moves the data from the video frame buffer to the video formatter. usually capture video mode is used because the data coming in from the vip block is interlaced and has a 30 hz refresh rate (ntsc format) and the tft panel, is progressive and has a 60 to 85 hz refresh rate. the capture video mode process must convert the inter- laced data to progressive data and change the frames per second. there are two methods to perform the interlaced to progressive conversion; bob and weave. each method uses a different mechanism to up the refresh rate bob the bob method displays the odd frame followed by the even frame. if a full-scale image is displayed, each line in the odd and even field must be vertically doubled (see sec- tion 7.2.2.5 "2-tap vertical and horizontal upscalers" on page 337) because each odd and each even field only con- tain one-half a frames worth of data. this me ans that the bob method reduces the video image resolution, but has a higher effective refresh rate. if there is a change of refresh rate from the vip block to the display device, then a field will sometimes be displayed twice. the advantage of this method is that the process is simple as only half the data is transmitted from the gx1 modul e?s video frame buffer to the video processor per a given amount of time, therefore reducing the memory bandwid th requirement. the disad- vantage is that there are some observable visual effects due to the reduction in resolution. figure 7-5 on page 333 is an example of how the bob method is performed. the ex ample assumes that the dis- play device is a tft at 85 hz refresh and single buffering is used for the data. the example does not assume anything regarding scaling that may be performed in the video pro- cessor. the example is only presented to allow for a gen- eral understanding of how the sc3200?s video support hardware works and not as an all-inclusive statement of operation. the following procedure is an example of how to create a bob method. this example assumes single buffering in the gx1 module?s video frame buffer. the video processor registers that control the vip bus master only need to be initialized. 1) program the vip bus master address registers. three registers control where the vip video data is stored in the gx1 module?s frame buffer: ? f4bar2+memory offset 20h ? video data odd base address ? f4bar2+memory offset 24h ? video data even base address ? f4bar2+memory offset 28h ? video data pitch the video data even base address must be sepa- rated from the video data odd base address by at least the field data size. the video data pitch register must be programmed to 00000000h. 2) program other vip bus master support registers. in f4bar2+memory offset 00 h, make sure that the vip fifo bus request threshold is set to 32 bytes (bit 22 = 1) and that the vid eo input port mode is set to ccir-656. an interrupt needs to be generated so that the gx1 module?s video frame buffer pointer can flip to the field that has completed transfer to the video frame buffer. so in f4bar2+memory offset 04h, enable the field interrupt bit. auto-flip is normally set to allow the ccir-656 decoder to identify which field is being pro- cessed. capture video data needs to be enabled and run mode capture is set to start capture at beginning of next field. data is now being captured to the frame buffer. 3) field interrupt. when the field interrupt occurs, the interrupt handler must program the gx1 module?s video buffer start off- set value (gx_base+memory offset 8320h) with the address of the field that was just received from the vip interface. this action will cause the display controller to ping-pong between the two fields. the new address will not take affect until the start of a new display con- troller frame. the field that was just received can be known by reading the current field bit at f4bar2+memory offset 08h[24].
amd geode? sc3200 processor data book 333 video processor module revision 5.1 figure 7-5. capture video mode bob example using one video frame buffer weave the weave method assembles the odd field and even field together to form the complete frame, and then renders the ?weaved? frames to the display device. the video data is converted from interlaced to progressive. since both fields are rendered simultaneously, the gx1 module?s video frame buffer must be at least double buffered. the weave method has the advantage of not creating the temporal effects that bob does. the di sadvantage of weave is twice as much data is transferred from the video frame buffer to the video processor; meaning that weave uses more memory bandwidth. figure 7-6 on page 334 is an example of the weave method in action. as in the bob example (figure 7-5), a tpt panel at 85 hz refresh is assumed. double buffering of the incoming data is also assumed. the example does not assume anything about any scaling that may be done in the video processor. no attempt has been made to assure that this example is absolutely workable. the exam- ple is only presented to allow for a general understanding of how the sc3200?s video support hardware works. the following procedure is an example of how to create the weave method. since at least double buffering is required, more of the vip?s control registers are used for weave than required for bob during video runtime. 1) program the vip bus master address registers. three registers control where the vip video data is stored in the gx1 module?s frame buffer: ? f4bar2+memory offset 20h ? video data odd base address ? f4bar2+memory offset 24h ? video data even base address ? f4bar2+memory offset 28h ? video data pitch the video data even base address must be sepa- rated from the video data odd base address by one horizontal line. the video data pitch register must be programmed to one horizontal line. 2) program other vip bus master support registers. ensure the vip fifo bus re quest threshold is set to 32 bytes (f4bar2+memory offset 00h[22] = 1) and the video input port mode is set to ccir-656 (f4bar2+memory offset 00h[1:0] = 10). an interrupt needs to be generated so that the gx1 module?s video frame buffer pointer can flip to the field that has com- pleted transfer to the video frame buffer. so the field interrupt bit (f4bar2+memo ry offset 04h[16] = 1). must be enabled. auto-flip is normally set (f4bar2+memory offset 04h[10] = 0) to allow the ccir-656 decoder to identify which field is being pro- cessed. capture video data needs to be enabled (f4bar2+memory offset 04h[10] = 1) and run mode capture is set to start capture (f4bar2+memory off- set 04h[1:0] = 11) at beginning of next field. data is now being captured to the frame buffer. video data odd base video data even base dc_vid_st_offset odd field even field gx1 module?s video frame buffer 1234567891011121314151617 1234 67891011121314151617181920 2223 capture video fill video subsystem 85 frames per second 5 5 21 30 frames per second (f4bar2+memory offset 24h) address not changed during runtime (gx_base+memory offset 8320h) ping-pongs between the two buffers during runtime (f4bar2+memory offset 20h) address not changed during runtime buf #1 sequence empty sequence
334 amd geode? sc3200 processor data book video processor module revision 5.1 3) field interrupt. when the field interrupt occurs on the completion of an odd field, the interrupt must program the video data odd base address with the other buffer?s address. the odd field will ping-pong between the two buffers. when the interrupt is due to the completion of an even field, the interrupt handler must program the gx1 module?s video buffer start offset value (gx_base+memory offset 8320h) with the address of the frame (both odd and even fields) that was just received from the vip block. this new address will not take affect until the start of a new frame. it must also program the video data even base address with the other buffer so that the even field will ping-pong just like the odd field. the field just received can be known by reading the cur- rent field bit (f4bar2+memory offset 08h[24]). 7.2.1.3 capture vbi mode there are three types of vbi data defined by the ccir-656 protocol: task a data, task b data, and ancillary data. the vip block supports the captur e for each data type. gener- ally task a data is the data ty pe captured. just as in cap- ture video mode, there are three registers that tell the bus master where to put the raw vbi data in the gx1 module?s frame buffer. once the raw vbi data has been captured, the data can be manipulated or decoded. the data can also be used by an application. an example of this would be an internet address that is encoded on one or more of the vbi lines, or have an application decode the closed captioning information put in the graphics frame buffer. the registers, f4bar2+memory offset 40h, 44h, and 48h, tell the bus master the destination addresses for the vbi data in the gx1 module?s frame buffer. five bits (f4bar2+memory offset 00h[21:17]) are used to tell the bus master the data types to store. capture vbi mode needs to be enabled at f4bar2+memory offset 04h[9,1:0]. the field interrupt bit (f4bar2+memory offset 04h[16]) should be used by the software driver to know when the captured vbi data has been completed for a field. figure 7-6. capture video mode weave example using two video frame buffers video data odd base f 4bar2+memory offset 20h video data even base f4bar2+memory offset 20h vid_start_offset gx_base+memory offset 8320h ping-pongs between the two buffers during runtime gx1 module?s video frame buffer 12 4567891011121314151617 1234 67891011121314151617181920 22 capture video fill sequence gx1 module?s display 5 5 21 video data even base f 4bar2+memory offset 24h video data even base f4bar2+memory offset 24h odd and even fields are buf #2 video frame buffer #1 video frame buffer #2 18 23 5 11 3 7 line 1 odd field line n odd field line 2 odd field line 1 even field line 2 even field line n-1 odd field line n-1 even field line n odd field line n even field line 1 odd field line 1 even field line 2 odd field line 2 even field line n-1 odd field line n-1 even field line n even field 15 18 85 frames per second 30 frames per second buf #1 controller empty sequence ?weaved? together ping-pongs between the two buffers during runtime
amd geode? sc3200 processor data book 335 video processor module revision 5.1 7.2.2 video block the video block receives video data from the vip block or the gx1 module?s video frame buffer. the video data is for- matted and scaled and then sent to the mixer/blender. the video data also changes clock domains while in the video block. it is clocked in with the gx1 module?s video clock and it is clocked out with the gx1 module?s graphics clock. a diagram of the video block is shown in figure 7-7. 7.2.2.1 video in put formatter the video input formatter accepts video data 8 bits at a time in yuv 4:2:2, yuv 4:2:0, or rgb 6:5:6 format. the gx1 module?s video clock is the source clock. the data can be interlaced or progressive. when the data comes directly from the vip block it is usually interlaced. the video format is configured via the en_42x bit (f4bar0+memory offset 00h[28] and the gv_sel bit (f4bar0+memory offset 4ch[13]). the byte order for each format is configured in the vid_fmt bits (f4bar0+offset 00h[3:2]). rgb 5:6:5 ? for this format each pixel is described as a 16-bit value: bits [15:11] = red bits [10:5] = green bits [4:0] = blue yuv 4:2:0 ? this format is not supported by the gx1 mod- ule. the horizontal downscaler in the video block cannot be used if the video data is in this format. in this format, 4 bytes of data are used to describe two pixels. the 4 bytes contain two y values one for each pixel; one u and one v for both pixels. for each horizontal line, all the y values are received first. the u values are received next and the v values are received last. for example for a horizontal line that has 720 pixels, there are 720 bytes of y, followed by 360 bytes of u, followed by 360 bytes of v. yuv 4:2:2 ? in this format each dword in the horizontal line represent two pixels. there are two y values and one each u and v in a dword. just as in the yuv 4:2:0 for- mat, each u and v value describes the two pixels. figure 7-7. video block diagram video input formatter 4-tap horizontal downscaler m m+1 1 m+1 or gx1 direct video input line buffer 0 line buffer 1 line buffer 2 formatter 4:4:4 2-tap vertical interpolating upscaler 24 24 24 2-tap horizontal interpolating upscaler yuv 4:4:4/rgb 5:6:5 video module 8 8 (3x360x32 bit) (4:2:2 or 4:2:0)
336 amd geode? sc3200 processor data book video processor module revision 5.1 7.2.2.2 horizontal downscal er with 4-tap filtering the video processor implements up to 8:1 horizontal downscaling with 4-tap filtering for horizontal interpolation. filtering is performed on video data input to the video pro- cessor. this data is fed to the filter and then to the down- scaler. there is a bypass path for both filtering and downscaling logic. if this bypass is enabled, video data is written directly into the line buffers. (see figure 7-8.) filtering there are four 4-bit coefficients which can have pro- grammed values of 0 to 15. th e filter coefficients can be programmed via the video downscaler coefficient register (f4bar0+memory offset 40h) to increase picture quality. horizontal downscaler the video processor supports horizontal downscaling. the downscaler can be implemented in the video processor to shrink the video window by a factor of up to 8:1, in 1-pixel increments. the downscaler factor (m) is programmed in the video downscaler control register (f4bar0+memory offset 3ch[4:1]). if bit 0 of this register is set to 0, the down- scaler logic is bypassed. the horizontal downscaler supports downscaling of video data input format yuv 4:2:2 only. the downscaler supports up to 29 downscaler factors. there are two types of factors: type a is (1/m+1). one pixel is retained, and m pixels are dropped. this enables down scaling factors of 1/16, 1/15, 1/14, 1/13, 1/12, 1/11, 1/ 10, 1/9,1/8, 1/ 7, 1/6, 1/5, 1/4, 1/3, and 1/2. type b is (m/m+1). m pixels are retained, and one pixel is dropped. this enables downscaling factors of 2/3, 3/4, 4/5, 5/6, 6/7, 7/8, 8/9, 9/10 , 10/11, 11/12, 12/13, 13/14, 14/15, and 15/16. bit 6 of the video downscaler control register (f4bar0+memory offset 3ch) selects the type of down- scaling factor to be used. note: there is no vertical downscaling in the video pro- cessor. figure 7-8. horizontal downscaler block diagram bypass 4-tap horizontal 4x4 downscale video input filtering coefficients downscaler factors to l i n e buffers
amd geode? sc3200 processor data book 337 video processor module revision 5.1 7.2.2.3 line buffers after the data has been optionally horizontally downscaled the video data is stored in a 3-line buffer. each line is 360 dwords, which means a line width of up to 720 pixels can be stored. this buffer supports two functions. first, the clock domain of the video data changes from the gx1 module?s video clock to the gx1 module?s graphics clock. this clock domain change is required because the video data and graphics data can only be mixed/blended in the same clock domain. the second function the line buffer performs is to provide the necessary look ahead and look behind data in the vertical direction for the vertical upscaler. there is no direct program control of the line buffer. 7.2.2.4 formatter video data in yuv 4:2:2 or yuv 4:2:0 format is converted to yuv 4:4:4 format. rgb data is not translated. there is no direct program control of the formatter. 7.2.2.5 2-tap vertical an d horizontal upscalers after the video data has been buffered, the upscaling algo- rithm can be applied. the video processor employs a digi- tal differential analyzer-style (dda) algorithm for both horizontal and vertical upscaling. the scaling parameters are programmed via the video upscale register (f4bar0+memory offset 10h). the scalers support up to 8x factors for both horizontal and vertical scaling. the scaled video pixel stream is then passed through bi-linear interpolating filters (2-tap, 8-phase) to smooth the output video, significantly enhancing the quality of the displayed image. the x and y upscaler uses the dda and linear interpolat- ing filter to calculate (via inte rpolation) the values of the pix- els to be generated. the interpolation formula uses a i,j , a i,j+1 , a i+1,j , and a i+1,j+1 values to calculate the value of intermediate points. the act ual location of calculated points is determined by the dda algorithm. the location of each intermediate point is one of eight phases between the original pixels (see figure 7-9). figure 7-9. linear interpolation calculation b 1 b 2 x z y a i,j+1 a i+1,j+1 a i+1,j a i,j notes: x and y are 0 - 7 b 1 a ij , () 8 y ? 8 ----------- - a i 1 j , + () y 8 -- - + = b 2 a ij ,1 + () 8 y ? 8 ----------- - a i 1 j 1 + , + () y 8 -- - + = zb 1 () 8 x ? 8 ----------- - b 2 () x 8 -- - + =
338 amd geode? sc3200 processor data book video processor module revision 5.1 7.2.3 mixer/blender block the mixer/blender block of the video processor module performs all the necessary functions to properly mix/blend the video data and the graphics data. these functions include color space conversion (csc), optional gamma correction, color/chroma key, and the mixing/blending logic. see figure 7-10 for block diagram of the mixer/blender block. video/graphics mixing/blending must be performed in the rgb format. the yuv to rgb csc (section 7.2.3.1 on page 339) must be used on the video data if it is in yuv format. there is not a post mix/blend yuv to rgb csc to support the tft output. if gamma correction (see section 7.2.3.2) on the video data is desired, it must be done in the color space of the input video data, which can be either yuv or rgb. if gamma correction on the graphics data is desired, it must be done in the color space of the input graphics data, which is rgb. the video data can be in progressive or interlaced format, while the graphics data is always in the progressive format. the mixer/blender can mix/blend either format of video data with graphics data. f4bar0+memory offset 4ch[9] programs the mix/blend format. considering the color space and the data format, the mixer/blender supports five types of mixing/blending. some of the mixing/blending types have additional programming considerations to enable them to work optimally. the valid mixing/blending configurations are listed in see table 7-1 on page 339 along with any additional pr ogramming requirements. figure 7-10. mixer/blender block diagram 01 10 video, 4:4:4 graphics, csc_for_ optional gamma correction ram csc yuv to rgb color/chroma key and mixer/blender crt dacs and tft interface 1/2 y flicker filter flicker_filt_cntrl = 01 01 /gv_gamma_sel * /gamma_en gv_gamma_sel * /gamma_en gv_gamma_sel csc_for_video 01 01 csc rgb to yuv 10 yuv or rgb cursor color key 01 color_chroma_sel color/chroma key graphics compare compare rgb yuv data tvout block
amd geode? sc3200 processor data book 339 video processor module revision 5.1 7.2.3.1 yuv to rgb csc in video data path this csc must be enabled if the video data is in the yuv color space. the csc_for_ video bit, f4bar0+memory offset 4ch[10], controls this csc. yuv video data is passed through this csc to obtain 24-bit rgb data using the following ccir-601-1 recommended formula: r = 1.1640625(y ? 16) + 1.59375(v ? 128) g = 1.1640625(y ? 16) ? 0.8125(v ? 128) ? 0.390625(u ? 128) b = 1.1640625(y ? 16) + 2.015625(u ? 128) the csc clamps inputs to prevent them from exceeding acceptable limits. 7.2.3.2 gamma correction either the video or graphics data can be routed through an integrated palette ram for gamma correction. there are three 256-byte rams, one for each color component value. gamma correction supported in the yuv or rgb color space for the video data and rgb color space for the graphics data. gamma correction is accomplished by treat- ing each color component as an address into each ram. the output of the ram is the new color. a simple rgb gamma correction example is to increase each color com- ponent by one. the address 00h in the rams would con- tain the data 01h. the address 01h would contain the data 02h and so on. this would have the effect of increasing each original red, green, and blue value by one. g_v_gamma, f4bar0+memory offset 04h[21] selects which data path (video or graphics) to send to the gamma correction block. gamma_en, f4bar0+memory offset 28h[0] enables the gamma correction function. to l oad the gamma correction palette ram, use f4bar0+memory offset 1ch and 20h. 7.2.3.3 color/chroma key a color/chroma key mechanism is used to support the mixer/blender logic. there are two keys: key1 is for the cur- sor and key2 is for graphics or video data. key1, the cursor key, is always a color key. th e cursor color key registers are located at, f4bar0+memory offset 50h-5cf. how the cursor key mechanism works with the mixer/blender is explained in section 7. 2.3.4. color_chroma_key (f4bar0+memory offset 04h[20]) determines whether key2 is a color key or a chroma key. the video color key register (f4bar0+memory offset 14h) stores the key. color keying is used when video is overlaid on the graphics (gfx_ins_video, f4bar0+memo ry offset 4ch[8] = 0). chroma keying is used when graphics is overlaid on the video (gfx_ins_video = 1). how the color/chroma key mechanism works with the mixer/blender is explained in section 7.2.3.4. table 7-1. valid mixing/blending configurations mixing/blending 1 (bit) flicker filter 2 (bit) mode comment 13 11 10 9 30 29 001000i nput: yuv progressive video mixing: rgb produces highest quality rgb output (see section 7.2.1.2 "capture video mode", weave subsection on page 333). 100000i nput: rgb progressive video mixing: rgb produces highest quality rgb output (see section 7.2.1.2 "capture video mode", weave subsection on page 333). 010101i nput: yuv interlaced video mixing: yuv not supported. 010000i nput: yuv progressive video mixing: yuv not supported. 001000i nput: yuv interlaced video upscaled by 2 mixing: rgb typically direct video mode. must be vertically upscaled by a factor of 2 (see section 7.2.2.5 "2-tap vertical and horizontal upscalers" on page 337). 1. f4bar0+memory offset 4ch[13, 11:9]. 2. f4bar0+memory offset 814h[30:29].
340 amd geode? sc3200 processor data book video processor module revision 5.1 7.2.3.4 color/chroma key and mixer/blender the mixer/blender takes each pixel of the graphics and video data streams and mixes or blends them together. mixing is simply choosing the graphics pixel or the video pixel. blending takes a percentage of a graphics pixel (alpha_value * graphics_pixel_value) and percentage of the video pixel (1 - alpha_value * video_pixel_value) and adds them together. the perc entages of each add up to 100%. the actual formula is: blended pixel = (alpha_value * graphics_pixel_value) / 256 + ((256 ? alpha_value) * video_pixel_value) / 256 where: alpha_value = 0 to 255 mixing and blending are supported simultaneously for every rendered frame, however, each pixel can only be mixed or blended. the mix or blend question is decided by the pixel position, whether video is overlaid on the graphics or visa versa (gfx_ins_video, f4bar0+memory offset 4ch[8]), and several programmed ?windows?. figure 7-11 illustrates and example frame. graphics window the graphics window is defined in the gx1 module?s dis- play controller and is always the full screen resolution. video window the video window tells the mixer/blender where the video window is and its size. if direct video mode is enabled (see section 7.2.1.1 "direct video mode" on page 331), the video window must be defined as the resolution of the video port data resolution (720x480 for ntsc, 720x576 for pal). vertical scaling is not allowed. horizontal scaling is allowed. if the video source is from the gx1 module?s video frame buffer (which includes capture video mode, see section 7.2.1.2 "capture video mode" on page 332) then the video data can be scaled both horizontally and verti- cally. the video data size, scaled or unscaled, must equal the video window size. the video x position (horizontal) and video y position (vertical) registers (f4bar0+memory offset 08h and 0ch) define the video window. cursor window the cursor window can be managed two ways: with the gx1 module?s hardware cursor or a software cursor. when using the hardware cursor, the displayed colors of the hard- ware cursor must be the cursor color keys (see section 5.5.3 ?hardware cursor? in the amd geode? gx1 pro- cessor data book ). when the software cursor is used, the cursor size and position are not defined using registers. the cursor size, position, and image are determined through the use of the cursor color key colors in the graph- ics frame buffer. when the cursor is described in this man- ner, the cursor can be of any size and shape. alpha windows up to three alpha windows can be defined. they are used only for blending. they can be of any size up to the graph- ics window size and they may overlap. to support overlap- ping of the alpha windows they can be prioritized as to which one is on top (f4bar0+memory offset 4ch[20:16]). the alpha windows are programmed at f4bar0+memory offset 60h-88h. figure 7-11. graphics/video frame with alpha windows graphics window (gfx_ins_video = 0) video window alpha window #3 cursor window alpha1_win_priority = 10 alpha2_win_priority = 01 alpha3_win_priority = 00 video x video y position register alpha window 3 x position alpha window 3 y position register register alpha window #2 alpha window #1 position register
amd geode? sc3200 processor data book 341 video processor module revision 5.1 mixing/blending operation table 7-2 on page 341 shows the truth table used to create th e flow diagram, figure 7-12 on page 342, that the mixer/ blender logic uses to determine each pixels disposition. table 7-2. truth table for alpha blending color_ chroma_sel 1 1. color_chroma_sel: f4bar0+memory offset 04h[20]. windows configuration 2 2. gfx_ins_video: f4bar0+memory offset 4ch[8]. alphax_color_reg_en: f4bar0+memory offsets 68h[24], 78h[24], and 88h[24]. graphics data match cursor color key graphics data match normal color key video data match normal color key mixer output x x x yes x x cursor color x not in video window x no x x graphics data graphics color key (color_ chroma_sel = 0) not in an alpha window gfx_ins_video = 0 no yes x video data no no x graphics data gfx_ins_video = 1 no x x video data inside alpha window x alphax_color_reg_en = 1 no yes x color from color register alphax_color_reg_en = 0 no yes x video data x no no x alpha-blended data video chroma key (color_ chroma_sel = 1) not in an alpha window gfx_ins_video = 0 no x yes graphics data no x no video data gfx_ins_video = 1 no x x graphics data inside alpha window x alphax_color_reg_en = 1 no x yes color from color register alphax_color_reg_en = 0 no x yes graphics data x no x no alpha-blended data
342 amd geode? sc3200 processor data book video processor module revision 5.1 figure 7-12. color key and alpha blending logic color register enabled for this window ?graphics 2 inside video? is enabled cursor color key matches graphics value pixel outside the video window no ye s use selected cur- sor color for pixel no no pixel value 3 matches normal color key ye s no blend graphics values and video values using the alpha value for this window pixel value 3 matches normal color key no use graphics value for this pixel ye s ye s replace the value with the color register value ye s start notes: 1) alpha window should not be pl aced outside of the video window. 2) ?graphics inside video? is enabled via bit gfx_ins_video in the video de-interlacing and alpha control register (f4bar0+memory offset 4ch[8]). 3) the ?pixel value? refers to either the video value or the graphics value, depending on the setting of bit color_chroma_sel in the display configuration register (f4bar0+memory offset 04h[20]). ye s use graphics value for this pixel use video value for this pixel ye s color_chroma _sel = 1 no no no ye s use graphics value for this pixel use video value for this pixel no ye s ye s no pixel inside 1 alpha window color_chroma _sel = 1 color_chroma _sel = 1
amd geode? sc3200 processor data book 343 video processor module revision 5.1 7.2.4 tft interface the tft interface can be programmed to one of two sets of balls: ide balls or parallel port balls. pmr[23] of the gen- eral configuration registers program where the tft inter- face exists (see table 4-2 on page 88). note: if the tft interface is on the ide balls, the maxi- mum fpclk supported is 40 mhz. if the tft inter- face is on the parallel port balls the maximum fpclk supported is 80 mhz. support for a tft panel requires power sequencing and an 18-bit (6-bit rgb), digital output. the relevant digital output signals are available from the sc3200. tft output signals are: tftd[5:0] for blue signals tftd[11:6] for green signals tftd[17:12] for red signals hsync and vsync - sync signals tftdck - data clock signal. tftde - data enable signal. fp_vdd_on - power control signal power sequence power sequence is used to control assertion of fp_vdd_on and tftd signals. all bits related to power sequence configuration are located in the display configuration register (f4bar0+memory offset 04h). after enabling tft_en (bit 0), and fp_pwr_en (bit 6), the state machine waits until the next vsync to switch on the fp_vdd_on signal. the st ate machine then asserts the tftd[17:0] si gnals after the delay programmed via pwr_seq_dly (bits [19:17]) when fp_pwr_en (bit 6) is set to 0, the reverse sequence happens for powering down the tft. figure 7-13. tft power sequence fp_vdd_on fp_pwr_en tftd[17:0], hsync, vsync, tftde, tftdck t 1 t 1 t 0 +t 1 t 0 t 0 is time to next vsync t 1 is a programmable multiple of frame time bit
344 amd geode? sc3200 processor data book video processor module revision 5.1 7.2.5 integrated pll the integrated pll can generate frequencies up to 135 mhz from a single 27 mhz source. the clock frequency is programmable using two registers. figure 7-14 shows the block diagram of the video processor integrated pll. f ref is 27 mhz, generated by an external crystal and an integrated oscillator. f out is calculated from: f out = (m + 1) / (n+ 1) x f ref the integrated pll can generate any frequency by writing into the ?m? and ?n? bit fields (fbar0+memory offset 2ch, m = bits [14:8] and n = bits [3:0]). additionally, 16 prepro- grammed vga frequencies can be selected via the pll clock select register (f4bar0+memory offset 2ch[19:16]), if the crystal o scillator has a frequency of 27 mhz. this pll can be powered down via the miscella- neous register (f4bar0+memory offset 28h[12]). figure 7-14. pll block diagram f ref f out n phase charge m vco compare divider divider pump loop filter out divide
amd geode? sc3200 processor data book 345 video processor module - register summary revision 5.1 7.3 register descriptions the register space for accessing and configuring the video processor is located in the core logic chipset register space (f0-f5). the chipset register space is accessed via the pci interface using the pci type one configuration mechanism (see section 6.3.1 "pci configuration space and access methods" on page 191). 7.3.1 register summary the tables in this subsection summarize the registers of the video processor. included in the tables are the regis- ter?s reset values and page references where the bit for- mats are found. table 7-3. f4: pci header registers for video processor support summary f4 index width (bits) type name reset value reference (table 7-6) 00h-01h 16 ro vendor identification register 100bh page 348 02h-03h 16 ro device identification register 0504h page 348 04h-05h 16 r/w pci command register 0000h page 348 06h-07h 16 ro pci status register 0280h page 348 08h 8 ro device revision id register 01h page 348 09h-0bh 24 ro pci class code register 030000h page 348 0ch 8 ro pci cache line size register 00h page 348 0dh 8 ro pci latency timer register 00h page 348 0eh 8 ro pci header type register 00h page 348 0fh 8 ro pci bist register 00h page 348 10h-13h 32 r/w base address register 0 (f 4bar0). sets the base address for the memory-mapped video configuration registers within the video processor. refer to table 7-7 on page 350 for programming infor- mation regarding the register offs ets accessed through this regis- ter. 00000000h page 348 14h-17h 32 r/w base address register 1 (f4bar1). reserved. 00000000h page 348 18h-1bh 32 r/w base address register 2 (f4bar2). sets the base address for the memory-mapped vip (video interface port) registers (summa- rized in table 7-8 on page 363). 00000000h page 348 1ch-2bh -- -- reserved 00h page 348 2ch-2dh 16 ro subsystem vendor id 100bh page 348 2eh-2fh 16 ro subsystem id 0504h page 348 30h-3bh -- -- reserved 00h page 348 3ch 8 r/w interrupt line register 00h page 348 3dh 8 r/w interrupt pin register 03h page 349 3eh-ffh --- --- reserved 00h page 349 table 7-4. f4bar0: video processor configuration registers summary f4bar0+ memory offset width (bits) type name reset value reference (table 7-7) 00h-03h 32 r/w video configuration register 00000000h page 350 04h-07h 32 r/w display configuration register x0000000h page 351 08h-0bh 32 r/w video x position register 00000000h page 352 0ch-0fh 32 r/w video y position register 00000000h page 352 10h-13h 32 r/w video upscaler register 00000000h page 352 14h-17h 32 r/w video color key register 00000000h page 353 18h-1bh 32 r/w video color mask register 00000000h page 353 1ch-1fh 32 r/w palette addres s register xxxxxxxxh page 353 20h-23h 32 r/w palette data register xxxxxxxxh page 353 24h-27h 32 ro reserved --- page 353
346 amd geode? sc3200 processor data book video processor module - register summary revision 5.1 28h-2bh 32 r/w miscellaneous register 00001400h page 354 2ch-2fh 32 r/w pll2 clock select register 00000000h page 354 30h-33h 32 --- reserved 00000000h page 354 34h-37h 32 ro reserved 00000000h page 354 38h-3bh 32 ro reserved 00000000h page 354 3ch-3fh 32 r/w video downscaler control register 00000000h page 355 40h-43h 32 r/w video downscaler coefficient register 00000000h page 355 44h-47h 32 r/w crc signature register xxxxx100h page 355 48h-4bh 32 ro device and revision identification 0000015xh page 355 4ch-4fh 32 r/w video de-interlacing and alpha control register 00060000h page 356 50h-53h 32 r/w cursor color key register 00000000h page 357 54h-57h 32 r/w cursor color mask register 00000000h page 357 58h-5bh 32 r/w cursor color register 1 00000000h page 357 5ch-5fh 32 r/w cursor color register 2 00000000h page 357 60h-63h 32 r/w alpha window 1 x position register 00000000h page 358 64h-67h 32 r/w alpha window 1 y position register 00000000h page 358 68h-6bh 32 r/w alpha window 1 color register 00000000h page 358 6ch-6fh 32 r/w alpha window 1 control register 00000000h page 358 70h-73h 32 r/w alpha window 2 x position register 00000000h page 359 74h-77h 32 r/w alpha window 2 y position register 00000000h page 359 78h-7bh 32 r/w alpha window 2 color register 00000000h page 359 7ch-7fh 32 r/w alpha window 2 control register 00000000h page 359 80h-83h 32 r/w alpha window 3 x position register 00000000h page 360 84h-87h 32 r/w alpha window 3 y position register 00000000h page 360 88h-8bh 32 r/w alpha window 3 color register 00000000h page 360 8ch-8fh 32 r/w alpha window 3 control register 00000000h page 360 90h-93h 32 r/w video request register 001b0017h page 361 94h-97h 32 ro alpha watch register 00000000h page 361 98h-3ffh --- reserved --- page 361 400h-403h 32 r/w video processor display mode register 00000000h page 361 404h-407h 32 --- reserved 00000000h page 361 408h-40bh 32 r/w video processor test mode register 00000000h page 361 40ch-41fh --- --- reserved 00000000h page 361 420h-423h 32 r/w genlock register 00000000h page 362 424h-427h 32 r/w genlock delay register 00000000h page 362 428h-43bh --- --- reserved --- page 362 43ch-43fh 32 r/w continuous genlock time-out register 1fff1fffh page 362 table 7-4. f4bar0: video processor configuration registers summary (continued) f4bar0+ memory offset width (bits) type name reset value reference (table 7-7)
amd geode? sc3200 processor data book 347 video processor module - register summary revision 5.1 table 7-5. f4bar2: vip support registers summary f4bar2+ memory offset width (bits) type name reset value reference (table 7-8) 00h-03h 32 r/w video interface port configuration register 00000000h page 363 04h-07h 32 r/w video interface control register 00000000h page 363 08h-0bh 32 r/w video interface status register xxxxxxxxh page 364 0ch-0fh -- -- reserved 00000000h page 365 10h-13h 32 ro video current line register xxxxxxxxh page 365 14h-17h 32 r/w video line target register 00000000h page 365 18h-1fh --- --- reserved 00000000h page 365 20h-23h 32 r/w video data odd base register 00000000h page 365 24h-27h 32 r/w video data even base register 00000000h page 365 28h-2bh 32 r/w video data pitch register 00000000h page 365 2ch-3fh -- -- reserved 00000000h page 365 40h-43h 32 r/w vbi data odd base register 00000000h page 366 44h-47h 32 r/w vbi data even base register 00000000h page 366 48h-4bh 32 r/w vbi data pitch register 00000000h page 366 4ch-1ffh -- -- reserved 00000000h page 366
348 amd geode? sc3200 processor data book video processor module - video processor registers - function 4 revision 5.1 7.3.2 video processor registers - function 4 the register space designated as function 4 (f4) is used to configure the pci portion of support hardware for accessing the video processor support registers, including vip (separate bar). the bit formats for the pci header registers are given in table 7-6. located in the pci header registers of f4 are three base address registers (f4barx) used for pointing to the regis- ter spaces designated for video processor support. f4bar0 is for video processor configuration, f4bar1 is reserved, and f4bar2 is for vip configuration. table 7-6. f4: pci header registers for video processor support registers bit description index 00h-01h vendor identification register (ro) reset value: 100bh index 02h-03h device identification register (ro) reset value: 0504h index 04h-05h pci command register (r/w) reset value: 0000h 15:2 reserved. (read only) 1 memory space. allow the core logic module to respond to memory cycles from the pci bus. 0: disable. 1: enable. this bit must be enabled to access memory offsets th rough f4bar0, f4bar1, and f4bar2 (see f4 index 10h, 14h, and 18h). 0 reserved. (read only) index 06h-07h pci status register (ro) reset value: 0280h index 08h device revision id register (ro) reset value: 01h index 09h-0bh pci class code register (ro) reset value: 030000h index 0ch pci cache line size register (ro) reset value: 00h index 0dh pci latency timer register (ro) reset value: 00h index 0eh pci header type (ro) reset value: 00h index 0fh pci bist register (ro) reset value: 00h index 10h-13h base address register 0 - f4bar0 (r/w) reset value: 00000000h video processor video memory address space. this register allows pci access to the memory mapped video processor configura- tion registers. bits [11:0] ar e read only (0000 0000 0000) indicating a 4 kb memory address range. see table 7-7 on page 350 for bit formats and reset values of the registers ac cessed through this base address register. 31:12 video processor video memory base address. 11:0 address range. (read only) index 14h-17h base address register 1 - f4bar1 (r/w) reset value: 00000000h reserved index 18h-1bh base address register 2 - f4bar2 (r/w) reset value: 00000000h vip address space. this register allows access to memo ry mapped vip (video interface port) rela ted registers. bits [11:0] are read only (0000 0000 0000), indicating a 4 kb i/o address range. refer to table 7-8 for the vip register bit formats and reset value s. 31:12 vip base address. 11:0 address range. (read only) index 1ch-2bh reserved reset value: 00h index 2ch-2dh subsystem vendor id (ro) reset value: 100bh index 2eh-2fh subsystem id (ro) reset value: 0504h index 30h-3bh reserved reset value: 00h index 3ch interrupt line register (r/w) reset value: 00h this register identifies the system interrup t controllers to which the device?s interr upt pin is connected. the value of this r egister is used by device drivers and has no direct meaning to this function.
amd geode? sc3200 processor data book 349 video processor module - video processor registers - function 4 revision 5.1 index 3dh interrupt pin register (r/w) reset value: 03h this register selects which interrupt pin the device uses. vip uses intc# after reset. inta#, intb# or intd# can be selected by writing 1, 2 or 4, respectively. index 3eh-ffh reserved reset value: 00h table 7-6. f4: pci header registers for video processor support registers (continued) bit description
350 amd geode? sc3200 processor data book video processor module - video processor registers - function 4 revision 5.1 7.3.2.1 video proc essor support registers - f4bar0 f4 index 10h, base address re gister 0 (f4bar0) sets the base address that allows pci access to the video proces- sor support registers, not including vip. a separate base address register (f4bar2) is used to access vip support registers (see secti on 7.3.2.2 on page 363). note: reserved bits that are not defined as ?must be set to 0 or 1" should be written with a value that is read from them. table 7-7. f4bar0+memory offset: video processor configuration registers bit description offset 00h-03h video co nfiguration register (r/w) reset value: 00000000h configuration register for options of the motion video acceleration hardware. 31:29 reserved. must be set to 0. 28 en_42x (enable 4:2:x format). allows format selection. 0: 4:2:2 format. 1: 4:2:0 format. note: when input video stream is rgb (i.e., f4bar0+memory offset 4ch[13] = 1), this bit must be set to 0. 27 bit_8_line_size. when enabled, this bit increases line size from vid_lin_siz (bits [15:8]) dwords by adding 256 dwords. 0: disable. 1: enable. 26:25 reserved. must be set to 0. 24:16 init _ rd _ addr (initial buffer read address). this field preloads the starting read address for the line buffers at the beginning of each display line. it is used for hardware clipping of the video window at the left edge of the active display. it represents the dword address of the source pixel which is to be displayed first. for an unclipped window, this va lue should be 0. for 4:2:0 format, set bits [17:16] to 00. 15:8 vid_lin_siz (video line size). represents the number of dwords that make up the horizontal size of the source video data. 7 yfilt_en (y filter enable). enables/disables the vertical filter. 0: disable. upscaling done by repeating pixels. 1: enable. upscaling done by interpolating pixels. note: this bit is used with y upscaling logic. reset to 0 when not required. 6 xfilt_en (x filter enable). enables/disables the horizontal filter. 0: disable. upscaling done by repeating pixels. 1: enable. upscaling done by interpolating pixels. note: this bit is used with x upscaling logic. reset to 0 when not required. 5:4 reserved. 3:2 vid_fmt (video format). byte ordering of video data on the video input bus (vpd[7:0]). the interpretation of these bits depends on the settings of bit 13 (gv_sel) in the video de-interlacing and alpha cont rol register (f4bar0+memory offset 4ch) and bit 28 (en_42x) of this register. if gv_sel = 0 and en_42x = 0: 00: cb y0 cr y1 10: y0 cb y1 cr 01: y1 cr y0 cb 11: y0 cr y1 cb if gv_sel = 0 and en_42x = 1: 00: y0 y1 y2 y3 10: y1 y0 y3 y2 01: y3 y2 y1 y0 11: y1 y2 y3 y0 if gv_sel = 1 and en_42x = 0: 00: p1l p1m p2l p2m 10: p1m p1l p2m p2l 01: p2m p2l p1m p1l 11: p1m p2l p2m p1l if gv_sel = 1 and en_42x = 1: reserved note: both rgb 5:6:5 and yuv 4:2:2 contain two pixels in each 32-bit dword. yuv 4:2:0 contains a stream of y data for each line, followed by u and v data for that same line. 1 reserved.
amd geode? sc3200 processor data book 351 video processor module - video processor registers - function 4 revision 5.1 0 vid_en (video enable). enables video acceleration hardware. 0: disable (reset) video module. 1: enable. offset 04h-07h display co nfiguration register (r/w) reset value: x0000000h general configuration register for display control. this register is also used to determine how graphics and video data are to be com- bined in the display on the output device. 31 reserved. write as read. 30:28 reserved. 27 fp_on_status (flat panel on status). (read only) shows whether power to the attached flat panel is on or off. this bit transitions at the end of the power-up or power-down sequence. 0: power to the flat panel is off. 1: power to the flat panel is on. 26 reserved. set to 0. 25 reserved. must be set to 0. 24:22 reserved. set to 0. 21 gv_gamma_sel (graphics or video gamma source data). selects whether the graphics or video data goes to the gamma correction ram. gamma_en (f4bar0+memory offset 28h[0]) must be enabled for the selected data source to pass through the gamma correction ram. 0: graphics data to gamma correction ram. 1: video data to gamma correction ram. note: gamma correction is always in th e rgb domain for graphics data. gamma correction can be in the yu v or rgb domain for video data. 20 color_chroma_sel (color or chroma key select). selects whether the graphics is used for color keying or the video data stream is used for chroma keying. 0: graphics data is compared to the color key. 1: video data is compared to the chroma key. 19:17 pwr_seq_dly (power sequence delay). selects the number of frame periods that transpire between successive transi- tions of the power sequence control lines. 16:14 reserved. write as read. 13:8 reserved. write as read. 7 fp_data_en (flat panel output enable). controls the data, data-enable, clock and sync output signals. 0: flat panel data outputs are forced to zero depending on the value of bit 3 (bl_en). bit 6 (fp_pwr_en ) is ignored. 1: flat panel outputs are forced to zero until power-up, and la ter, data outputs are subject to the value of bit 3 (bl_en). 6 fp_pwr_en (flat panel power enable). changing this bit initiates a flat panel power-up or power-down. 0-to-1: power-up flat panel. 1-to-0: power-down flat panel. 5:4 reserved. 3 bl_en (blank enable). controls blanking of tft data. 0: tft data is constantly blanked. 1: tft data is blanked normally (i.e., during horizontal and vertical blank). 2 vsync_en (vertical sync enable). enables/disables display vertical sync (used for vesa dpms support). 0: disable. 1: enable. 1 hsync_en (horizontal sync enable). enables/disables display horizontal sync (used for vesa dpms support). 0: disable. 1: enable. 0 tft_en (tft enable). enables the tft control logic and is al so used to reset the tft control logic. 0: reset tft control logic. 1: enable tft control logic. table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
352 amd geode? sc3200 processor data book video processor module - video processor registers - function 4 revision 5.1 offset 08h-0bh video x position register (r/w) reset value: 00000000h provides the window x position. th is register is programmed relative to crt horiz ontal sync input (not physical screen position ). note: h_total and h_sync_end are values programmed in the gx1 module?s display cont roller timing registers (gx_base+memory offset 8330h[26:19] and 8338h[10:3], respectively). the value of (h_total ? h_sync_end) is some- times referred to as ?horizontal back porch?. for more information, see the amd geode? gx1 processor data book . 31:28 reserved. 27:16 vid_x_end (video x end position). represents the horizontal end position of t he video window (not inclusive). this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 13. 15:12 reserved. 11:0 vid_x_start (video x start position). represents the horizontal start position of the video window. this value is calcu- lated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 14. offset 0ch-0fh video y position register (r/w) reset value: 00000000h provides the window y position. this register is programmed relative to crt vertical sync input (not physical screen position). note: v_total and v_sync_end are values programmed in the gx1 module?s display controller timing registers (gx_base+memory offset 8340h[26:16] and 8348h[26:16], respectively). the value of (v_total ? v_sync_end) is some- times referred to as ?vertical back porch?. for more information, see the amd geode? gx1 processor data book . 31:27 reserved. 26:16 vid_y_end (video y end position). represents the vertical end position of the vi deo window (not inclusive). this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. 15:11 reserved 10:0 vid_y_start (video y start position). represents the vertical start position of the video window. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 1. offset 10h-13h video upscale regi ster (r/w) reset value: 00000000h provides horizontal and vertical upscale factors of the window. 31:30 reserved. 29:16 vid_y_scl (video y scale factor). represents the vertical upscale factor of the video window according to the following formula: vid_y_scl = 8192 * (ys - 1) / (yd - 1) where: ys = video source vertical size in pixels yd = video destination vertical size in pixels note: upscale factor must be used. yd is equal or bigger than ys . if no scaling is intended, set to 2000h. the actual scale factor used is vid_y_scl/8192, but the formula above fits a given source number of li nes into a destination win- dow size. note: when progressive mixing/blending is programmed (f4bar 0+memory offset 4ch[9] = 0) and the video data is interlaced, this register should be progra mmed to 1000h to double the vertical lines, 15:14 reserved. 13:0 vid_x_scl (video x scale factor). represents horizontal upscale factor of the video window according to the following formula: vid_x_scl = 8192 * (xs - 1) / (xd - 1) where: xs = video source horizontal size in pixels xd = video destination vertical size in pixels note: upscale factor must be used. xd is equal or bigger than xs . if no scaling is intended, set to 2000h. the actual scale factor used is vid_x_scl/8192, but the formula above fits a given source number of pixels into a destination win- dow size. table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
amd geode? sc3200 processor data book 353 video processor module - video processor registers - function 4 revision 5.1 offset 14h-17h video color key re gister (r/w) reset value: 00000000h provides the video color key. the color key can be used to al low irregular shaped overlays of graphics onto video, or video ont o graph- ics, within a scaled video window. 31:24 reserved. 23:0 vid_clr_key (video color key). the video color key is a 24-bit rgb or yuv value. if the color_chroma_sel bit (f4bar0+memory offset 04h[20]) = 0: ? the video pixel is selected within the target window if the corresponding graphics pixel matches the color key. the color key in an rgb value. if the color_chroma_sel bit (f4bar0+memory offset 04h[20]) = 1: ? the video pixel is selected within the target window only if it (the video pixel) does not match the color key. the color key is usually an rgb value. however, if both the csc_ for video and gv_sel bits (f4bar0+memory offset 4ch bits 10 and 13, respectively) are programmed to 0, the color key is a yuv value (i.e., video is not converted to rgb). the graphics or video data being compared can be masked prio r to the compare via the video color mask register (described in f4bar0+memory offset 18h). offset 18h-1bh video color mask register (r/w) reset value: 00000000h provides the video color mask. this value is used to mask bits of the graphics or vi deo stream being compared to the video colo r key (described in f4bar0+memory offset 14h). it can be used to allow a range of values to serve as the color key. 31:24 reserved. 23:0 vid_clr_mask (video color mask). this mask is a 24-bit value. zeros in the mask cause the corresponding bits in the graphics or video stream to be ignored. offset 1ch-1fh palette (gamma correction ra m) address register (r/w) reset value: xxxxxxxxh 31:8 reserved. 7:0 pal_addr (palette address). specifies the address to be used for the next access to the palette data register (f4bar0+memory offset 20h[31:8]). each access to the data register automatically increm ents the palette address regis- ter. if non-sequential access is made to the palette, the address register must be loaded between each non-sequential data block. offset 20h-23h palette (gamma correction ram ) data register (r/w) reset value: xxxxxxxxh provides the video palette data. the data c an be read or written to the gamma correcti on ram (palette) via this register. prior to accessing this register, an appropriate address should be loaded to the palette address register (f4bar0+memory offset 1ch[7:0] ). subsequent accesses to the palette data register cause the in ternal address counter to be incremented for the next cycle. 31:8 pal_data (palette data). contains the read or write data for a gamma correction ram (palette). blue[7:0] = bits [31:24] green[7:0] = bits [23:16] red[7:0] = bits [15:8] note: when a read or write to the gamma correction ram occu rs, the previous output value is held for one additional dotclk period. this effect s hould go unnoticed during normal operation. 7:0 reserved. offset 24h-27h reserved table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
354 amd geode? sc3200 processor data book video processor module - video processor registers - function 4 revision 5.1 offset 28h-2bh miscellaneous register (r/w) reset value: 00001400h configuration and control register for miscell aneous characteristics of the video processor. 31:13 reserved. 12 pll2_pwr_en (pll2 power-down enable). 0: power-down. 1: normal. 11:10 reserved. set to 1. 9:1 reserved. 0 gamma_en (gamma correction ram enable). allows video or graphics (selected by f4bar0+memory offset 04h[21]) to go to the gamma correction ram. 0: enable. 1: disable. offset 2ch-2fh pll2 clock select register (r/w) reset value: 00000000h determines the characteristics of the integrated pll2. 31:23 reserved. must be set to 0. 22:21 clk_div_sel (clock divider select). 00: no division 01: divide by 2 10: divide by 4 11: divide by 8 divides the clock generated by the pll2, using the programmed m (bits [14:8]) and n (bits [3:0]) values. 20 sel_reg_cal. selects specific or previously-calculated values. 0: values previously calculated fr om the clk_sel bits (bits [19:16]). 1: values according to the m (bits [14:8]), n (b its [3:0]), and clk_div_sel (bits [22:21]) fields. 19:16 clk_sel (clock select). selects frequency (in mhz) of the display clock. 0000: 25.175 0100: 50 1000: 65 1100: 108 0001: 31.5 0101: 49.5 1001: 75 1101: 135 0010: 36 0110: 56.25 1010: 78.5 1110: 27 0011: 40 0111: 44.9 1011: 94.5 1111: 24.923052 15 lftc (loop filter time constant). this bit should be set when m (bits [14:8]) value is higher than 30. 14:8 m (defines m pll2 value). relevant when sel_reg_cal (bit 20) = 1. the following formula is used for calculating the frequency using m and n values: fvco = oscclk * km/kn km = m + 1 kn = n + 1 oscclk = 27 mhz 7:4 reserved 3:0 n (defines n pll2 value). relevant when sel_reg_cal (bit 20) = 1. the fo llowing formula is used for calculating the fre- quency using m and n values: fvco = oscclk * km/kn km = m + 1 kn = n + 1 osccl = 27 mhz offset 30h-33h reserved reset value: 00000000h offset 34h-37h reserved reset value: 00000000h offset 38h-3bh reserved reset value: 00000000h table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
amd geode? sc3200 processor data book 355 video processor module - video processor registers - function 4 revision 5.1 offset 3ch-3fh video downscaler cont rol register (r/w) reset value: 00000000h controls the characteristics of the integrated video downscaler. 31:7 reserved 6 dts (downscale type select). 0: type a (downscale formula is 1/m+1, m pixels are dropped, 1 pixel is kept). 1: type b (downscale formula is m/m+1, m pixels are kept, 1 pixel is dropped). 5 reserved. 4:1 dfs (downscale factor select). determines the downscale factor to be prog rammed into these bits, where m is used to derive the desired downscale factor depending on bit 6 (dts). 0 dcf (downscaler and filtering). enables/disables downscaler and filtering logic. 0: disable. 1: enable. note: no downscaling support for rgb 5:6:5 and yuv 4:2:0 video formats. offset 40h-43h video downscaler coeffi cient register (r/w) reset value: 00000000h indicates filter coefficients. the filters can be programmed independently to increase video quality when the downscaler is imp lemented. valid values for each filter coef ficient are 0-15. the sum of coef ficients must be 16. flt_co_4 is used with the earliest pixel s and flt_co_1 is used with the latest. only lu minance values of pixels are filtered. 31:28 reserved 27:24 flt_co_4 (filter coefficient 4). for the tap-4 filter. 23:20 reserved 19:16 flt_co_3 (filter coefficient 3). for the tap-3 filter. 15:12 reserved 11:8 flt_co_2 (filter coefficient 2). for the tap-2 filter. 7:4 reserved 3:0 flt_co_1 (filter coefficient 1). for the tap-1 filter. offset 44h-47h crc signature register (r/w) reset value: xxxxx100h signature values stored in this regi ster can be read by the host. this register is used for test purposes. 31:8 sig_value (signature value). (read only) a 24-bit signature value is stored in th is bit field and can be read at any time. the signature is produced from the rgb data output of the mixer. this bit field is used for test purpose only. see sign_en (bit 0) description for more information. 7:3 reserved 2 sign_free (signature free run). 0: disable. (default) if this bit was previously set to 1, t he signature process stops at the end of the current frame (i.e., at the next falling edge of vsync). 1: enable. if sign_en (bit 0) = 1, the signature regist er captures data continuously across multiple frames. 1 reserved. 0 sign_en (signature enable). 0: disable. (default) the sig_value (bits [31:8]) is reset to 000001h and held (no capture). 1: enable. the next falling edge of vsync is counted as the star t of the frame to be used for crc checking with each pixel clock beginning with the next vsync. if sign_free (bit 2) = 1, the signature register captures the pixel data signature continuously across multiple frames. if sign_free (bit 2) = 0, a signature is captured for one fr ame at a time, starting from the next falling vsync. after a signature capture, the sig_value can be read to det ermine the crc check status. sign_en can then be reset to initialize the sig_value as an essential preparation for the next round of crc check. offset 48h-4bh device and revision identification (ro) reset value: 0000xxxxh 31:16 reserved. 15:8 rev_id (revision id). see the amd geode? sc3200 specification update document for value. 7:0 dev_id (device id). see the amd geode? sc3200 specification update document for value. table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
356 amd geode? sc3200 processor data book video processor module - video processor registers - function 4 revision 5.1 offset 4ch-4fh video de-interlacing and al pha control register (r/w) reset value: 00060000h 31:22 reserved. 21:20 alpha3_win_priority (alpha window 3 priority). determines the priority of alph a window 3. a higher number indi- cates a higher priority. priority is used to det ermine display order for overlapping alpha windows. 00: lowest priority (default). 01: medium priority. 10: highest priority. 11: illegal. note: priority of enabled alpha wi ndows must be different. 19:18 alpha2_win_priority (alpha window 2 priority). determines the priority of alph a window 2. a higher number indi- cates a higher priority. priority is used to det ermine display order for overlapping alpha windows. 00: lowest priority (default). 01: medium priority. 10: highest priority. 11: illegal. note: priority of enabled alpha wi ndows must be different. 17:16 alpha1_win_priority (alpha window 1 priority). determines the priority of alph a window 1. a higher number indi- cates a higher priority. priority is used to det ermine display order for overlapping alpha windows. 00: lowest priority (default). 01: medium priority. 10: highest priority. 11: illegal. note: priority of enabled alpha wi ndows must be different. 15:14 reserved 13 gv_sel (gv select). selects input video format. 0: yuv format. 1: rgb format. note: mixing and blending configurations are created using bits [13, 11:9] of this register. see table 7-1 "valid mixing/ blending configurations" on page 339. if this bit is set to 1, en_42x (f4bar0+memory offset 00h[28]) must be programmed to 0. 12 vid_lin_inv (video line invert). when this bit is set, it allows the video window to be positioned at odd offsets with respect to the first line. the values below are recommended if vid_y_start (f4bar0+memory offset 0ch[10:0]) is an odd (set to 1) or even (set to 0) number of lines from the start of the active display. 0: even. 1: odd. 11 reserved: set to 0. 10 csc_for_video (color space converter for video). determines whether or not the video stream from the video mod- ule is passed through the csc. 0: disable. the video stream is sent "as is" to the video mixer/blender. 1: enable. the video stream is passed thr ough the csc (for yuv to rgb conversion). note: mixing and blending configurations are created using bits [ 13,11:9] of this register. see table 7-1 "valid mixing/ blending configurations" on page 339. 9 video_blend_mode (video blending mode). allows selection of the type of video (i.e., interlaced or progressive) used for blending. 0: progressive video used for blending. 1: interlaced video used for blending. note: mixing and blending configurations are created using bits [ 13,11:9] of this register. see table 7-1 "valid mixing/ blending configurations" on page 339. table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
amd geode? sc3200 processor data book 357 video processor module - video processor registers - function 4 revision 5.1 8 gfx_ins_video (graphics inside video). this bit works in conjunction with bit color_chroma_sel (f4bar0+mem- ory offset 4ch[20]). color_chroma_sel selects whether the gr aphics is used for color ke ying or the video data stream is used for chroma keying. if color_chroma_sel = 0, graphics data is compared to the color key. if color_chroma_sel = 1, video data is compared to the chroma key. 0: outside the alpha windows, graphics or video is displayed depending on the result of the color key comparison. 1: outside the alpha windows, only video is displayed (if color_chroma_sel = 0) or only graphics is displayed (if color_chroma_sel = 1) color key comparison is not performed outside the alpha windows. 7 vid_win_push_en (video window push enable). video window repositioning at an offset of 1 line below the pro- grammed value. facilitates line ra te matching in both fields. 0: disable. (default) 1: enable. 6 top_line_in_odd (top line in odd field). allows selection of what field the top line is in. 0: top line is in even field. (default) 1: top line is in odd field. 5 reserved. 4 insert_en (insert enable). when this bit is set, the odd frame is shifted with respect to the even frame. 0: no shifting occurs. 1: the odd frame is shifted according to the offset specified in bits [2:0]. 3 reserved. 2:0 offset (vertical scaler offset). for a non-interlaced video stream and when bob de-interlacing is used, program a value of 100 (i.e., shift one line); otherwise, leave at 000. offset 50h-53h cursor color key register (r/w) reset value: 00000000h 31:29 reserved. 28:24 color_reg_offset (cursor color register offset). this field indicates a bit in the incoming graphics stream. it is used to indicate which of the two possible cursor color regi sters should be used for color key matches for the bits in the graphics stream. 23:0 cur_color_key (cursor color key). specifies the 24-bit rgb value of the cu rsor color key. the incoming graphics stream is compared with this value. if a match is detected, the pixel is replaced by a 24-bi t value from one of the cursor color registers. offset 54h-57h cursor color mask register (r/w) reset value: 00000000h 31:24 reserved 23:0 cur_color_mask (cursor color mask). this mask is a 24-bit value. zeroes in the mask cause the corresponding bits in the incoming graphics stream to be ignored. offset 58h-5bh cursor color re gister 1 (r/w) reset value: 00000000h 31:24 reserved 23:0 cur_color_reg1 (cursor color register 1). specifies a 24-bit cursor color va lue. this is an rgb value (for rgb blending) or a yuv value (for yuv blending). in inte rlaced yuv blending mode, y/2 value should be used. this is one of two possible cursor color values. the co lor_reg_offset bits (f4bar0+memory offset 50h[28:24]) determine a bit of the graphics data that if even, selects this color to be used. offset 5ch-5fh cursor color re gister 2 (r/w) reset value: 00000000h 31:24 reserved 23:0 cur_color_reg2 (cursor color register 2). specifies a 24-bit cursor color va lue. this is an rgb value (for rgb blending) or a yuv value (for yuv blending). in inte rlaced yuv blending mode, y/2 value should be used. this is one of two possible cursor color values. the co lor_reg_offset bits (f4bar0+memory offset 50h[28:24]) determine a bit of the graphics data that if even, selects this color to be used. table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
358 amd geode? sc3200 processor data book video processor module - video processor registers - function 4 revision 5.1 offset 60h-63h alpha window 1 x posi tion register (r/w) reset value: 00000000h note: h_total and h_sync_end are values programmed in the gx1 module?s display cont roller timing registers (gx_base+memory offset 8330h[26:19] and 8338h[10:3], respectively). the value of (h_total ? h_sync_end) is some- times referred to as ?horizontal back porch?. for more information, see the amd geode? gx1 processor data book . desired screen position should not be outside a vi deo window (f4bar0+memory offset 08h and 0ch). 31:27 reserved. 26:16 alpha1_x_end (alpha window 1 horizontal end). determines the horizontal end positi on of alpha window 1 (not inclu- sive). this value is calculated ac cording to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 1. 15:11 reserved. 10:0 alpha1_x_start (alpha window 1 horizontal start). determines the horizontal start position of alpha window 1. this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 2. offset 64h-67h alpha window 1 y posi tion register (r/w) reset value: 00000000h note: v_total and v_sync_end are values programmed in the gx1 module?s display controller timing registers (gx_base+memory offset 8340h[26:16] and 8348h[26:16], respectively). the value of (v_total ? v_sync_end) is some- times referred to as ?vertical back porch?. for more information, see the amd geode? gx1 processor data book . desired screen position should not be outside a vi deo window (f4bar0+memory offset 08h and 0ch). 31:27 reserved. 26:16 alpha1_y_end (alpha window 1 vertical end). determines the vertical end position of alpha window 1 (not inclusive). this value is calculated accord ing to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. 15:11 reserved. 10:0 alpha1_y_start (alpha window 1 vertical start). determines the vertical start posit ion of alpha window 1. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 1. offset 68h-6bh alpha window 1 color register (r/w) reset value: 00000000h 31:25 reserved. 24 alpha1_color_reg_en (alpha window 1 color register enable). enable bit for the color key matching in alpha window 1. 1: enable. if this bit is enabled and the alpha window is enabled, then where there is a color key match. the color value (in bits [23:0], alpha1_color_reg) is displayed. 0: disable. where there is a color key match, no blending is performed. 23:0 alpha1_color_reg (alpha window 1 color register). specifies the color to be displayed inside alpha window 1 when there is a color key match in the alpha window. this is an rgb value (for rgb blending) or a yuv value (for yuv blending). in interlaced yuv blending mode, y/2 value should be used. this color is only displayed if the alpha window is enabled and bit 24 (alpha 1_color_reg_en) is enabled. offset 6ch-6fh alpha window 1 cont rol register (r/w) reset value: 00000000h 31:18 reserved. 17 load_alpha (load alpha value). (write only) when set to 1, this bit causes t he video processor to load the alpha value (in bits [7:0], alpha_val) at the start of the next frame. 16 alpha1_win_en (alpha window 1 enable). enable bit for alpha window 1. 1: enable alpha window 1. 0: disable alpha window 1. note: valid only if video window is enabled (f4bar0+memory offset 00h[0] = 1). 15:8 alpha1_inc (alpha window 1 increment). specifies the alpha value increment/dec rement. this is a signed 8-bit value that is added to the alpha value for each frame. the msb (bit 15) indicates the sign (i.e., increment or decrement). when this value reaches either the maximum or the minimum alpha value (255 or 0) it keeps that value (i.e., it is not incremented/ decremented) until it is rel oaded via bit 17 (load_alpha). 7:0 alpha1_val (alpha window 1 value). specifies the alpha value to be used for this window. table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
amd geode? sc3200 processor data book 359 video processor module - video processor registers - function 4 revision 5.1 offset 70h-73h alpha window 2 x posi tion register (r/w) reset value: 00000000h note: h_total and h_sync_end are values programmed in the gx1 module?s display cont roller timing registers (gx_base+memory offset 8330h[26:19] and 8338h[10:3], respectively). the value of (h_total ? h_sync_end) is some- times referred to as ?horizontal back porch?. for more information, see the amd geode? gx1 processor data book . desired screen position should not be outside a vi deo window (f4bar0+memory offset 08h and 0ch). 31:27 reserved. 26:16 alpha2_x_end (alpha window 2 horizontal end). determines the horizontal end posi tion of alpha window 2 (not inclu- sive). this value is calculated ac cording to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 1. 15:11 reserved 10:0 alpha2_x_start (alpha window 2 horizontal start). determines the horizontal start position of alpha window 2. this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 2. offset 74h-77h alpha window 2 y posi tion register (r/w) reset value: 00000000h note: v_total and v_sync_end are values programmed in the gx1 module?s display controller timing registers (gx_base+memory offset 8340h[26:16] and 8348h[26:16], respectively). the value of (v_total ? v_sync_end) is some- times referred to as ?vertical back porch?. for more information, see the amd geode? gx1 processor data book . desired screen position should not be outside a vi deo window (f4bar0+memory offset 08h and 0ch). 31:27 reserved. 26:16 alpha2_y_end (alpha window 2 vertical end). determines the vertical end position of alpha window 2 (not inclusive). this value is calculated accord ing to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. 15:11 reserved. 10:0 alpha2_y_start (alpha window 2 vertical start). determines the vertical start posit ion of alpha window 2. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 1. offset 78h-7bh alpha window 2 color register (r/w) reset value: 00000000h 31:25 reserved. 24 alpha2_color_reg_en (alpha window 2 color register enable). enable bit for the color key matching in alpha window 2. 0: disable. where there is a color key match, graphics and video are alpha-blended. 1: enable. if this bit is enabled and the alpha window is enabled, then where there is a color key match, the color value (in bits [23:0], alpha2_color_reg) is displayed. 23:0 alpha2_color_reg (alpha window 1 color register). specifies the color to be displayed inside alpha window 2 when there is a color key match in the alpha window. this is an rgb value (for rgb blending) or a yuv value (for yuv blending). in interlaced yuv blending mode, y/2 value should be used. this color is only displayed if the alpha window is enabled and bit 24 (alpha 2_color_reg_en) is enabled. offset 7ch-7fh alpha window 2 cont rol register (r/w) reset value: 00000000h 31:18 reserved. 17 load_alpha (load alpha value). (write only) when set to 1, this bit causes t he video processor to load the alpha value (in bits [7:0], alpha2_val) at the start of the next frame. 16 alpha2_win_en (alpha window 2 enable). enable bit for alpha window 2. 0: disable alpha window 2. 1: enable alpha window 2. note: valid only if video window is enabled (f4bar0+memory offset 00h[0] = 1). 15:8 alpha2_incr (alpha window 2 increment). specifies the alpha value increment/decrement. this is a signed 8-bit value that is added to the alpha value fo r each frame. the msb (bit 15) indicates the sign (i.e., incre- ment or decrement). when this value reac hes either the maximum or the minimum al pha value (255 or 0) it keeps that value (i.e., it is not incremented/decremented) un til it is reloaded via bit 17 (load_alpha). 7:0 alpha2_val (alpha window 1 value). specifies the alpha value to be used for this window. table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
360 amd geode? sc3200 processor data book video processor module - video processor registers - function 4 revision 5.1 offset 80h-83h alpha window 3 x posi tion register (r/w) reset value: 00000000h note: h_total and h_sync_end are values programmed in the gx1 module?s display cont roller timing registers (gx_base+memory offset 8330h[26:19] and 8338h[10:3], respectively). the value of (h_total ? h_sync_end) is some- times referred to as ?horizontal back porch?. for more information, see the amd geode? gx1 processor data book . note: desired screen position should not be outside a vi deo window (f4bar0+memory offset 08h and 0ch). 31:27 reserved. 26:16 alpha3_x_end (alpha window 3 horizontal end). determines the horizontal end posi tion of alpha window 3 (not inclu- sive). this value is calculated ac cording to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 1. 15:11 reserved. 10:0 alpha3_x_start (alpha window 3 horizontal start). determines the horizontal start position of alpha window 3. this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 2. offset 84h-87h alpha window 3 y posi tion register (r/w) reset value: 00000000h note: v_total and v_sync_end are values programmed in the gx1 module?s display controller timing registers (gx_base+memory offset 8340h[26:16] and 8348h[26:16], respectively). the value of (v_total ? v_sync_end) is some- times referred to as ?vertical back porch?. for more information, see the amd geode? gx1 processor data book . desired screen position should not be outside a vi deo window (f4bar0+memory offset 08h and 0ch). 31:27 reserved 26:16 alpha3_y_end (alpha window 3 vertical end). determines the vertical end position of alpha window 3 (not inclusive). this value is calculated accord ing to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. 15:11 reserved 10:0 alpha3_y_start (alpha window 3 vertical end). determines the vertical start posit ion of alpha window 3. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 1. offset 88h-8bh alpha window 3 colo r register (r/w) reset value: 00000000h 31:25 reserved. 24 alpha3_color_reg_en (alpha window 3 color register enable). enable bit for the color key matching in alpha window 3. 0: disable. where there is a color key match, graphics and video are alpha-blended. 1: enable. if this bit is enabled and the alpha window is enabled, then where there is a color key match, the color value (in bits [23:0], alpha3_color_reg) is displayed. 23:0 alpha3_color_reg (alpha window 3 color register). specifies the color to be displayed inside alpha window 3 when there is a color key match in the alpha window. this is an rgb value (for rgb blending) or a yuv value (for yuv blending). in interlaced yuv blending mode, y/2 value should be used. this color is only displayed if the alpha window is enabled and the bit 24 (alpha 3_color_reg_en) is enabled. offset 8ch-8fh alpha window 3 cont rol register (r/w) reset value: 00000000h 31:18 reserved 17 load_alpha (load alpha value). (write only) when set to 1, this bit causes t he video processor to load the alpha value (in bits [7:0], alpha3_val) at the start of the next frame. 16 alpha3_win_en (alpha window 3 enable). enable bit for alpha window 3. 0: disable alpha window 3. 1: enable alpha window 3. valid only if video window is enabled (f4bar0+memory offset 00h[0] = 1) 15:8 alpha3_incr (alpha window 3 increment). specifies the alpha value increment/dec rement. this is a signed 8-bit value that is added to the alpha value for each frame. the msb (bit 15) indicates the sign (i.e., increment or decrement). when this value reaches either the maximum or the minimum alpha value (255 or 0) it keeps that value (i.e., it is not incremented/ decremented) until it is rel oaded via bit 17 (load_alpha). 7:0 alpha3_val (alpha window 3 value). specifies the alpha value to be used for this window. table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
amd geode? sc3200 processor data book 361 video processor module - video processor registers - function 4 revision 5.1 offset 90h-93h video request register (r/w) reset value: 001b0017h 31:28 reserved. set to 0. 27:16 video_x_req (video horizontal request). determines the horizontal (pixel) lo cation at which to start requesting video data out of the video fifo. this value is ca lculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 2. 15:11 reserved 10:0 video_y_req (video vertical request). determines the line number at which to start requesting video data out of the video fifo. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 1. offset 94h-97h alpha watch register (ro) reset value: 00000000h alpha values may be automatically increment ed/decremented for successive frames. this register can be us ed to read the alpha va lues that are being used in the current frame. 31:24 reserved. 23:16 alpha3_val (value for alpha window 3). 15:8 alpha2_val (value for alpha window 2). 7:0 alpha1_val (value for alpha window 1). offset 98h-3ffh reserved offset 400h-403h video processor display mode register (r/w) reset value: 00000000h selects various video processor modes. 31 video fifo underflow (empty). 0: no underflow has occurred. 1: underflow has occurred. write 1 to reset this bit. 30 video fifo overflow (full). 0: no overflow has occurred. 1: overflow has occurred. write 1 to reset this bit. 29 reserved. write as read. 28 reserved. write as read. 27:4 reserved . set to 0. 3 reserved. write as read. 2 note: reserved. write as read. 1:0 vid_sel (video select). selects the source of the video data. 00: gx1 module. 10: vip block. 01: reserved. 11: reserved. the gx1 module?s video clock must be active at all times, regardless of the source of video input. offset 404h-407h reserved reset value: 00000000h offset 408h-40bh video processor test mode register (r/w) reset value: 00000000h 31:0 reserved. offset 40ch-41fh reserved table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
362 amd geode? sc3200 processor data book video processor module - video processor registers - function 4 revision 5.1 offset 420h-423h genlock regi ster (r/w) reset value: 00000000h 31:24 reserved. must be set to 0. 23 odd_to (odd field time out). indicates cgento0 (f4bar0+memory offset 43ch[15:0]) has expired. this bit can be reset by writing 1 to it. 22 even_to (even field time out). indicates cgento1 (f4bar0+memory offset 43ch[31:16]) has expired. this bit can be reset by writing 1 to it. 21:9 reserved. 8 reserved. set to 0. 7 reserved. set to 0. 6 reserved. set to 0. 5 reserved. set to 0. 4 genlock_tout_en (genlock timeout enable). 0: disable. 1: enable timeout. 3 vip_vsync_edge_sel (vip vsync edge select). selects which edge of the vsync signal should be synchronized with vip. 0: rising edge. 1: falling edge. 2 gx1_vsync_edge_sel (gx1 vsync edge select). selects which edge of the vsyn c signal should be synchronized with the gx1 module. 0: rising edge. 1: falling edge. 1 ct_genlock_en (enable continuous genlock function). 0: the continuous genlock function is disabled. 1: enable locking (i.e., synchronization) of the gx1 vsync with the vip vsync on every vsync (i.e., continuous lock- ing). note: if bit 0 (sg_genlock_en) = 1, it overrides the value of this bit. 0 reserved. set to 0. offset 424h-427h genlock delay re gister (r/w) reset value: 00000000h 31:21 reserved. 20:0 genlock_del (genlock delay). indicates the delay (in 27 mhz clocks) between the vip vsync and the gx1 module?s display controller vsync. offset 428h-43bh reserved offset 43ch-43fh continuous genlock timeou t register (r/w) reset value: 1fff1fffh 31:16 cgento1 (even field continuous genlock timeout). 15:0 cgento0 (odd field continuous genlock timeout). table 7-7. f4bar0+memory offset: video proc essor configuration registers (continued) bit description
amd geode? sc3200 processor data book 363 video processor module - video processor registers - function 4 revision 5.1 7.3.2.2 vip support registers - f4bar2 f4 index 18h, base address register 2 (f4bar2) points to the base address of where the vip configuration registers are located. table 7-8 shows the memory mapped vip support registers accessed through f4bar2. table 7-8. f4bar2+memory offset: vip configuration registers bit description offset 00h-03h video interface port config uration register (r /w) reset value: 00000000h 31:23 reserved. must be set to 0. 22 vip fifo bus request threshold. vip fifo issues a bus request when it is filled with 32 or 64 bytes. 0: 64 bytes. 1: 32 bytes 21 vbi task b store to memory. when this bit is enabled, raw vbi task b data is stored to memory. 0: disable. 1: enable. this bit is relevant only if bit 18 (vbi configuration override) = 1 (enabled). 20 vbi task a store to memory. when this bit is enabled, raw vbi task a data is stored to memory. 0: disable. 1: enable. this bit is relevant only if bit 18 (vbi configuration override) = 1 (enabled). 19 vbi ancillary store to memory. when this bit is enabled, raw vbi an cillary data is stored to memory. 0: disable. 1: enable. this bit is relevant only if bit 18 (vbi configuration override) = 1 (enabled). 18 vbi configuration override. when this bit is enabled, bits [21:19] ov erride the setup specified in bits 17 and 16. 0: disable. 1: enable. 17 vbi data task. specifies the ccir656 video stream task used to store raw vbi data to memory. 0: task b. 1: task a. this bit is relevant only if bit 16 (vbi mode for ccir656) = 1 and bit 18 (vbi configuration override) = 0 (disabled). 16 vbi mode for ccir656. specifies the mode in which to store vbi data to memory. 0: use ccir656 ancillary data to store vbi data to memory. 1: use ccir656 video task a or b to store vbi data to memory, depending on the value of bit 17 (vbi data task). this bit is only used if bit 18 (vbi configuration override) = 0 (disabled). 15:2 reserved. set to 0. 1:0 video input port mode. selects vip operating mode. 10: ccir656 mode. all other decodes: reserved. offset 04h-07h video interface cont rol register (r/w) reset value: 00000000h 31:18 reserved. must be set to 0. 17 line interrupt. when asserted, allows interrupt (intc#) generati on when the video current line register (f4bar2+ mem- ory offset 10h) contents equal the video line target r egister (f4bar2+ memory offset 14h) contents. 0: disable. 1: enable. 16 field interrupt. when asserted, allows interrupt (intc#) generation at the end of a field (i.e., the end of active video for the current field). interrupt generation can be enabled regardless of whether or not video capture (store to memory) is enabled. 0: disable. 1: enable. 15:11 reserved. must be set to 0.
364 amd geode? sc3200 processor data book video processor module - video processor registers - function 4 revision 5.1 10 auto-flip. video port operation mode. 0: the video port automatically detects the even and odd fi elds based on the vp_href and vp_vsync_in signals or the ccir656 control codes. 1: the even/odd field detect logic is disabled and the video port automatically toggles between the even and odd buffers during capture. the odd buffer is the first to be filled in this mode. this bit must be programmed to 0 when direct video mode is used. direct video mode is used when vid_sel = 10 (f4bar0+memory offset 400h[1:0]). otherwise the video select from the gx1 module. vid_sel indicates the source of the video data.) 9 capture (store to memory) vbi data. 0: disable. 1: enable. 8 capture (store to memory) video data. 0: disable. 1: enable. 7:2 reserved. must be set to 0. 1:0 run mode capture. selects capture run mode. 00: stop capture at end of current line. 01: stop capture at end of current field. 10 reserved. 11: start capture at beginning of next field. offset 08h-0bh video interface status register (r/w) reset value: xxxxxxxxh 31:25 reserved. (read only) 24 current field. (read only) 0: even field is being processed. 1: odd field is being processed. 23:22 reserved. (read only) 21 base register not updated. (read only) when set to 1, this bit indicates that one of the base registers (at f4bar2+memory offset 20h, 24h, 40h, and 44h) has been written but has not yet been updated. 0: all base registers are updated. 1: one or more of the base registers has not been updated. 20 fifo overflow status indication. 0: no overflow occurred. 1: an overflow occurred for the fifo between the vip and the fast x-bus. writing a 1 to this bit clears the status. 19:18 reserved. (read only) 17 line interrupt (intc#) pending status. 0: interrupt not pending. 1: interrupt pending. writing a 1 to this bit clears the status. 16 field interrupt (intc) pending status. 0: interrupt not pending. 1: interrupt pending. writing a 1 to this bit clears the status. 15:10 reserved. (read only) 9 vbi data capture active. (read only) 0: vbi data is not being stored to memory. 1: vbi data is now being stored to memory. table 7-8. f4bar2+memory offset: vip configuration registers (continued) bit description
amd geode? sc3200 processor data book 365 video processor module - video processor registers - function 4 revision 5.1 8 video data capture active. (read only) 0: video data is not being stored to memory. 1: video data is now being stored to memory. 7:1 reserved. (read only) 0 run status. (read only) 0: video port capture is not active. 1: video port capture is in progress. offset 0ch-0fh reserved reset value: 00h offset 10h-13h video current line register (ro) reset value: xxxxxxxxh 31:10 reserved. 9:0 current line. indicates the video line currently being stored to memory. t he count indicated in this field is reset to 0 at the start of each field. offset 14h-17h video line target register (r/w) reset value: 00000000h 31:10 reserved. must be set to 0. 9:0 line target. indicates the video line to generate an interrupt on. offset 18h-1bh reserved reset value: 00000000h offset 1ch-1fh reserved reset value: 00000000h offset 20h-23h video data odd b ase register (r/w) reset value: 00000000h this register specifies the base address in graphics memory where odd video field data are stored. changes to this register tak e effect at the beginning of the next field. the va lue in this register is 16-byte aligned. note: this register is double-buffered. when a new value is written to this register, the new value is placed in a special "pending" reg- ister, and the "base register not updated" bit (f4bar2+memoryo ffset 08h[21]) is set to 1. the video data odd base register (this register) is not updated at this point. when the first data of the next field is stored to memory, the pending values of all base registers (including this one) are written to the appropria te base registers, and the "bas e register not updated" bit is cleared. 31:0 video odd base address. base address where odd video data are stored in gr aphics memory. bits [3:0] are always 0, and define the required address space. offset 24h-27h video data even b ase register (r/w) reset value: 00000000h this register specifies the base address in graphics memory where even video field dat a are stored. changes to this register ta ke effect at the beginning of the next field. the va lue in this register is 16-byte aligned. note: this register is double-buffered. when a new value is written to this register, the new value is placed in a special "pending" reg- ister, and the "base register not updated" bit (f4bar2+memoryo ffset 08h[21]) is set to 1. the video data even base regis- ter (this register) is not updated at this point. when the first data of the next field is stored to memory, the pending values of all base registers (including this one) are written to the appropria te base registers, and the "bas e register not updated" bit is cleared. 31:0 video even base address. base address where even video data are stored in graphics memory. bits [3:0] are always 0, and define the requi red address space. offset 28h-2bh video data pitch register (r/w) reset value: 00000000h this register specifies the logical widt h of the video data buffer. this value is added to the start of the line address to get the address of the next line where video data are stored to memory. this value must be an integral number of dwords. 31:16 reserved. 15:0 video data pitch. specifies the logical width of the video data buffer. bits [1:0] are always 0. offset 2ch-3fh reserved reset value: 00000000h table 7-8. f4bar2+memory offset: vip configuration registers (continued) bit description
366 amd geode? sc3200 processor data book video processor module - video processor registers - function 4 revision 5.1 offset 40h-43h vbi data odd base register (r/w) reset value: 00000000h this register specifies the base address in graphics memory where vbi data for odd fiel ds are stored. changes to this register take effect at the beginning of the next field. t he value in this register is 16-byte aligned. note: this register is double-buffered. when a new value is written this register, the new value is placed in a special "pending" reg is- ter, and the "base register not updated" bit (f4bar2+memoryoffs et 08h[21]) is set to 1. the vbi data odd base register (this register) is not updated at this point. when the first data of the next field is stored to memory, the pending values of all base registers (including this one) are written to the appropria te base registers, and the "bas e register not updated" bit is cleared. 31:0 vbi odd base address. base address where vbi data for odd fields is stor ed in graphics memory. bits [3:0] are always 0 and define the requi red address space. offset 44h-47h vbi data even b ase register (r/w) reset value: 00000000h this register specifies the base address in graphics memory where vbi data for even fields is stor ed. changes to this register take effect at the beginning of the next field. the va lue in this register is 16-byte aligned. note: this register is double-buffered. when a new value is written to this register, the new value is placed in a special "pending" reg- ister, and the "base register not updated" bit (f4bar2+memoryo ffset 08h[21]) is set to 1. the vbi data even base register (this register) is not updated at this point. when the first data of the next field is stored to memory, the pending values of all base registers (including this one) are written to the appropria te base registers, and the "bas e register not updated" bit is cleared. 31:0 vbi even base address. base address where vbi data for even fields is st ored in graphics memory. bits [3:0] are always 0 and define the requi red address space. offset 48h-4bh vbi data pitch register (r/w) reset value: 00000000h this register specifies the logical width of the vbi data buff er. this value is added to the start of the line address to get t he address of the next line where vbi data are stored to memory. this value must be an integral number of dwords. 31:16 reserved. 15:0 vbi data pitch. specifies the logical width of the video data buffer. bits [1:0] are always 0. offset 4ch-1ffh reserved reset value: 00h table 7-8. f4bar2+memory offset: vip configuration registers (continued) bit description
amd geode? sc3200 processor data book 367 8 debugging and monitoring revision 5.1 8.0 debugging and monitoring 8.1 testability (jtag) the test access port (tap) allows board level interconnec- tion verification and chip production tests. an ieee- 1149.1a compliant test interface, tap supports all ieee mandatory instructions as well as several optional instruc- tions for added functionality. see table 8-1 for a summary of all instructions support. for further information on jtag, refer to ieee standard 1149.1a-1993 test access port and boundary-scan architecture. 8.1.1 mandatory instruction support the tap supports all ieee mandatory instructions, includ- ing: bypass. presents the shortest path through a given chip (a 1-bit shift register). extest drives data loaded into the jtag path (possibly with a sample/preload instruction) to output pins. sample/preload captures chip inputs and outputs. 8.1.2 optional instruction support the tap supports the following ieee optional instructions: idcode presents the contents of the device identification register in serial format. clamp ensures that the bypass regi ster is connected between tdi and tdo, and then drives data that was loaded into the boundary scan register (e.g., via sample- preload instruction) to output signals. these signals do not change while the clamp instruction is selected. hiz puts all chip outputs in inactive (floating) state (including all pins that do not require a tri-state output for normal functionality). note that not all pull-up resistors are disabled in this state. 8.1.3 jtag chain balls that are not part of the jtag chain: usb i/os table 8-1. jtag mode instruction support code instruction activity 000 extest drives shifted data to output pins. 001 sample/preload captures inputs and system outputs. 010 idcode scans out device identifier. 011 hiz puts all output and bidirectional pins in tri-state. 100 clamp drives fixed data from boundary scan register. 101 reserved 110 reserved 111 bypass presents shortest external path through device.
368 amd geode? sc3200 processor data book debugging and monitoring revision 5.1
amd geode? sc3200 processor data book 369 9 electrical specifications revision 5.1 9.0 electrical specifications this chapter provides information about: general electrical specifications dc characteristics ac characteristics all voltage values in this chapter are with respect to v ss unless otherwise noted. 9.1 general specifications 9.1.1 electro static discharge (esd) this device is a high performance integrated circuit and is esd sensitive. handling and assembly of this device should be performed at esd free workstations. table 9-1 lists the esd ratings of the sc3200. 9.1.2 power/ground connections and decoupling when testing and operating the sc3200, use standard high frequency techniques to reduce parasitic effects. for example: filter the dc power leads with low-inductance decou- pling capacitors. use low-impedance wiring. utilizing the pwr and gnd pins. 9.1.3 absolute maximum ratings stresses beyond those indicated in the following table may cause permanent damage to the sc3200, reduce device reliability and result in premature failure, even when there is no immediately apparent sign of failure. prolonged expo- sure to conditions at or near the absolute maximum ratings may also result in reduced device life span and reduced reliability. note: the values in the following table are stress ratings only. they do not imply that operation under other conditions is impossible. table 9-1. electro static discharge (esd) parameter units human body model (hbm) 2000v esd machine model (mm) 200v esd table 9-2. absolute maximum ratings symbol parameter min max unit comments t case operating case temperature -10 110 o c note 1 t storage storage temperature -45 125 o c note 2 v cc supply voltage see table 9-3 v v max voltage on 5v tolerant balls -0.5 6.0 v note 3 others -0.5 3.6 v note 3, note 4 i ik input clamp current -0.5 10 ma note 1 i ok output clamp current 25 ma note 1 note 1. power applied - no clocks. note 2. no bias. note 3. voltage min is -0.8v with a transient voltage of 20 ns or less. note 4. voltage max is 4.0v with a transient voltage of 20 ns or less.
370 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.1.4 operating conditions table 9-3 lists the various power supplies of the sc3200 and provides the device operating conditions. notes: 1) all power sources except v bat must be connected, even if the function is not used. 2) v sb , and v sbl must be on if any other voltage is applied. v sb and v bat voltages can be applied sepa- rately. see section 9.3.15 "power-up sequencing" on page 434. 3) the power planes of the sc3200 can be turned on or off. for more information, see section 6.2.9 "power management logic" on page 174. 4) it is recommended that the voltage difference between v core and v sbl be less than 0.25v, in order to reduce leakage current. if the voltage difference exceeds 0.25v, excessive leakage current is used in gates that are connected on the boundary between voltage domains. 5) it is recommended that the voltage difference between v io and v sb be less than 0.25v, in order to reduce leakage current. if the voltage difference exceeds 0.25v, excessive leakage current is used in gates that are connected on the boundary between voltage domains. table 9-3. operating conditions symbol (note 1) parameter min typ max unit comments t c operating case temperature 0 - 85 o c av ccusb analog power supply. powers internal ana- log circuits and some external signals (see table 9-4). 3.14 3.3 3.46 v v bat battery supply voltage. powers rtc and acpi when v bat is greater than v sb (by at least 0.5v), and some external signals (see table 9-4). 2.4 3.0 3.46 v v io i/o buffer power supply. powers most of the external signals (see table 9-4); certain signals within this power plane are 5v tolerant. 3.14 3.3 3.46 v v core core processor and internal digital power supply. powers internal digital logic, includ- ing internal frequency multipliers. 1.71 1.8 1.89 v v pll2 v pll3 pll. internal phase locked loops (pll) power supply. 3.14 3.3 3.46 v v sb standby power supply. powers rtc and acpi when v sb is greater than v bat -0.5v, and some external signals (see table 9-4). 3.14 3.3 3.46 v v sbl standby logic. powers internal logic needed to support standby v sb . v sbl requires a 0.1 f bypass capacitor to v ss . 1.71 1.8 1.89 v note 1. for v ih (input high voltage), v il (input low voltage), i oh (output high current), and i ol (output low current) op- erating conditions refer to section 9.2 "dc characteristics" on page 375.
amd geode? sc3200 processor data book 371 electrical specifications revision 5.1 table 9-4 indicates which power rails are used for each signal of the sc3200 external interface. power planes not listed in this table are internal, and are not related to signals of the external interface. 9.1.5 dc current dc current is not a simple measurement. three of the sc3200 power states (on, active idle, sleep) were selected for measurement. for each power state mea- sured, two functional characteristics (typical average, absolute maximum) are used to determine how much cur- rent the sc3200 uses. 9.1.5.1 power state parameter definitions the dc characteristics tables in this section list core and i/ o current for three of the power states. for more explana- tion on the sc3200 power states see section 6.2.9 "power management logic" on page 174. on (c0) : all internal and external clocks with respect to the sc3200 are running and all functional blocks inside the gx1 module (cpu core, memory controller, display controller, etc.) are actively generating cycles. this is equivalent to the acpi spec ification?s ?s0,c0? state. active idle (c1) : the cpu core has been halted, all other functional blocks (including the display controller for refreshing the display) are actively generating cycles. this state is entered when a hlt instruction is executed by the cpu core. from a user?s perspective, this state is indistinguishable from the on state and is equivalent to the acpi specification?s ?s0,c1? state. sleep (sl2) : this is the lowest power state the sc3200 can be in with voltage still applied to the device?s core and i/o supply pins. this is equivalent to the acpi spec- ification?s ?s1? state. 9.1.5.2 definition and measurement techniques of sc3200 current parameters these parameters describe the current while the sc3200 is in the on state: typical average : indicates the average current used by the sc3200 while in the on state. this is measured by running typical windows applications in a typical display mode. in this case, 800x600x8 bpp at 75 hz, 50 mhz dclk using a background image of vertical stripes (4- pixel wide) alternating between black and white with power management disabled (to guarantee that the sc3200 never goes into the active idle state). this number is provided for reference only since it can vary greatly depending on the usag e model of the system. note: this typical average should not be confused with the typical power numbers. typical power is based on a combination of on (typical average) and active idle states. absolute maximum : indicates the maximum instanta- neous current used by the sc3200. cpu core current is measured by running the landmark speed 200 bench- mark test (with power management disabled) and measuring the peak current at any given instant during the test. i/o current is measured by running microsoft windows 98? and using a background image of vertical stripes (1-pixel wide) alternating between black and white at the maximum display resolution. table 9-4. power planes of external interface signals power plane signal names v cc balls v ss balls standby gpwio[0:2], led#, o nctl#, pwrbtn#, pwrcnt[1:2], thrm#, clk32, irrx1, ri2#, sdata_in2 v sb v ss battery x32i, x32o v bat v ss usb dpos_port1, dneg_ port1, dpos_port2, dneg_port2, dpos_port3, dneg_port3 av ccusb av ssusb i/o all other external interface signals v io v ss
372 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.1.5.3 definition of sy stem conditions for measuring on parameters the sc3200?s current is highly dependent on two func- tional characteristics, dclk (dot clock) and sdram fre- quency. table 9-5 shows how these factors are controlled when measuring the typical average and absolute maxi- mum processor current parameters. 9.1.5.4 dc current measurements table 9-6 and table 9-7 show the dc current measure- ments of the sc3200. table 9-5. system conditions used to measure sc3200 current during on state cpu current measurement system conditions v core (note 1_ v io (note 1) dclk frequency sdram frequency typical average nominal nominal 50 mhz (note 2) nominal absolute maximum max max 135 mhz (note 3) max note 1. see table 9-3 on page 370 for nominal and maximum voltages. note 2. a dclk frequency of 50 mhz is derived by setting the display mode to 800x600x8 bpp at 75 hz, using a display image of vertical stripes (4-pixel wide) alternati ng between black and white with power management disabled. note 3. a dclk frequency of 135 mhz is derived by setting t he display mode to 1280x1024x8 bpp at 75 hz, using a display image of vertical stripes (1-pixel wide) alternati ng between black and white with power management disabled. table 9-6. dc characteristics for on state symbol parameter (note 1) typ avg abs max unit comments i cc3on f clk = 233 mhz, i/o current @ v io = 3.3v (nominal); cpu state = on 260 300 ma i cc for v io f clk = 266 mhz, i/o current @ v io = 3.3v (nominal); cpu state = on 270 310 i coreon f clk = 233 mhz, core current @ v core = 1.8v (nominal); cpu state = on 820 990 ma i cc for v core f clk = 266 mhz, core current @ v core = 1.8v (nominal); cpu state = on 900 1090 i sbon sb current @ v sb = 3.3v (nominal); cpu state = on 12ma i sblon sbl current @ v sbl = 1.8v (nominal); cpu state = on 10 20 ma sbl current @ v sbl = 2.0v (nominal); cpu state = on 10 20 note 1. f clk ratings refer to in ternal clock frequency.
amd geode? sc3200 processor data book 373 electrical specifications revision 5.1 9.1.6 ball capacitance and inductance table 9-8 gives ball capacitance and inductance values. table 9-7. dc characteristics for active idle, sleep, and off states symbol parameternote 1 min typ max unit comments i cc3idle f clk = 233 mhz, i/o current @ v io = 3.3v (nominal); cpu state = active idle 260 ma i cc for v io f clk = 266 mhz, i/o current @ v io = 3.3v (nominal); cpu state = active idle 270 i cc3slp i/o current @ v io = 3.3v (nominal); cpu state = sleep 20 30 ma i cc for v io , note 2 i coreidle f clk = 233 mhz, core current @ v core = 1.8v (nominal); cpu state = active idle 360 ma i cc for v core f clk = 266 mhz, core current @ v core = 1.8v (nominal); cpu state = active idle 380 i coreslp core current @ v core = 1.8v (nominal); cpu state = sleep 20 30 ma i cc for v core , note 2 i sboff sb current @ v sb = 3.3v (nominal); cpu state = off <1 ma i sbloff sbl current @ v sbl = 1.8v (nominal); cpu state = off <1 ma i cc for v sbl , note 3 i bat bat current @ v bat = 3.0 (nominal); cpu state = off 750a note 1. f clk ratings refer to in ternal clock frequency. note 2. all inputs are at 0.2v or v io ? 0.2 (cmos levels). all inputs are held st atic, and all outputs are unloaded (static i out = 0 ma). note 3. all v sbl supplied inputs are at 0.2v or v sbl ? 0.2 (cmos levels). all inputs ar e held static, and all outputs are un- loaded (static i out = 0 ma). table 9-8. ball capacitance and inductance symbol parameter min typ max unit comments c in input pin capacitance 4 7 pf note 1 c in clock input capacitance 5 8 12 pf note 1 c io i/o pin capacitance 10 12 pf note 1 c o output pin capacitance 6 8 pf note 1 l pin pin inductance 20 nh note 2 note 1. t a = 25 c, f = 1 mhz. all capacitances are not 100% tested. note 2. not 100% tested.
374 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.1.7 pull-up and pull-down resistors the following table lists input balls that are internally con- nected to a pull-up (pu) or pull-down (pd) resistor. if these balls are not used, they do not require connection to an external pu or pd resistor. note: the resistors described in this table are imple- mented as transistors. the resistance for pus assumes v in = v ss and for pds assumes v in = v io . table 9-9. balls with pu/pd resistors signal name ball no. pu/ pd typ (note 1) value [ ? ] ebga tepbga pci frame# e1 d8 pu 22.5k c/be[3:0]# a8, d8, a10, a13 h4, f3, j2, l1 pu 22.5k par c10 j4 pu 22.5k irdy# c8 f2 pu 22.5k trdy# b8 f1 pu 22.5k stop# d9 g1 pu 22.5k lock# c9 h3 pu 22.5k devsel# b5 e4 pu 22.5k perr# b9 h2 pu 22.5k serr# a9 h1 pu 22.5k req[1:0]# e3, c1 a5, b5 pu 22.5k inta# ae3 d26 pu 22.5k intb# af1 c26 pu 22.5k intc# h4 c9 pu 22.5k intd# b22 aa2 pu 22.5k low pin count (lpc) lad[3:0] aj10, ak10, al10, aj11 l29, l30, l31, m28 pu 22.5k ldrq al9 l28 pu 22.5k serirq al8 j31 pu 22.5k system (straps) clksel[3:0] al13, ak3, b27, f3 p30, d29, af3, b8 pd 100k boot16 g4 c8 pd 100k tft_prsnt ak13 p29 pd 100k lpc_rom e4 d6 pd 100k fpci_mon d3 a4 pd 100k did[1:0] d2, d4 c6, c5 pd 100k access.bus (note 2) ab1c aj13 n31 pu 22.5k ab1d al12 n30 pu 22.5k ab2c aj12 n29 pu 22.5k ab2d al11 m29 pu 22.5k parallel port afd#/dstrb# ab2 d22 pu 22.5k pe t3 d17 punot e 2 22.5k pdnot e 2 22.5k slin#/astrb# w1 b20 pu 22.5k stb#/write# ab1 a22 pu 22.5k init# y3 b21 pu 22.5k jtag tck al4 e31 pu 22.5k tms aj5 f28 pu 22.5k tdi ak5 f29 pu 22.5k trst# ak4 e29 pu 22.5k gpio (note 2) gpio1 h2, al12 d10, n30 pu 22.5k gpio6 ah3 d28 pu 22.5k gpio7 ah4 c30 pu 22.5k gpio8 aj2 c31 pu 22.5k gpio9 ag4 c28 pu 22.5k gpio10 aj1 b29 pu 22.5k gpio11 h30 aj8 pu 22.5k gpio12 aj12 n29 pu 22.5k gpio13 al11 m29 pu 22.5k gpio14 f1 d9 pu 22.5k gpio15 g3 a8 pu 22.5k gpio16 al15 v31 pu 22.5k gpio17 j4 a10 pu 22.5k gpio18 a28 ag1 pu 22.5k gpio19 h4 c9 pu 22.5k gpio20 h3, aj13 a9, n31 pu 22.5k gpio32 aj11 m28 pu 22.5k gpio33 al10 l31 pu 22.5k gpio34 ak10 l30 pu 22.5k gpio35 aj10 l29 pu 22.5k gpio36 al9 l28 pu 22.5k gpio37 ak9 k31 pu 22.5k gpio38 aj9 k28 pu 22.5k gpio39 al8 j31 pu 22.5k power management pwrbtn# e29 ah5 pu 100k gpwio[2:0] g29, g28, e31 aj6, ak5, ah6 pu 100k test and measurement gtest al5 f30 pd 22.5k note 1. accuracy is: 22.5 k ? resistors are within a range of 20 k ? to 50 k ?. 100 k ? resistors are within a range of 90 k ? to 250 k ?. note 2. controlled by software. signal name ball no. pu/ pd typ (note 1) value [ ? ] ebga tepbga
amd geode? sc3200 processor data book 375 electrical specifications revision 5.1 9.2 dc characteristics table 9-10 describes the signal buffer types of the sc3200. (see table 3-2 "4 32-ebga ball assignment - sorted by ball number" on page 29 and table 3-4 "481- tepbga ball assignment - so rted by ball number" on page 43) for each signal?s buffer type.) the subsections that follows provide detailed dc charac- teristics according to buffer type. table 9-10. buffer types symbol description reference diode diodes only, no buffer --- in ab input, access.bus compatible wi th schmitt trigger section 9.2.1 in btn input, ttl compatible with schmitt trigger, low leakage section 9.2.2 in pci input, pci compatible section 9.2.3 in strp input, strap ball (min v ih is 0.6v io ) with weak pull-down section 9.2.4 in t input, ttl compatible section 9.2.5 in ts input, ttl compatible with schmitt trigger type 200 mv section 9.2.6 in ts1 input, with schmitt trigger type 200 mv section 9.2.7 in usb input, usb compatible section 9.2.8 o ac97 output, totem-pole, ac97 compatible section 9.2.9 od n output, open-drain, capable of sinking n ma.note 1 section 9.2.10 od pci output, open-drain, pci compatible section 9.2.11 o p/n output, totem-pole, capable of sourcing p ma and sinking n ma section 9.2.12 o pci output, pci compatible, tri-state section 9.2.13 o usb output, usb compatible section 9.2.14 ts p/n output, tri-state, capable of sourcing p ma and sinking n ma section 9.2.15 wire wire, no buffer --- note 1.output from these signals is open-drain and cannot be forced high.
376 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.2.1 in ab dc characteristics 9.2.2 in btn dc characteristics 9.2.3 in pci dc characteristics note that the buffer type for pciclk (ebga ball e2 / tepbga ball a7) is in t - not in pci . symbol parameter min max unit comments v ih input high voltage 1.4 v v il input low voltage -0.5 ( note 1 ) 0.8 v i il input leakage current 10 a v in = v io -10 a v in = v ss v his input hysteresis 150 mv note 1. not 100% tested. symbol parameter min max unit comments v ih input high voltage 2.0 v sb +0.3 (note 1) v v il input low voltage -0.5 (note 1) 0.8 v i il input leakage current 5 a v in = v sb -36 a v in = v ss v his input hysteresisnote 1 250 mv note 1. not 100% tested. symbol parameter min max unit comments v ih input high voltage 0.5v io v io +0.3 (note 1) note 1. not 100% tested. v v il input low voltage -0.5 (note 1) 0.3v io v v ipu input pull-up voltage 0.7v io v note 2 note 2. not 100% tested. this parameter indicates the minimu m voltage to which pull-up resistors are calculated in order to pull a floated network. l il input leakage current +/-10 a 0 < v in < v io , note 3, note 4 note 3. input leakage currents inclu de hiz output leakage for all bidire ctional buffers wit h tri-state outputs. note 4. see exceptions 2 and 3 in section 9.2.15.1 on page 379.
amd geode? sc3200 processor data book 377 electrical specifications revision 5.1 9.2.4 in strp dc characteristics 9.2.5 in t dc characteristics 9.2.6 in ts dc characteristics 9.2.7 in ts1 dc characteristics symbol parameter min max unit comments v ih input high voltage 0.6v io v io +0.3 (note 1) v v il input low voltage 0.3v io v i il input leakage current 36 a during reset: v in = v io ? 10 a v in = v ss note 1. not 100% tested. symbol parameter min max unit comments v ih input high voltage 2.0 v io +0.3 (note 1) v v il input low voltage -0.5 (note 1) 0.8 v i il input leakage current 10 a v in = v io ? 10 a v in = v ss note 1. not 100% tested. symbol parameter min max unit comments v ih input high voltage 2.0 v io +0.3 (note 1) v v il input low voltage -0.5 (note 1) 0.8 v i il input leakage current 10 a v in = v io -10 a v in = v ss v h input hysteresis 200 mv note 1. not 100% tested. symbol parameter min max unit comments v ih input high voltage 0.5v io v io +0.3 (note 1) v v il input low voltage -0.5 (note 1) 0.3v io v i il input leakage current 10 a v in = v io -10 a v in = v ss v his input hysteresis 200 mv note 1 note 1. not 100% tested.
378 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.2.8 in usb dc characteristics figure 9-1. differential input sensitivity for common mode range 9.2.9 o ac97 dc characteristics 9.2.10 od n dc characteristics symbol parameter min max unit comments v ih input high voltage 2.0 v io +0.3 (note 1) v v il input low voltage -0.5 (note 1) 0.8 v i il input leakage current 10 a v in = v io -10 a v in = v ss v di differential input sensitivity 0.2 v |(d+)-(d-)| and figure 9-1 v cm differential common mode range 0.8 2.5 v includes v di range v se single ended receiver threshold 0.8 2.0 v note 1. not 100% tested. 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 common mode input voltage (volts) minimum differential sensitivity (volts) symbol parameter min max unit comments v oh output high voltage 0.9v io vl oh = -5 ma v ol output low voltage 0.1v io vl ol = 5 ma symbol parameter min max unit comments v ol output low voltage 0.4 v i ol = n ma
amd geode? sc3200 processor data book 379 electrical specifications revision 5.1 9.2.11 od pci dc characteristics 9.2.12 o p/n dc characteristics 9.2.13 o pci dc characteristics 9.2.14 o usb dc characteristics 9.2.15 ts p/n dc characteristics 9.2.15.1 exceptions 1) i oh is valid for a gpio pin only when it is not configured as open-drain. 2) signals with internal pull-ups have a maximum input leakage current of: where v power is v io , or v sb . 3) signals with internal pull-downs have a maximum input leakage current of: symbol parameter min max unit comments v ol output low voltage 0.1v io vl ol = 1500 a symbol parameter min max unit comments v oh output high voltage 2.4 v l oh = -p ma v ol output low voltage 0.4 v l ol = n ma symbol parameter min max unit comments v oh output high voltage 0.9v io vl oh = -500 a v ol output low voltage 0.1v io vl ol =1500 a symbol parameter min max unit comments v usb_oh high-level output voltage 2.8 3.6 (note 1) vi oh = -0.25 ma r l = 15 k ? to gnd v usb_ol low-level output voltage 0.3 v i ol = 2.5 ma r l = 1.5 k ? to 3.6v t usb_crs output signal crossover voltage 1.3 2.0 v note 1. tested by characterization. symbol parameter min max unit comments v oh output high voltage 2.4 v i oh = - p ma v ol output low voltage 0.4 v i ol = n ma v power v in ? rpull up ? () -------------------------------------- - ?? ?? ? v in v ss ? r pull down ? () ----------------------------------------- - ?? ?? +
380 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3 ac characteristics the tables in this section list the following ac characteris- tics: output delays input setup requirements input hold requirements output float delays power-up sequencing requirements the default levels for measurement of the rising clock edge reference voltage (v ref ), and other voltages are shown in table 9-11. input or output si gnals must cross these levels during testing. unless otherwise specified, all measure- ment points in this section conform to these default levels. all ac tests are at v io = 3.14v to 3.46v (3.3v nominal), t c = 0 o c to 85 o c, c l = 50 pf, unless otherwise specified. figure 9-2. drive level and measurement points table 9-11. default levels for measurement of switching parameters symbol parameter value (v) v ref reference voltage 1.5 v ihd input high drive voltage 2.0 v ild input low drive voltage 0.8 v ohd output high drive voltage 2.4 v old output low drive voltage 0.4 clk outputs inputs v ihd v ild v ref valid input valid output n+1 valid output n v ref v ref v ild v ihd min max legend: a = maximum output or float delay specification b = minimum output or float delay specification c = minimum input setup specification d = minimum input hold specification t x b a cd v ohd v old
amd geode? sc3200 processor data book 381 electrical specifications revision 5.1 9.3.1 memory controller interface the minimum input setup and hold times described in figure 9- 3 (legend c and d) define the smallest acceptable sampling window during which a synchronous input signal must be stable to ensure correct operation. figure 9-3. memory controller drive level and measurement points sdclk_out v oh v ref v ref v ref c valid output n+1 a b valid output n outputs inputs v ih v il v ol min max legend: a = maximum output delay b = minimum output delay c = minimum input setup d = minimum input hold d t x v oh v ol v old v ohd sdclk_in v ih v ref v il t x v ild v ihd sdclk[3:0]
382 amd geode? sc3200 processor data book electrical specifications revision 5.1 table 9-12. memory controller timing parameters symbol parameter min max unit comments t 1 control output valid from sdclk[3:0] -3.0 + (x * y) 0.1 + (x * y) ns note 1, note 2 t 2 ma[12:0], ba[1.0] output valid from sdclk[3:0] -3.2 + (x * y) 0.1 + (x * y) ns note 2 t 3 md[63.0] output valid from sdclk[3:0] -2.2 + (x * y) 0.7 + (x * y) ns note 2 t 4 md[63.0] read data in setup to sdclk_in 1.3 ns t 5 md[63:0] read data hold to sdclk_in 2.0 ns t 6 sdclk[3:0], sdclk_out cycle time 233 mhz 10 14 ns 266 mhz 8.3 13.5 t 7 sdclk[3:0], sdclk_out fall/rise time between (v old -v ohd ) 2ns t 9 sdclk_in fall/rise time between (v ild -v ihd ) 2ns t 10 sdclk[3:0], sdclk_out high time 233 mhz 4.0 ns 266 mhz 3.0 t 11 sdclk[3:0], sdclk_out low time 233 mhz 4.0 ns 266 mhz 2.5 note 1. control output includes all the following signals: rasa#, casa#, wea#, ckea, dqm[7:0], and cs[1:0]#. load = 50 pf, v core = 1.8v@ 233/266 mhz, v io = 3.3v, @25 o c. note 2. use the min/max equations [value+(x * y)] to calculate the actual output value. x is the shift value which is applied to the shftsdclk field, and y is 0.45 the core clock period. note that the shftsdclk field = gx_base+ memory offset 8404h[5:3]. refer to the amd geode? gx1 proces- sor data book for more information. for example, for a 266 mhz sc3200 running a 88. 7 mhz sdram clock, with a shift value of 3: t1 min = -3 + (3 * (3 .76 * 0.45)) = 2.08 ns t1 max = 0.1 + (3 * (3.76 * 0.45)) = 5.18 ns
amd geode? sc3200 processor data book 383 electrical specifications revision 5.1 figure 9-4. memory controller output valid timing diagram figure 9-5. read data in setup and hold timing diagram sdclk[3:0] control output, ma[12:0] ba[1:0], md[63:0] t 1 , t 2 , t 3 t 6 t 7 t 7 v ref v ohd v old v ref t 10 t 11 sdclk_in data valid md[63:0] read data in t 4 t 5 t 4 t 5 data valid v ref v ihd v ild t 9 t 9
384 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3.2 video port figure 9-6. video input port timing diagram table 9-13. video input port timing parameters symbol parameter min max unit comments t vp_c vpckin cycle time 18 ns t vp_s video port input setup time before vpckin rising edge 6ns t vp_h video port input hold time after vpckin rising edge 0ns t vpck_fr vpckin fall/rise time - 2 ns note 1 t vpck_d vpckin duty cycle 35/65 % note 1. guaranteed by characterization. t pck_fr t pck_fr t vp_h t vp_s t vp_c vpckin v ihd v ild v ref vpd[7:0]
amd geode? sc3200 processor data book 385 electrical specifications revision 5.1 9.3.3 tft interface figure 9-7. tft timing diagram table 9-14. tft timing parameters symbol parameter min max unit comments t ov tftd[17:0], tftde valid time after tftdck rising edge (multiplexed on ide) 08ns t ov tftd[17:0], tftde valid time after tftdck rising edge (multiplexed on parallel port) 04ns t clk_rf tftdck rise/fall time between 0.8v and 2.0v 3 ns note 1 t clk_p tftdck period time (multiplexed on ide) 25 ns t clk_p tftdck period time (multiplexed on parallel port) 12.5 ns t clk_d tftdck duty cycle 40/60 % note 1. guaranteed by characterization t ov t clk_rf t clk_p tftdck tftd[17:0] tftde
386 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3.4 access.bus interface the following tables describe the timing for the access.bus signals. notes: 1) all access.bus timing is not 100% tested. 2) in this table t clk = 1/24mhz = 41.7 ns. table 9-15. access.bus input timing parameters symbol parameter min max unit comments t bufi bus free time between stop and start condition t sclhigho t cstosi ab1c/ab2c setup time 8 * t clk - t sclri before stop condition t cstrhi ab1c/ab2c hold time 8 * t clk - t sclri after start condition t cstrsi ab1c/ab2c setup time 8 * t clk - t sclri before start condition t dhcsi data high setup time 2 * t clk before ab1c/ab2c rising edge t dlcsi data low setup time 2 * t clk before ab1c/ab2c rising edge t sclfi ab1d/ab2d fall time 300 ns t sclri ab1d/ab2d rise time 1 s t scllowi ab1c/ab2c low time 16 * t clk after ab1c/ab2c falling edge t sclhighi ab1c/ab2c high time 16 * t clk after ab1c/ab2c rising edge t sdafi ab1d/ab2d fall time 300 ns t sdari ab1d/ab2d rise time 1 s t sdahi ab1d/ab2d hold time 0 after ab1c/ab2c falling edge t sdasi ab1d/ab2d setup time 2 * t clk before ab1c/ab2c rising edge table 9-16. access.bus output timing parameters symbol parameter min max unit comments t sclhigho ab1c/ab2c high time k * t clk - 1 s after ab1c/ab2c rising edge, note 1 t scllowo ab1c/ab2c low time k * t clk - 1 s after ab1c/ab2c falling edge t bufo bus free time between stop and start condition t sclhigho 1 s note 2 t cstoso ab1c/ab2c setup time t sclhigho 1 s before stop condition, note 2 t cstrho ab1c/ab2c hold time t sclhigho 1 s after start condition, note 2 t cstrso ab1c/ab2c setup time t sclhigho 1 s before start condition, note 2 t dhcso data high setup time t sclhigho - t sdaro 1 s before ab1c/ab2c rising edge, note 2 t dlcso data low setup time t sclhigho - t sdafo 1 s before ab1c/ab2c rising edge, note 2 t sclfo ab1d/ab2d signal fall time 300 ns t sclro ab1d/ab2d signal rise time 1 s
amd geode? sc3200 processor data book 387 electrical specifications revision 5.1 figure 9-8. acb signals: rising time and falling timing diagram figure 9-9. acb start and stop condition timing diagram t sdafo ab1d/ab2d signal fall time 300 ns t sdaro ab1d/ab2d signal rise time 1 s t sdaho ab1d/ab2d hold time 7 * t clk - t sclfo after ab1c/ab2c falling edge t sdavo ab1d/ab2d valid time 7 * t clk + t rd after ab1c/ab2c falling edge note 1. k is determined by bits [7:1] of the acbctl2 register (ldn 05h/06h, offset 05h). note 2. t sclhigho value depends on the signal capacitance an d the pull-up value of the relevant pin. table 9-16. access.bus output timing parameters (continued) symbol parameter min max unit comments ab1d t sdar 0.7v io 0.3v io t sdaf 0.7v io 0.3v io ab1c t sclr 0.7v io 0.3v io t sclf 0.7v io 0.3v io ab2d ab2c ab1d ab1c t cstosi t bufi t dlcs t cstrhi start condition stop condition t dlco t cstoso t bufo t cstrho ab2d ab2c
388 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-10. acb start condition timing diagram figure 9-11. acb data bit timing diagram t cstrsi t dhcsi start condition t cstrhi ab1d ab1c t cstrho t cstrso t dhcso ab2d ab2c t sclhigho t scllowo t sdaho t sdavo t sdaso ab1d ab1c t sdasi t scllowi t sclhighi t sdahi t sdaho ab2d ab2c
amd geode? sc3200 processor data book 389 electrical specifications revision 5.1 9.3.5 pci bus interface the sc3200 is compliant with pci bus rev. 2.1 specifica- tions. relevant information from the pci bus specifications is provided below. all parameters in table 9-17 are not 100% tested. the parameters in this table are further described in figure 9- 13. figure 9-12. testing setup for slew rate and minimum timing table 9-17. pci ac specifications symbol parameter min max unit comments i oh (ac) (note 1) switching current high -12v io ma 0 < v out 0.3v io, -17.1(v io -v out )ma0.3v io < v out < 0.9v io equation a (figure 9-13) 0.7v io < v out < v io test point (note 2) -32v io ma v out = 0.7v io i ol (ac) (note 1) switching current low 16v io ma v io > v out 0.6v io 26.7v out ma 0.6v io > v out > 0.1v io equation b (figure 9-13) 0.18v io >v out >0 test point (note 2) 38v io ma v out = 0.18v io i cl low clamp current -25+(v in +1)/0.015 ma -3 < v in < -1 i ch high clamp current 25+(v in -v io -1)/0.015 ma v io +4 > v in > v io +1 slew r (note 3) output rise slew rate 1 4 v/ns 0.2v io - 0.6v io load slew f output fall slew rate 1 4 v/ns 0.6v io - 0.2v io load note 1. refer to the v/i curves in figure 9-13. this spec ification does not apply to pc iclk0, pciclk1, and pcirst# which are system outputs. note 2. maximum current requirements are met when drivers pull beyond the first step volt age. equations which define these maximum values (a and b) are provided with releva nt diagrams in figure 9-13. these maximum values are guaranteed by design. note 3. rise slew rate does not apply to open-drain outputs. this parameter is interpreted as the cumulative edge rate across the specified range, according to the test circuit in figure 9-12. buffer v cc 0.5" max. pin 1 k ? 1 k ? 10 pf output
390 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-13. v/i curves for pci output signals pull-up pull-down test point v io 0.9 v io dc drive point ac drive point 0.3 v io 0.6 v io 0.1 ac drive point dc drive point test point v io equation a for v io >v out >0.7v io i ol = (256/v io )*v out *(v io -v out ) for 0v amd geode? sc3200 processor data book 391 electrical specifications revision 5.1 figure 9-14. pciclk timing and measurement points table 9-18. pci clock parameters symbol parameter min max unit comments t cyc pciclk cycle time 30 ns note 1 t high pciclk high time 11 ns note 2 t low pciclk low time 11 ns note 2 pciclk sr pciclk slew rate 1 4 v/ns note 3 pcirst sr pcirst# slew rate 50 - mv/ns note 4 note 1. clock frequency is between nominal dc and 33 mhz. device operational parameters at frequencies under 16 mhz are not 100% tested. the clock ca n only be stopped in a low state. note 2. guaranteed by characterization. note 3. slew rate must be met acro ss the minimum peak-to-peak portion of the clock waveform (see figure 9-14). note 4. the minimum pcirst# slew rate applies only to the rising (de-assertion) edge of the reset signal. see figure 9-18 for pcirst# timing. t high 0.4 v io , p-to-p (minimum) 0.6v io 0.2v io 0.5 v io 0.4 v io 0.3 v io t cyc t low pciclk
392 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-15. load circuits for maximum time measurements table 9-19. pci timing parameters symbol parameter min max unit comments t val pciclk to signal valid delay (on the bus) 2 11 ns note 1, note 2 t val (ptp) pciclk to signal valid delay (gnt#) 2 9 ns note 1, note 2 t on float to active delay 2 ns note 1, note 3, t off active to float delay 28 ns note 1, note 3, t su input setup time to pciclk (on the bus) 7 ns note 4 t su (ptp) input setup time to pciclk (req#) 6 ns note 4 t h input hold time from pciclk 0 ns note 4 t rst pcirst# active time after power stable 1 ms note 3, note 5 t rst-clk pcirst# active time after pciclk stable 100 s note 3, note 5 t rst-off pcirst# active to output float delay 40 ns note 3, note 5, note 6 note 1. see the timing measurement conditions in figure 9-16. note 2. minimum times are evaluated with same load used for sl ew rate measurement (as shown in note 3 of table ); max- imum times are evaluated with the load circuits shown in figure 9-15, for high-going and low-going edges respec- tively. note 3. not 100% tested. note 4. see the timing measuremen t conditions in figure 9-17. note 5. pcirst# is asserted and de-asserted asynchronously with respect to pciclk (see figure 9-18). note 6. all output drivers are asynchronously floated when pcirst# is active. output buffer output buffer v cc 25 ? 25 ? 10 pf 10 pf 0.5" max. 0.5" max. pin t val (max) rising edge t val (max) falling edge
amd geode? sc3200 processor data book 393 electrical specifications revision 5.1 9.3.5.1 measurement and test conditions figure 9-16. output timing measurement conditions table 9-20. measurement condition parameters symbol value unit comments v th 0.6 v io v note 1 v tl 0.2 v io v note 1 v test 0.4 v io v v step (rising edge) 0.285 v io v v step (falling edge) 0.615 v io v v max 0.4 v io v note 2 input signal edge rate 1 v/ns note 1. the input test is performed with 0.1 v io of overdrive. timing parameters must not exceed this overdrive. note 2. v max specifies the maximum peak-to-peak waveform allowed for measuring input timing. output current leakage current t off t on pciclk output delay tri-state output v th v tl v test v step t val
394 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-17. input timing measurement conditions figure 9-18. pci reset timing v test v test input valid t su t h v test v max v th v tl pciclk input v th v tl ) ( 100 ms (typ) ) ( t rst t rst-clk t rst-off tri_state pci signals pcirst# pciclk power por# t fail v io note: the value of t fail is 500 ns (maximum) from the power rail wh ich exceeds specified tolerance by more than 500 mv.
amd geode? sc3200 processor data book 395 electrical specifications revision 5.1 9.3.6 sub-isa interface all output timing is guaranteed for 50 pf load, unless other- wise specified. the isa clock divisor (defined in f0 index 50h[2:0] of the core logic module) is 011. table 9-21. sub-isa timing parameters symbol parameter bus width (bits) type min (ns) max (ns) figure comments t rd1 memr#/docr#/rd#/trde# read active pulse width fe to re 16 m 225 9-19 standard t rd2 memr#/docr#/rd#/trde# read active pulse width fe to re 16 m 105 9-19 zero wait state t rd3 ior#/rd#/trde# read active pulse width fe to re 16 i/o 160 9-19 standard t rd4 ior#/memr#/docr#/rd#/trde# read active pulse width fe to re 8 m, i/o 520 9-19 standard t rd5 ior#/memr#/docr#/rd#/trde# read active pulse width fe to re 8 m, i/o 160 9-19 zero wait state t rcu1 memr#/docr#/rd#/trde# inactive pulse width 16 m 103 9-19 t rcu2 memr#/docr#/rd#/trde# inactive pulse width 8m163 9-19 t rcu3 ior#/rd#/trde# inactive pulse width 8, 16 i/o 163 9-19 t wr1 memw#/wr# write active pulse width fe to re 16 m 225 9-20 standard t wr2 memw#/docw#/wr# write active pulse width fe to re 16 m 105 9-20 zero wait state t wr3 iow#/wr# write active pulse width fe to re 16 i/o 160 9-20 standard t wr4 iow#/memw#/docw#/wr# write active pulse width fe to re 8 m, i/o 520 9-20 standard t wr5 iow#/memw#/docw#/wr# write active pulse width fe to re 8 m, i/o 160 9-20 zero wait state t wcu1 memw#/wr#/docw# inactive pulse width 16 m 103 9-20 t wcu2 memw#/wr#/docw# inactive pulse width 8m163 9-20 t wcu3 iow#/wr# inactive pulse width 8, 16 i/o 163 9-20 t rdyh ior#/memr#/rd#/docr#/iow#/ memw#/wr#/docw# hold after iochrdy re 8, 16 m, i/o 120 9-19 9-20 t rdya1 iochrdy valid after ior#/memr#/ rd#/docr#/iow#/memw#/wr#/ docw# fe 16 m, i/o 78 9-19 9-20
396 amd geode? sc3200 processor data book electrical specifications revision 5.1 t rdya2 iochrdy valid after ior#/memr#/ rd#/docr#/iow#/memw#/wr#/ docw# fe 8 m, i/o 366 9-19 9-20 t iocsa iocs[1:0]#/docs#/romcs# driven active from a[23:0] valid 8, 16 m, i/o 34 9-19 9-20 t iocsh iocs[1:0]#/docs#/romcs# valid hold after a[23:0] invalid 8, 16 m, i/o 0 9-19 9-20 t ar1 a[23:0]/bhe# valid before memr#/ docr# active 16 m 34 9-19 t ar2 a[23:0]/bhe# valid before ior# active 16 i/o 100 9-19 t ar3 a[23:0]/bhe# valid before memr#/ docr#/ior# active 8 m, i/o 100 9-19 t ra a[23:0]/bhe# valid hold after memr#/docr#/ior# inactive 8, 16 m, i/o 25 9-19 t rvds read data d[15:0] valid setup before memr#/docr#/ior# inactive 8, 16 m, i/o 24 9-19 t rdh read data d[15:0] valid hold after memr#/docr#/ior# inactive 8, 16 m, i/o 0 9-19 t hz read data floating after memr#/ docr#/ior# inactive 8, 16 m, i/o 41 9-19 t aw1 a[23:0]/bhe# valid before memw#/ docw# active 16 m 34 9-20 t aw2 a[23:0]/bhe# valid before iow# active 16 i/o 100 9-20 t aw3 a[23:0]/bhe# valid before memw#/ docw#/iow# active 8 m, i/o 100 9-20 t wa a[23:0]/bhe# valid hold after memw#/docw#/iow# invalid 8, 16 m, i/o 25 9-20 t dv1 write data d[15:0] valid after memw#/docw# active 8, 16 m 40 9-20 t dv2 write data d[15:0] valid after iow# active 8 i/o 40 9-20 t dv3 write data d[15:0] valid after iow# active 16 i/o -23 9-20 t wtr trde# inactive after memw#/ docw#/iow# inactive 8, 16 m, i/o 20 9-20 t dh write data d[15:0] after memw#/ docw#/iow# inactive 8, 16 m, i/o 45 9-20 t df write data d[15:0] goes tri-state after memw#/docw#/iow# inactive 8, 16 m, i/o 105 9-20 t wdar write data d[15:0] after read memr#/ docr#/ior# 8, 16 m, i/o 41 9-19 table 9-21. sub-isa timing parameters (continued) symbol parameter bus width (bits) type min (ns) max (ns) figure comments
amd geode? sc3200 processor data book 397 electrical specifications revision 5.1 figure 9-19. sub-isa read operation timing diagram t rdx t arx valid valid valid data t rcux t ra t rvds t rdh t hz a[23:0]/bhe# d[15:0] t rdyax t rdyh memw#/docw# romcs#/doccs# iow#/wr# iocs[1:0]# (read) t iocsa t iocsh t wdar d[15:0] (write) ior#/rd#/trde# memr#/docr# iochrdy note: x indicates a numeric index for the relevant symbol.
398 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-20. sub-isa write operation timing diagram t wrx t awx valid valid valid data t wcux t wa t dh a[23:0]/bhe# trde# d[15:0] iochrdy t rdyax t rdyh doccs#/romcs# t iocsh iocs[1:0]# t df t dvx t iocsa iow#/wr# memw#/docw# ior#/rd# memr#/docr# t wtr note: x indicates a numeric index for the relevant symbol.
amd geode? sc3200 processor data book 399 electrical specifications revision 5.1 9.3.7 lpc interface figure 9-21. lpc output timing diagram figure 9-22. lpc input timing diagram table 9-22. lpc and serirq timing parameters symbol parameter min max unit comments t val output valid delay 0 17 ns after pciclk rising edge t on float to active delay 2 ns after pciclk rising edge t off active to float delay 28 ns after pciclk rising edge t su input setup time 7 ns before pciclk rising edge t hi input hold time 0 ns after pciclk rising edge pciclk lpc signals/ serirq t on t val t off pciclk lpc signals/ serirq t su t hi input valid
400 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3.8 ide interface figure 9-23. ide reset timing diagram table 9-23. ide genera l timing parameters symbol parameter min max unit comments t ide_fall ide signals fall time (from 0.9v io to 0.1v io )5 nsc l = 40 pf t ide_rise ide signals rise time (from 0.1v io to 0.9v io )5 nsc l = 40 pf t ide_rst_pw ide_rst# pulse width 25 s ide_rst# t ide_rst_pw
amd geode? sc3200 processor data book 401 electrical specifications revision 5.1 table 9-24. ide register transfer to/from device timing parameters symbol parameter mode unit comments 01235 t 0 cycle time (min) 600 383 240 180 120 ns note 1 t 1 address valid to ide_ior[0:1]#/ ide_iow[0:1]# setup (min) 70 50 30 30 25 ns t 2 ide_ior[0:1]#/ide_ iow[0:1]# pulse width 8-bit (min) 290 290 290 80 70 ns note 1 t 2i ide_ior[0:1]#/ide_iow[0:1]# recovery time (min) - - - 70 25 ns note 1 t 3 ide_iow[0:1]# data setup (min) 6045303020ns t 4 ide_iow[0:1]# data hold (min) 30 20 15 10 10 ns t 5 ide_ior[0:1]# data set up (min) 5035202020ns t 6 ide_ior[0:1]# data hold (min) 55555ns t 6z ide_ior[0:1]# data tri-state (max) 30 30 30 30 30 ns note 2 t 9 ide_ior[0:1]#/ide_iow[0:1]# to address valid hold (min) 20 15 10 10 10 ns t rd read data valid to ide_iordy[0:1] active (if ide_iordy [0:1] initially low after t a (min) 00000ns t a ide_iordy[0:1] setup time 35 35 35 35 35 ns note 3 t b ide_iordy[0:1] pulse width (max) 1250 1250 1250 1250 1250 ns t c ide_iordy[0:1] assertion to release (max) 55555ns note 1. t 0 is the minimum total cycle time, t 2 is the minimum command active time, and t 2i is the minimum command recov- ery time or command inactive time. the actual cycle time equals the sum of the command active time and the com- mand inactive time. the three timing requirements of t 0 , t 2 , and t 2i are met. the minimum total cycle time requirements is greater than the sum of t 2 and t 2i . (this means that a host implementation can lengthen t 2 and/or t 2i to ensure that t 0 is equal to or greater than the value report ed in the device?s identify device data.) note 2. this parameter specifies the time from the rising edge of ide_ ior[0:1]# to the ti me that the data bus is no longer driven by the device (tri-state). note 3. the delay from the activation of ide_ior[0:1]# or ide_ iow[0:1]# until the state of id e_iordy[0,1] is first sampled. if ide_iordy[0:1] is inactive, then the host waits until ide_ iordy[0:1] is active before the pio cy cle is completed. if the device is not driving ide_io rdy[0:1] negated after activation (t a ) of ide_ior[0:1]# or ide_iow[0:1]#, then t 5 is met and t rd is not applicable. if the device is driving ide_iordy[0:1] negated after activation (t a ) of ide_ior[0:1]# or id e_iow[0:1]#, then t rd is met and t 5 is not applicable.
402 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-24. register transfer to/from device timing diagram addr valid 1 write read t 0 t 1 t 2 t 9 t 2i t 3 t 5 t 6z t 6 t a t 4 t c t rd t b t c ide_ior0# ide_iow0# ide_iordy0 2,3 ide_iordy0 2,4 ide_iordy0 2,5 notes: 1) device address consists of signals ide_cs[0:1]# and ide_addr[2:0]. 2) negation of ide_iordy0,1 is used to extend the pio cycle. the determination of whethe r or not the cycle is to be extended is made by the host after t a from the assertion of ide_ior[0:1]# or ide_iow[0:1]#. 3) device never negates ide_iordy[0:1]. device keeps ide_iordy[0:1] released, and no wait is generated. 4) device negates ide_iordy[0:1] before t a but causes ide_iordy[0:1] to be asserted before t a . ide_iordy[0:1] is released, and no wait is generated. 5) device negates ide_iordy[0:1] before t a . ide_iordy[0:1] is released prior to negation and may be asserted for no more than 5 ns before release. a wait is generated. 6) the cycle completes after ide_iordy[0:1 ] is reasserted. for cycles where a wait is generated an d ide_ior[0:1] is asserted, the device places read data on ide_data[15:0] for t rd before asserting ide_iordy[0:1]. ide_data[7:0] ide_data[7:0]
amd geode? sc3200 processor data book 403 electrical specifications revision 5.1 table 9-25. ide pio data transfer to/from device timing parameters symbol parameter mode unit comments 01234 t 0 cycle time (min) 600 383 240 180 120 ns note 1 t 1 address valid to ide_ior[0:1]#/ ide_iow[0:1]# setup (min) 70 50 30 30 25 ns t 2 ide_ior[0:1]#/ide_iow[0:1]# 16-bit (min) 165 125 100 80 70 ns note 1 t 2i ide_ior[0:1]#/ide_iow[0:1]# recovery time (min) - - - 70 25 ns note 1 t 3 ide_iow[0:1]# data setup (min) 6045303020ns t 4 ide_iow[0:1]# data hold (min) 30 20 15 10 10 ns t 5 ide_ior[0:1]# data set up (min) 5035202020ns t 6 ide_ior[0:1]# data hold (min) 55555ns t 6z ide_ior[0:1]# data tri-state (max) 30 30 30 30 30 ns note 2 t 9 ide_ior[0:1]#/ide_iow[0:1]# to address valid hold (min) 20 15 10 10 10 ns t rd read data valid to ide_iordy[0,1] active (if ide_iordy [0:1] initially low after t a ) (min) 00000ns t a ide_iordy[0:1] setup time 35 35 35 35 35 ns note 3 t b ide_iordy[0:1] pulse width (max) 1250 1250 1250 1250 1250 ns t c ide_iordy[0:1] assertion to release (max) 55555ns note 1. t 0 is the minimum total cycle time, t 2 is the minimum command active time, and t 2i is the minimum command recov- ery time or command inactive time. the actual cycle time equals the sum of the command active time and the com- mand inactive time. the three timing requirements of t 0 , t 2 , and t 2i are met. the minimum total cycle time requirement is greater than the sum of t 2 and t 2i . (this means that a host implementation may lengthen t 2 and/or t 2i to ensure that t 0 is equal to or greater than the value report ed in the device?s identify device data.) note 2. this parameter specifies the time from the rising edge of ide_ ior[0:1]# to the ti me that the data bus is no longer driven by the device (tri-state). note 3. the delay from the activation of ide_ior[0:1]# or ide_ iow[0:1]# until the state of id e_iordy[0:1] is first sampled. if ide_iordy[0:1] is inactive, then the host waits until ide_ iordy[0:1] is active before the pio cy cle is completed. if the device is not driving ide_iordy [0:1] negated after the activation (t a ) of ide_ior[0:1]# or ide_iow[0:1]#, then t 5 is met and t rd is not applicable. if the device is driving ide_iordy[0:1] negated after the activation (t a ) of ide_ior[0:1]# or id e_iow[0:1]#, then t rd is met and t 5 is not applicable.
404 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-25. pio data transfer to/from device timing diagram addr valid 1 write ide_data[15:0] read ide_data[15:0] t 0 t 1 t 2 t 9 t 2i t 3 t 5 t 6z t 6 t a t 4 t c t rd t b t c ide_ior0# ide_iow0# ide_iordy0 2,3 ide_iordy0 2,4 ide_iordy0 2,5 notes: 1) device address consists of signals i de_cs[0:1]# and ide_addr[2:0]. 2) negation of ide_iordy[0:1] is used to extend the pio cycle. the de termination of whether or not the cycle is to be extended is made by the host after t a from the assertion of ide_ior[0:1]# or ide_iow[0:1]#. 3) device never negates ide_iordy[0:1]. devices keep ide_iordy[0:1] released, and no wait is generated. 4) device negates ide_iordy[0:1] before t a but causes ide_iordy[0:1] to be asserted before t a . ide_iordy[0:1] is released, and no wait is generated. 5) device negates ide_iordy[0:1] before t a . ide_iordy[0:1] is released prior to negation and may be asserted for no more than 5 ns before release. a wait is generated. 6) the cycle completes after ide_iordy[0: 1] is reasserted. for cycles where a wa it is generated a nd ide_ior[0:1]# is asserted, the device places read data on ide_data[15:0] for t rd before asserting ide_iordy[0:1].
amd geode? sc3200 processor data book 405 electrical specifications revision 5.1 table 9-26. ide multiword dma data transfer timing parameters symbol parameter mode unit comments 012 t 0 cycle time (min) 480 150 120 ns note 1 t d ide_ior[0:1]#/ide_iow[0:1]# (min) 215 80 70 ns t e ide_ior[0:1]# data a ccess (max) 150 60 50 ns t f ide_ior[0:1]# dat a hold (min) 5 5 5 ns t g ide_iow[0:1]#/ide_io w[0:1]# data setup (min) 100 30 20 ns t h ide_iow[0:1]# data hold (min) 20 15 10 ns t i ide_dack[0:1]# to ide_ior[0:1]#/ ide_iow[0:1]# setup (min) 000ns t j ide_ior[0:1]#/ide_iow[0:1]# to ide_dack[0:1]# hold (min) 20 5 5 ns t kr ide_ior[0:1]# negated pulse width (min) 50 50 25 ns t kw ide_iow[0:1]# negated pulse width (min) 215 50 25 ns t lr ide_ior[0:1]# to ide_dreq[0:1] delay (max) 120 40 35 ns t lw ide_iow[0:1]# to ide_dreq0,1 delay (max) 40 40 35 ns t m ide_cs[0:1]# valid to ide_ior[0:1]#/ ide_iow[0:1]# (min) 50 30 25 ns t n ide_cs[0:1]# hold 15 10 10 ns t z ide_dack[0:1]# to tri-state 20 25 25 ns note 1. t 0 is the minimum total cycle time, t d is the minimum command active time, and t kr or t kw is the minimum command recovery time or command inactive ti me. the actual cycle time equals the su m of the command ac tive time and the command inactive time. the three timing requirements of t 0 , t d and t kr/kw , are met. the mini mum total cycle time requirement t 0 is greater than the sum of t d and t kr/kw . (this means that a host im plementation can lengthen t d and/or t kr/kw to ensure that t 0 is equal to or greater than the value reported in the device?s identify device data.)
406 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-26. multiword dma data transfer timing diagram t m t n t l t j t k t d t i t e t z t f t g t g t h t 0 ide_cs[1:0]# ide_data[15:0] ide_data[15:0] ide_dreq0 ide_dack0# ide_ior0# ide_iow0# notes: 1) for multiword dma transfers, the device may negate ide_ dreq[0:1] within the tl specified time once ide_dack[0:1 is asserted, and reassert it again at a later time to resume th e dma operation. alternatively, if the device is able to c o tinue the transfer of data, the device may leave ide_dreq[0:1] asserted and wait for the host to reass e ide_dack[0:1]#. 2) this signal can be negated by the host to suspend the dma transfer in process.
amd geode? sc3200 processor data book 407 electrical specifications revision 5.1 table 9-27. ide ultradma data burst timing parameters symbol parameter mode 0 mode 1 mode 2 unit comments min max min max min max t 2cyc typical sustained average two cycle time 240 160 120 ns two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of strobe) 235 156 117 ns t cyc cycle time allowing fo r asymmetry and clock variations (from strobe edge to strobe edge) 114 75 55 ns t ds data setup time (at recipient) 15 10 7 ns t dh data hold time (at recipient) 5 5 5 ns t dvs data valid setup time at sender (from data bus being valid until strobe edge) 70 48 34 ns t dvh data valid hold time at sender (from strobe edge until data may become invalid) 666ns t fs first strobe time (for device to first negate ide_irdy[0:1] (dstrobe[0:1]) from ide_iow[0:1]# (stop[0:1]) during a data in burst) 0 230 0 200 0 170 ns t li limited interlock time 0 150 0 150 0 150 ns note 1 t mli interlock time with minimum 20 20 20 ns note 1 t ui unlimited interlock time 0 0 0 ns note 1 t az maximum time allowed for output drivers to release (from being asserted or negated) 10 10 10 ns t zah minimum delay time required for output driv- ers to assert or negate (from released state) 20 20 20 ns t zad 000ns t env envelope time (from ide_dack[0:1]# to ide_iow[0:1]# (stop[0:1]) and ide_ior[0:1]# (hdmardy[0:1]#) during data out burst initiation) 20 70 20 70 20 70 ns t sr strobe to dmardy time (if dmardy# is negated before this long after strobe edge, the recipient receives no more than one additional data word) 50 30 20 ns t rfs ready-to-final-strobe time (no strobe edges are sent this long after negation of dmardy#) 75 60 50 ns t rp ready-to-pause time (time that recipient waits to initiate pause after negating dmardy#) 160 125 100 ns t iordyz pull-up time before allowing ide_iordy[0:1] to be released 20 20 20 ns t ziordy minimum time device waits before driving ide_iordy[0:1] 000ns t ack setup and hold times for ide_dack[0:1]# (before assertion or negation) 20 20 20 ns t ss time from strobe edge to negation of ide_dreq[0:1] or assertion of ide_iow[0:1]# (stop[0:1]) (when sender terminates a burst) 50 50 50 ns note 1. t ui , t mli , and t li indicate sender-to-recipient or recipi ent-to-sender interlocks, that is, one agent (either sender or recipient) is wait- ing for the other agent to respond wi th a signal before proceeding. t ui is an unlimited interlock with no maximum time value. t mli is a limited timeout with a defined minimum. t li is a limited time-out with a defined maximum.
408 amd geode? sc3200 processor data book electrical specifications revision 5.1 all timing parameters are measured at the connector of the device to which the parameter applies. for example, the sender stops generating strobe edges t rfs after the negation of dmardy. both strobe and dmardy timing measurements are taken at the connector of the sender. figure 9-27. initiating an ultradma data in burst timing diagram t ui t ack t env t fs t fs t zad t ack t ziordy t az t ack t dvs t dvh t env t zad ide_data[15:0] ide_addr[2:0] ide_cs[0:1] ide_req0 (device) i de_dack0# (host) ide_iow0# (stop0) (host) i de_ior0# (hdmardy0#) (host) ide_irdy0 (dstrobe0) (device) note: the definitions for the ide_iow[0: 1]# (stop[0:1]), ide_ior[0:1]# (hdmardy[0:1]#) and ide_irdy[0:1] (dstrobe[0:1]) signal lines are not in effect un til ide_req[0:1] and ide_dack[0:1]# are asserted.
amd geode? sc3200 processor data book 409 electrical specifications revision 5.1 figure 9-28. sustained ultradma data in burst timing diagram t ds t dh t ds t dh t dh t dvh t dvs t dvh t dvs t dvh t 2cyc t cyc t cyc t 2cyc ide_data[15:0] at device ide_data[15:0] at host ide_irdy0 (dstrobe0) at device ide_irdy0 (dstrobe0) at host note: ide_data[15:0] and ide_irdy[0:1] (dstrobe[0:1]) signa ls are shown at both the host and the device to emphasize that cable settling time and cable propagation del ay do not allow the data signals to be considered sta- ble at the host until a certain amount of time after they are driven by the device.
410 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-29. host pausing an ultradma data in burst timing diagram t rp ide_data[15:0] (device) t rfs t sr ide_irdy0 (dstrobe0) (device) ide_ior0 (hdmardy0 ) (host) ide_iow0 (stop0) (host) ide_dack0 (host) ide_dreq0 (device) notes: 1) the host can assert ide_iow[0:1]# (stop[0:1]#) to re quest termination of the ultradma burst no sooner than t rp after ide_ior[0:1]# (hdmardy[0:1]#) is de-asserted. 2) if the t sr timing is not satisfied, the host may receive up to two additional data words from the device.
amd geode? sc3200 processor data book 411 electrical specifications revision 5.1 figure 9-30. device terminating an ultr adma data in burst timing diagram ide_data[15:0] (device) ide_cs[0:1]# ide_addr[2:0] cr t ack t dvh t dvs t zah t az t ss t li t ack t iordz t ack t mli t li t li ide_irdy0 (dstrobe0) (device) ide_ior0# (hdmardy0#) (host) ide_iow0# (stop0#) (host) ide_dack0# (host) ide_dreq0 (device) note: the definitions for the ide_iow[0:1]# (stop[0:1]#), ide_ior[0:1]# (hdmardy[0:1 ]#), and ide_irdy[0:1] (dstrobe[0:1]) signal lines are no longer in effect after ide_dreq[0:1] and ide_dack[0:1]# are de-asserted.
412 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-31. host terminating an ultradma data in burst timing diagram ide_data[15:0] (device) ide_cs[0:1]# ide_addr[2:0] cr t ack t dvh t dvs t ack t iordyz t ack t mli t li t rp t mli t li t rfs t az t zah ide_irdy0 (dstrobe0) (device) ide_ior0# (hdmardy0#) (host) ide_iow0# (stop0#) (host) ide_dack0# (host) ide_dreq0 (device) note: the definitions for the ide_iow[0:1]# (stop[0:1]#), ide_ior[0:1]# (hdmardy[0:1 ]#), and ide_irdy[0:1] (dstrobe[0:1]) signal lines are no longer in effect after ide_dreq[0:1] and ide_dack[0:1] are de-asserted.
amd geode? sc3200 processor data book 413 electrical specifications revision 5.1 figure 9-32. initiating an ultradma data out burst timing diagram ide_data[15:0] (device) ide_cs[0:1]# ide_addr[2:0] t ui t ack t env t li t ui t ziordy t ack t dvs t dvh t ack ide_dack0# (host) ide_dreq0 (device) ide_iow0# (stop0#) (host) ide_iordy0 (ddmardy0) (device) ide_ior0# (hstrobe0#) (host) note: the definitions for the ide_iow[0:1]]# (stop[0:1]#) , ide_iordy[0:1]# (ddmardy[0:1]) and ide_ior[0:1]# (hstrobe[0:1]#) signal lines are not in effect un til ide_dreq[0:1] and ide_da ck[0:1]# are asserted.
414 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-33. sustained ultradma data out burst timing diagram t ds t dh t ds t dh t dh t dvh t dvs t dvh t dvs t dvh t 2cyc t cyc t cyc t 2cyc ide_data[15:0] at host ide_data[15:0] at device ide_ior0# (hstrobe0#) at host ide_ior0# (hstrobe0#) at device note: ide_data[15:0] and ide_ior[0:1]# (h strobe[0:1]#) signals are shown at both the device and the host to emphasize that cable settling time and cable propagation del ay do not allow the data signals to be considered sta- ble at the device until a certain amount of time after they are driven by the device.
amd geode? sc3200 processor data book 415 electrical specifications revision 5.1 figure 9-34. device pausing an ultradma data out burst timing diagram t rp ide_data[15:0] (host) t rfs t sr ide_ior0# (hstrobe0#) (host) ide_dack0# (host) ide_dreq0 (device) ide_iow0# (stop0#) (host) ide_iordy0# (ddmardy0#) (device) notes: 1) the device can de-assert ide_dreq[0:1] to request termination of the ultradma burst no sooner than t rp after ide_iordy[0:1]# (ddmardy[0:1]#) is de-asserted. 2) if the t sr timing is not satisfied, the device may receive up to two additional datawords from the host.
416 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-35. host terminating an ultradma data out burst timing diagram ide_data[15:0] (host) ide_cs[0:1]# ide_addr[2:0] cr t li t mli t ack t li t ss t li t ack t dvh t dvs t ack t iordyz ide_ior0# (hstrobe0#) (host) ide_iordy0# (ddmardy0)# (device) ide_iow0# (stop0#) (host) ide_dack0# (host) ide_dreq0 (device) note: the definitions for the ide_iow[0:1]# (stop[0:1]#), ide_iordy[0,1]# (d dmardy[0:1]#) and ide_ior[0:1]# (hstrobe[0:1]#) signal lines are no longer in effect after ide_dreq[0:1] and ide_ dack[0:1]# are de-asserted.
amd geode? sc3200 processor data book 417 electrical specifications revision 5.1 figure 9-36. device terminating an ultradma data out burst timing diagram ide_data[15:0] (host) ide_cs[0:1]# ide_addr[2:0] cr t ack t dvh t dvs t rfs t ack t iordz t ack t mli t li t rp t mli t li ide_ior0# (hstrobe0#) (host) ide_iordy0# (ddmardy0#) (device) ide_dreq0 (device) ide_dack0 (host) ide_iow0# (stop0#) (host) note: the definitions for the ide_iow[0:1]# (stop[0:1]#), ide_iordy[0:1]# (d dmardy[0:1]#) and ide_ior[0:1]# (hstrobe[0:1]#) signal lines are no longer in effect after ide_dreq[0:1] and ide_ dack[0:1]# are de-asserted.
418 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3.9 universal serial bus (usb) interface table 9-28. usb timing parameters symbol parameter min ma x unit figure comments full speed source (note 1, note 2) t usb_r1 dpos_port1,2,3, dneg_port1,2,3 driver rise time 4 20 ns 9-37 (monotonic) from 10% to 90% of the d_port lines t usb_f1 dpos_port1,2,3, dneg_port1,2,3 driver fall time 4 20 ns 9-37 (monotonic) from 90% to 10% of the d_port lines t usb_frfm rise/fall time matching 90 110 % t usb_fsdr full-speed data rate 11.97 12.03 mbps average bit rate 12 mbps 0.25% t usb_fsf full-speed frame interval 0.9995 1.0005 ms 1.0 ms 0.05% t period_f full-speed period between data bits 83.1 83.5 ns average bit rate 12 mbps t usb dor driver-output resistance 28 43 w steady-state drive t usb_dj11 source differential driver jitter for con- secutive transition ?3.5 3.5 ns 9-38 note 3, note 4 t usb_dj12 source differential driver jitter for paired transitions ?4.0 4.0 ns 9-38 note 3, note 4 t usb_se1 source eop width 160 175 ns 9-38 note 4, note 5 t usb_de1 differential to eop transition skew ?2 5 ns 9-39 note 4, note 5 t usb_rj11 receiver data jitter tolerance for con- secutive transition ?18.5 18.5 ns 9-40 note 4 t usb_rj12 receiver data jitter tolerance for paired transitions ?9 9 ns 9-40 note 4 full speed receiver eop width (note 4) t usb_re11 must reject as eop 40 ns 9-39 note 5 t usb_re12 must accept as eop 82 ns 9-39 note 5 low speed source (note 1) t usb_r2 dpos_port1,2,3, dneg_port1,2,3 driver rise time 75 300 (note 6) ns 9-37 (monotonic) from 10% to 90% of the d_port lines t usb_f2 dpos_port1,2,3, dneg_port1,2,3 driver fall time 75 300 (note 6) ns 9-37 (monotonic) from 90% to 10% of the d_port lines t usb_lrfm low-speed rise/fall time matching 80 120 % t usb_lsdr low-speed data rate 1.4775 1.5225 mbps average bit rate 1.5 mbps 1.5% t period_l low-speed period 0.657 0.677 s at 1.5 mbps t usb_djd21 source differential driver jitter for con- secutive transactions ?75 75 ns host (downstream), note 4 t usb_djd22 source differential driver jitter for paired transactions ?45 45 ns 9-38 host (downstream), note 4 t usb_dju21 source differential driver jitter for con- secutive transaction ?95 95 ns 9-38 function (downstream), note 4
amd geode? sc3200 processor data book 419 electrical specifications revision 5.1 t usb_dju22 source differential driver jitter for paired transactions ?150 150 ns 9-38 function (downstream), note 4 t usb_se2 source eop width 1.25 1.5 s 9-39 note 4, note 5 t usb_de2 differential to eop transiti on skew ?40 100 ns 9-39 note 5 t usb_rjd21 receiver data jitter tolerance for con- secutive transactions ?152 152 ns 9-40 host (upstream), note 4 t usb_rjd22 receiver data jitter tolerance for paired transactions ?200 200 ns 9-40 host (upstream), note 4 t usb_rju21 receiver data jitter tolerance for con- secutive transactions ?75 75 ns 9-40 function (downstream), note 4 t usb_rju22 receiver data jitter tolerance for paired transactions ?45 45 ns 9-40 function (downstream), note 4 low speed receiver eop width (note 5) t usb_re21 must reject as eop 330 ns 9-38 t usb_re22 must accept as eop 675 ns 9-38 note 1. unless otherwise specified, a ll timings use a 50 pf capacitive load (c l ) to ground. note 2. full-speed timing has a 1.5 k ? pull-up to 2.8 v on the dpos_port1,2,3 lines. note 3. timing difference between the differential data signals (dpos_port1, 2,3 and dneg_port1,2,3). note 4. measured at the crossover point of different ial data signals (dpos_port1,2,3 and dneg_port1,2,3). note 5. eop is the end of packet where dpos_port t = dneg_port = se0. se0 occurs when output level voltage v se (min). note 6. c l = 350 pf. table 9-28. usb timing parameters (continued) symbol parameter min ma x unit figure comments
420 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-37. data signal rise and fall timing diagram figure 9-38. source differential data jitter timing diagram rise time fall time t usb_r1,2 t usb_f1,2 90% 90% 10% 10% differential data lines c l c l full speed: 4 to 20 ns at c l = 50 pf low speed: 75 ns at c l = 50 pf, 300 ns at c l = 350 pf t period_f paired transitions consecutive transitions differential data lines crossover points n*t period _ f + t usb_dj11 n*t period_f + t usb_dj12 (1.3-2.0) v t usb_dj12 t usb_dj11 t period_l t usb_djd21 t usb_dju21 t usb_djd22 t usb_dju22 n*t period_l + t usb_djd21 n*t period_l + t usb_dju21 n*t period_l + t usb_djd22 n*t period_l + t usb_dju22
amd geode? sc3200 processor data book 421 electrical specifications revision 5.1 figure 9-39. eop width timing diagram figure 9-40. receiver jitter tolerance timing diagram eop width data crossover level differential data lines t period_f tperiod_l differential data to se0 skew n*t period_f + t usb_de1 n*t period_l + t usb_de2 t usb_se1, t usb_se2 t usb_re11, t usb_re12 t usb_re21, t usb_re22 source: receiver: t period_f paired transitions consecutive transitions differential data lines crossover points n*t period_f + t usb_rj11 n*t period_f + t usb_rj12 t usb_rj12 t usb_rj11 t period_l t usb_rjd21 t usb_rjd22 t usb_rju22 n*t period_l + t usb_rjd21 n*t period_l + t usb_rju21 n*t period_l + t usb_rjd22 n*t period_l + t usb_rju22 t usb_rju21
422 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3.10 serial port (uart) figure 9-41. uart, sharp-ir, sir, and c onsumer remote control timing diagram table 9-29. uart, sharp-ir, sir, and consumer remote control timing parameters symbol parameter min max unit comments t bt single bit time in uart and sharp-ir t btn - 25 (note 1) t btn + 25 ns transmitter t btn - 2% t btn + 2% ns receiver t cmw modulation signal pulse width in sharp-ir and consumer remote control t cwn - 25 (note 2) t cwn + 25 ns transmitter 500 ns receiver t cmp modulation signal period in sharp-ir and consumer remote control t cpn - 25 (note 3) t cpn + 25 ns transmitter t mmin (note 4) t mmax (note 4) ns receiver t spw sir signal pulse width ( 3 / 16 ) x t btn - 15 (note 1) ( 3 / 16 ) x t btn + 15 (note 1) ns transmitter, variable 1.48 1.78 s transmitter, fixed 1 s receiver s drt sir data rate tolerance % of nominal data rate 0.87% transmitter 2.0% receiver t sjt sir leading edge jitter % of nominal bit duration 2.5% transmitter 6.5% receiver note 1. t btn is the nominal bit time in uart, sharp-ir, sir and co nsumer remote control modes. it is determined by the setting of the baud generator divisor registers. note 2. t cwn is the nominal pulse width of the modulation signal for sharp-ir and consumer remote control modes. it is determined by the mcpw field (bits [7:5]) of the irtxmc register and the txhsc bit (bit 2) of the rccfg register. note 3. t cpn is the nominal period of the modulation signal for shar p-ir and consumer remote control modes. it is deter- mined by the mcfr field (bits [4:0]) of the irtxmc re gisterand the txhsc bit (bit 2) of the rccfg register. note 4. t mmin and t mmax define the time range within which the period of the incoming subcarrier signal has to fall in order for the signal to be accepted by the receiver. these time values are determined by the contents of r egister irrxdc and the setting of the rxhsc bit (bit 5) of the rccfg register. t bt t spw t cmp uart sharp ir consumer remote sir t cmw control
amd geode? sc3200 processor data book 423 electrical specifications revision 5.1 9.3.11 fast ir port figure 9-42. fast ir (mir and fir) timing diagram table 9-30. fast ir port timing parameters symbol parameter min max unit comments t mpw mir signal pulse width t mwn -25 (note 1) t mwn +25 ns transmitter 60 ns receiver m drt mir transmitter data rate toler- ance 0.1% t mjt mir receiver edge jitter, % of nominal bit duration 2.9% t fpw fir signal pulse width 120 130 ns transmitter 90 160 ns receiver t fdpw fir signal double pulse width 245 255 ns transmitter 215 285 ns receiver f drt fir transmitter data rate toler- ance 0.01% t fjt fir receiver edge jitter, % of nominal bit duration 4.0% note 1. t mwn is the nominal pulse width for mir mode. it is determined by the m_pwid field (bits [4:0]) in the mir_pw register at offset 01h in bank 6 of logical device 5. t fpw data mir fir symbol t fdpw chips t mpw
424 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3.12 parallel port interface figure 9-43. standard parallel port typical data exchange timing diagram table 9-31. standard parallel port timing parameters symbol parameter min typ max unit comments t pdh port data hold 500 ns note 1 t pds port data setup 500 ns note 1 t sw strobe width 500 ns note 1 note 1. times are system dependent and are therefore not tested. t pds t pdh t sw busy ack# pd[7:0] stb#
amd geode? sc3200 processor data book 425 electrical specifications revision 5.1 figure 9-44. enhanced parallel port timing diagram table 9-32. enhanced parallel port timing parameters symbol parameter min max epp 1.7 epp 1.9 unit comments t ww19a write# active from wait# low 45 x ns t ww19ia write# inactive from wait# low 45 x ns t wst19a dstrb# or astrb# active from wait# low 65 x ns t west dstrb# or astrb# active after write# active 10 x x ns t wpdh pd[7:0] hold after write# inactive 0xxns t wpds pd[7:0] valid after write# active 15 x x ns t epdw pd[7:0] valid width 80 x x ns t epdh pd[7:0] hold after dstrb# or astrb# inactive 0xxns write# dstrb# astrb# pd[7:0] wait# valid t ww19ia t wpdh t epdh t epdw or t ww19a t wst19a t wpds t west t wst19a
426 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3.12.1 extended capab ilities port (ecp) figure 9-45. ecp forward mode timing diagram table 9-33. ecp forward mode timing parameters symbol parameter min max unit comments t ecdsf data setup before stb# active 0 ns t ecdhf data hold after busy inactive 0 ns t eclhf busy active after stb# active 75 ns t echhf stb# inactive after busy active 0 1 s t echlf busy inactive after stb# active 0 35 ms t ecllf stb# active after busy inactive 0 ns pd[7:0] stb# busy t echhf t echlf t ecllf t ecdsf t eclhf t ecdhf afd#
amd geode? sc3200 processor data book 427 electrical specifications revision 5.1 figure 9-46. ecp reverse mode timing diagram table 9-34. ecp reverse mode timing parameters symbol parameter min max unit comments t ecdsr data setup before ack# active 0 ns t ecdhr data hold after afd# active 0 ns t eclhr afd# inactive after ack# active 75 ns t echhr ack# inactive after afd# inactive 0 35 ms t echlr afd# active after ack# inactive 0 1 s t ecllr ack# active after afd# active 0 ns pd[7:0] ack# afd# t echhr t echlr t ecllr t ecdsr t eclhr t ecdhr busy#
428 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3.13 audio interface (ac97) figure 9-47. ac97 reset timing diagram figure 9-48. ac97 sync timing diagram table 9-35. ac reset timing parameters symbol parameter min typ max unit comments t rst_low ac97_rst# active low pulse width 1.0 s t rst2clk ac97_rst# inactive to bit_clk startup delay 162.8 ns ac97_rst# bit_clk t rst_low t rst2clk table 9-36. ac97 sync timing parameters symbol parameter min typ max unit comments t sync_high sync active high pulse width 1.3 s t sync_ia sync inactive to bit_clk startup delay 162.8 ns sync bit_clk t sync_high t sync_ia
amd geode? sc3200 processor data book 429 electrical specifications revision 5.1 figure 9-49. ac97 clocks diagram table 9-37. ac97 clocks parameters symbol parameter min typ max unit comments f bit_clk bit_clk frequency 12.288 mhz t clk_pd bit_clk period 81.4 ns t clk_j bit_clk output jitter 750 ps t clk_h bit_clk high pulse width 32.56 40.7 48.84 ns note 1 t clk_l bit_clk low pulse width 32.56 40.7 48.84 ns note 1 f sync sync frequency 48.0 khz t sync_pd sync period 20.8 s t sync_h sync high pulse width 1.3 s t sync_l sync low pulse width 19.5 s f ac97_clk ac97_clk frequency 24.576 mhz t ac97_clk_pd ac97_clk period 40.7 ns t ac97_clk_d ac97_clk duty cycle 45 55 % t ac97_clk_fr ac97_clk fall/rise time 2 5 ns t ac97_clk_j ac97_clk output edge-to- edge jitter 100 ps measured from edge to edge note 1. worst case duty cycle restricted to 40/60. bit_clk sync t clk_pd t clk_h t clk_l t sync_h t sync_l t sync_pd t ac97_clk_fr v ohd v old t ac97_clk_pd ac97_clk
430 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-50. ac97 data timing diagram table 9-38. ac97 i/o timing parameters symbol parameter min typ max unit comments t ac97_s input setup to falling edge of bit_clk 15.0 ns t ac97_h hold from falling edge of bit_clk 10.0 ns t ac97_ov sdata_out or sync valid after rising edge of bit_clk 15 ns t ac97_oh sdata_out or sync hold time after falling edge of bit_clk 5ns t ac97_sv sync out valid after rising edge of bit_clk 15 ns t ac97_sh sync out hold after falling edge of bit_clk 5ns bit_clk sdata_in, sdata_in2 t ac97_s t ac97_h t ac97_ov t ac97_oh t ac97_sv t ac97_sh sdata_out/sync
amd geode? sc3200 processor data book 431 electrical specifications revision 5.1 figure 9-51. ac97 rise and fall timing diagram table 9-39. ac97 signal rise and fall timing parameters symbol parameter min typ max unit comments trise clk bit_clk rise time 2 6 ns tfall clk bit_clk fall time 2 6 ns trise sync sync rise time 2 6 ns c l = 50 pf tfall sync sync fall time 2 6 ns c l = 50 pf trise din sdata_in rise time 2 6 ns tfall din sdata_in fall time 2 6 ns trise dout sdata_out rise time 2 6 ns c l = 50 pf tfall dout sdata_out fall time 2 6 ns c l = 50 pf trise clk tfall clk bit_clk trise sync tfall sync sync trise din tfall din sdata_in trise dout tfall dout sdata_out 90% 10% 90% 10% 90% 10% 90% 10%
432 amd geode? sc3200 processor data book electrical specifications revision 5.1 figure 9-52. ac97 low power mode timing diagram table 9-40. ac97 low power mode timing parameters symbol parameter min typ max unit comments t s2_pdown end of slot 2 to bit_clk, sdata_in low 1.0 s sync bit_clk sdata_out sdata_in slot 1 slot 2 note: bit_clk is not to scale t s2_pdown
amd geode? sc3200 processor data book 433 electrical specifications revision 5.1 9.3.14 power management interface led# cycle time: 1 s 0.1 s, 40%-60% duty cycle. figure 9-53. pwrbtn# trigger and onctl# timing diagram figure 9-54. gpwio and onctl# timing diagram table 9-41. pwrbtn# timing parameters symbol parameter min max unit comments t pbtnp pwrbtn# pulse width 16 ms note 1 t pbtne delay from pwrbtn# events to onctl# 14 16 ms note 1. not 100% tested. pwrbtn# onctl# t pbtnp t pbtnp t pbtne t pbtne table 9-42. power management event (gpwio) and onctl# timing parameters symbol parameter min max unit comments t pm power management event to onctl# assertion 45 ns t pm onctl# pwrcnt1 gpwiox pwrcnt2
434 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3.15 power-up sequencing figure 9-55. power-up sequenci ng with pwrbtn# timing diagram table 9-43. power-up sequence using the power button timing parameters symbol parameter min max unit comments t 1 voltage sequence -100 100 ms optimum power-up results with t 1 = 0. t 2 pwrbtn# inactive after v sb or v sbl applied, whichever is applied last 0 1 s pwrbtn# is an input and must be powered by v sb . t 3 pwrbtn# active pulse width 16 4000 ms if pwrbtn# max is exceeded, onctl# will go inactive. t 4 onctl# inactive after v sb applied 0 1 ms t 5 signal active after pwrbtn active 14 16 ms t 6 v core and v io applied after onctl# active 0 ms system determines when v core and v io are applied, hence there is no maximum constraint. t 7 por# inactive after v core and v io applied 50 ms por# must not glitch during active time. t 1 v sbl v sb v core v io pwrbtn# ontcl# pwrcnt[2:1] por# t 4 t 2 t 3 t 1 t 6 t 5 t 7
amd geode? sc3200 processor data book 435 electrical specifications revision 5.1 figure 9-56. power-up sequencing without pwrbtn# timing diagram acpi is non-functional and all acpi outputs are undefined when the power-up sequence does not include using the power button. susp# is an internal signal generated from the ac pi block. without an acpi rese t, susp# can be permanently asserted. if the use_susp bit in ccr2 of gx1 module is enabled (index c2h[7] = 1), the cpu will stop. if acpi functionality is desired, or the situation described above avoided, the power button must be toggled. this can be done externally or internally. gpio63 is internally connec ted to pwrbtn#. to toggle the power button with software, gpio63 must be programmed as an output using the normal gpio programming protocol (s ee section 6.4.1.1 "gpio sup- port registers" on page 240). gpio63 must be pulsed lo w for at least 16 ms and not more than 4 sec. asserting por# has no effect on acpi. if por# is assert ed and acpi was active prior to por#, then acpi will remain active after por#. therefore, bios must ensure th at acpi is inactive before gpio63 is pulsed low. table 9-44. power-up sequence not using the power button timing parameters symbol parameter min max unit comments t 1 voltage sequence -100 100 ms optimum power-up results with t 1 = 0. t 2 por# inactive after v sbl , v core , v sb , and v io applied 50 ms por# must not glitch during active time. t 3 32khz startup time 1 s time required for 32 khz oscilla- tor and 14.318 mhz derived from pll6 to become stable at which time the rtc can reliably count. t 1 v sbl, v core 1 v sb, v io 2 por# t 2 1) v sbl and v core should be tied together. 2) v sb and v io should be tied together. t 3 32khz
436 amd geode? sc3200 processor data book electrical specifications revision 5.1 9.3.16 jtag interface figure 9-57. tck measurement points and timing diagram table 9-45. jtag timing parameters symbol parameter min max unit comments tck frequency 25 mhz t 1 tck period 40 ns t 2 tck high time 10 ns t 3 tck low time 10 ns t 4 tck rise time 4 ns t 5 tck fall time 4 ns t 6 tdo valid delay 3 25 ns t 7 non-test outputs valid delay 3 25 ns 50 pf load t 8 tdo float delay 30 ns t 9 non-test outputs float delay 36 ns t 10 tdi, tms setup time 8 ns t 11 non-test inputs setup time 8 ns t 12 tdi, tms hold time 7 ns t 13 non-test inputs hold time 7 ns v ih(min) v il(max) 1.5v t ck t 1 t 3 t 5 t 2 t 4
amd geode? sc3200 processor data book 437 electrical specifications revision 5.1 figure 9-58. jtag test timing diagram tck t 8 input output tdo tdi, t 11 t 13 t 9 t 7 t 6 t 12 t 10 tms signals signals
438 amd geode? sc3200 processor data book electrical specifications revision 5.1
amd geode? sc3200 processor data book 439 10 package specifications revision 5.1 10.0 package specifications 10.1 thermal characteristics the junction-to-case thermal resistance ( jc ) of the pack- ages shown in table 10-1 can be used to calculate the junction (die) temperature under any given circumstance. note that there is no specification for maximum junction temperature given since the operation of the device is guaranteed to a case temperature range of 0 c to 85 c (see table 9-3 on page 370). as long as the case tempera- ture of the device is maintained within this range, the junc- tion temperature of the die will also be maintained within its allowable operating range. however, the die (junction) tem- perature under a given operating condition can be calcu- lated by using the following equation: t j = t c + (p * jc ) where: t j = junction temperature ( c) t c = case temperature at top center of package ( c) p = maximum power dissipation (w) jc = junction-to-case thermal resistance ( c/w) these examples are given for reference only. the actual value used for maximum power (p) and ambient tempera- ture (t a ) is determined by the system designer based on system configuration, extremes of the operating environ- ment, and whether active thermal management (via sus- pend modulation) of the gx1 module is employed. a maximum junction temperature is not specified since a maximum case temperature is. therefore, the following equation can be used to calculate the maximum thermal resistance required of the thermal solution for a given max- imum ambient temperature: where: cs = max case-to-heatsin k thermal resistance ( c/w) allowed for thermal solution sa = max heatsink-to-ambient thermal resistance ( c/w) allowed for thermal solution t a = max ambient temperature ( c) t c = max case temperature at top center of package ( c) p = maximum power dissipation (w) if thermal grease is used between the case and heatsink, cs will reduce to about 0.01 c/w. therefore, the above equation can be simplified to: where: ca = sa = max heatsink-to-ambient thermal resistance ( c/w) allowed for thermal solution the calculated ca value (examples shown in table 10-2) represents the maximum allowed thermal resistance of the selected cooling solution which is required to maintain the maximum t case (shown in table 9-3 on page 370) for the application in which the device is used. table 10-1. jc (c/w) package max ( c/w) ebga 1 tepbga 5 cs + sa = t c ? t a p ca = t c ? t a p table 10-2. case-to-ambient thermal resistance example @ 85 c core voltage (v core ) (nominal) core frequency maximum power (w) ca for different ambient temperatures ( c/w) 20 c25 c30 c35 c40 c 1.8v 266 mhz 3.32 19.58 18.07 16.57 15.06 13.55
440 amd geode? sc3200 processor data book package specifications revision 5.1 10.1.1 heatsink considerations table 10-2 on page 439 shows the maximum allowed ther- mal resistance of a heatsink for particular operating envi- ronments. the calculated values, defined as ca , represent the required ability of a particular heatsink to transfer heat generated by the sc3200 processor from its case into the air, thereby maintaining the case temperature at or below 85 c. because ca is a measure of thermal resistivity, it is inversely pr oportional to the heatsinks ability to dissipate heat or its thermal conductivity. note: a ?perfect? heatsink would be able to maintain a case temperature equal to that of the ambient air inside the system chassis. looking at table 10-2, it can be seen that as ambient tem- perature (t a ) increases, ca decreases, and that as power consumption of the processor (p) increases, ca decreases. thus, the ability of the heatsink to dissipate thermal energy must increase as the processor power increases and as the temperature inside the enclosure increases. while ca is a useful parameter to calculate, heatsinks are not typically specified in terms of a single ca .this is because the thermal resistivity of a heatsink is not constant across power or temperature. in fact, heatsinks become slightly less efficient as the amount of heat they are trying to dissipate increases. for this reason, heatsinks are typi- cally specified by graphs that plot heat dissipation (in watts) vs. mounting surface (case) temperature rise above ambient (in c). this method is necessary because ambi- ent and case temperatures fluc tuate constantly during nor- mal operation of the system . the system designer must be careful to choose the proper heatsink by matching the required ca with the thermal dissipation curve of the device under the entire range of operating conditions in order to make sure that the maximum case temperature (from table 9-3 on page 370) is never exceeded. to choose the proper heatsink , the system designer must make sure that the calculated ca falls above the curve (shaded area). the curve itself defines the minimum tem- perature rise above ambient that the heatsink can main- tain. figure 10-1 is an example of a particular heatsink under consideration figure 10-1. heatsink example example 1 assume p (max) = 5w and t a (max) = 40 c. therefore: ca = 9 the heatsink must provide a thermal resistance below 9 c/ w. in this case, the heatsink under consideration is more than adequate since at 5w wors t case, it can limit the case temperature rise above ambient to 40 c ( ca =8). example 2 assume p (max) = 9w and t a (max) = 40 c. therefore: ca = 5 in this case, the heatsink under consideration is not ade- quate to limit the case temperature rise above ambient to 45 c for a 9w processor. for more information on thermal design considerations or heatsink properties, refer to the product selection guide of any leading vendor of thermal engineering solutions. note: the power dissipations p used in these examples are not representative of the power dissipation of the sc3200 processor, which is always less than 4 watts. 0 10 20 30 40 50 24 68 10 ca = 45/9 = 5 heat dissipated - watts ca = 45/5 = 9 mounting surface temperature rise above ambient ? c ca = t c ? t a p ca = 85 ? 40 5 ca = t c ? t a p ca = 85 ? 40 9
amd geode? sc3200 processor data book 441 package specifications revision 5.1 10.2 physical dimensions the figures in this section provide the mechanical package out lines for the 432-terminal ebga (enhanced ball grid array) and 481-terminal tepbga (thermally enhanced ball grid array) packages. figure 10-2. 432-terminal ebga package (body size: 40x40x1.72 mm; pitch: 1.27 mm) notes: unless otherwise specified. 1) ebga with lead (pb): a) solder ball composition: sn 63%, pb 37%. b) soldering profile: 220 o c. 2) ebga lead (pb) free: a) solder ball composition: sn 96.5%, ag 3.5%. b) soldering profile: 260 o c 3) dimension is measured at the maximum solder ball diameter, parallel to primary datum n. 4) reference jedec registration mo-151, variation -1.00, dated june 1997. 5) theta junction to case (t jc ) = 1c/watt.
442 amd geode? sc3200 processor data book package specifications revision 5.1 figure 10-3. 481-terminal tepbga package (body size: 40x40x2.38 mm; pitch: 1.27 mm) notes: unless otherwise specified. 1) tepbga with lead (pb): a) solder ball composition: sn 63%, pb 37%. b) soldering profile: 220 o c. 2) tepbga lead (pb) free: a) solder ball composition: sn 96.5%, ag 3.5%. b) soldering profile: 260 o c 3) dimension is measured at the maximum solder ball diameter, parallel to primary datum n. 4) the mold surface area may include dimple for a1 ball corner identification. 5) reference jedec registration ms-034, variation bau-1. 6) theta junction to case (t jc ) = 5c/watt.
amd geode? sc3200 processor data book 443 appendix a: support documentation revision 5.1 appendix a support documentation a.1 order information a.2 data book revision history this document is a report of the revision/creation process of the data book for the geode sc3200. any revisions (i.e., addi- tions, deletions, parameter corrections, etc.) are recorded in the table below. order number (amd opn) 1 1. the ?f? suffix denotes the lead free package. core frequency (mhz) core voltage (v core ) temp. (degree c) package 2 2. as of this publication date, a lead free package version may not be available. check with your local amd sales repre- sentative for availability. see section 10.0 "package s pecifications" on page 439 for details on the lead free part. sc3200ucl-266 266 1.8v 0 - 85 ebga SC3200UCL-266F lead free ebga sc3200ufh-233 233 1.8v 0 - 85 tepbga sc3200ufh-233f lead free tepbga sc3200ufh-266 266 1.8v 0 - 85 tepbga sc3200ufh-266f lead free tepbga table a-1. revision history revision # (pdf date) revisions / comments 0.1 (august 1999) first draft of data book. (for internal review only) 0.2 (october 1999) second draft. 0.5 (january 2000) draft. 0.8 (march 2000) draft 1.0 (july 2000) preliminary data book. 1.1 (august 2000) corrected typos, removed umimplemented features. 1.32 (february 2001) preliminary data book. gnt[1:0]# strapping functions changed. minor modifications and correc- tions. video input port (vip) added. 2.0 (april 2002) the entire data book has been reformatted and se veral sections re-written. strap information and tepbga ball assignments have been added. additionally, internal test signals and multiplexing have been included. this data book should be viewed as a new document.
444 amd geode? sc3200 processor data book appendix a: data book revision history revision 5.1 2.1 (june 2002) release for posting on external web site. changes made to the architecture overview, signal defini- tions, core logic module, video processor module, electrical specifications, and package specifi- cations chapters. see revision 2.1 for details. 2.2 (july 2002) corrected pin definitions for ball k3 on ebga pa ckage and ball d12 on tepbga package. were incorrectly called out as vio, changed to vcore. effected: figure 2-2 "432-ebga ball assignment diagram? table 2-2 ?432-ebga ball assignment - sorted by ball number? table 2-3 ?432-ebga ball assignment - sorted alphabetically by signal name? figure 2-3 ?481-tepbga ba ll assignment diagram? table 2-4 ?481-tepbga ball assign ment - sorted by ball number? table 2-5 ?481-tepbga ball assignment - sorted alphabetically by signal name? section 2.4.20 ?power, ground and no connections? 3.0 (august 2002) major corrections include fixing tepbga ball numbers in ?two-si gnal/group multiplexing? table (table 2-7) and gpio signal descriptions (table 2.4.16). 3.1 (february 2002) many minor changes mostly to the video processo r and electrical sections. expounded on the notes in the mechanical section. 4.0 (march 2003) many changes. changed all references to xpressaudio to audio. see revision 4.0 for details. 5.0 (november 2003) numerous minor changes/corrections made based upon user inputs. see revision 5.0 for details. 5.1 (march 2004) minor changes/corrections made based upon user in puts. see table a-2 "edits to current revision" for details. table a-1. revision history (continued) revision # (pdf date) revisions / comments
amd geode? sc3200 processor data book 445 appendix a: data book revision history revision 5.1 table a-2. edits to current revision section revision section 1.0 "amd geode? sc3200 processor" section 1.2 "features" on page 14: ? other features: modified voltages s ub-bullets for clarification purposes. section 2.0 ?architecture overview? no changes. section 3.0 ?signal definitions? section 3.4.6 "pci bus interface signals" on page 68: ? rewrote serr# description, was wrong. section 3.4.10 "universal serial bus (usb) interface signals" on page 76: ? changed footnote to say ?a 15 k ? pull-down resistor is required on all ports (even if unused).? section 4.0 "general configuration block" table 4-7 "strapped core clock frequency" on page 101: ? added note: ? note: not all speeds are supported. for information on supported speeds, see section a.1 "order information" on page 443.? section 5.0 ?superi/o module? no changes. section 6.0 "core logic module" section 6.2.6.1 "dma controller" on page 168: ? added text in parenthesis to first bullet. now reads as ?standard seven-channel dma support (channels 5 through 7 are not supported).? ? dma channels subsection: added last sentence to last paragraph ?dma channels 5 through 7 are not supported.? section 6.2.6.3 "programmable interrupt controller" on page 171: ? added second sentence to first paragraph, ?the pic devices support all x86 modes of opera- tion except special fully nested mode.? section 6.4.1 "bridge, gpio, and lpc registers - function 0" on page 206: ? f0 index 6ch (rom mask register): corrected reset value to 0000fff0h (was listed as fff0h). added note, ? note: register must be read/written as a dword.? also corrected reset value and ?width? column in table 6-14 on page 192 (register summary table). ? f0bar1+i/o offset 00h: rewrote bit descriptions and added note for clarification purposes. ? f0bar1+offset 0ch: rewrote bit descriptions and added note for clarification purposes. ? f0bar1+offset 10h[13]: changed note. did say ?this bit should not be enabled when using the internal superi/o module and if io_sioc fg_in (f5bar0+i/o offset 00h[26:25]) = 11.? now says ?this bit should not be routed to lpc when using the internal superi/o module and if io_siocfg_in (f5bar0+i/o offset 00h[26:25]) = 10.? section 6.4.2 "smi status and acpi re gisters - function 1" on page 252: ? f1bar0+i/o offset 00h[11] and of fset 02h[11]: clarified that the irq2 is from the sio module and not an external sio. section 6.4.3 "ide controller registers - function 2" on page 273: ? f2 index 40h and 44h: removed format 0 and format 1 settings for a fast-pci clock frequency of 48 mhz since it is not supported. section 6.4.7 "isa legacy register space" on page 313: ? changed register descriptions in table 6-43 and table 6-44 to emphasize that dma channels 5 through 7 are not supported. section 7.0 ?video processor module? no changes.
446 amd geode? sc3200 processor data book appendix a: data book revision history revision 5.1 section 8.0 ?debugging and monitoring? no changes. section 9.0 ?electrical specifications? table 9-2 "absolute maximum ratings" on page 369: ? changed t case min value from -45c to -10c. section 10.0 ?package specifications? section 10.1 "thermal characteristics" on page 439: ? new section. figure 10-3 "481-terminal tepbg a package (body size: 40x40x2. 38 mm; pitch: 1.27 mm)" on page 442: ? removed lot code example from figure. appendix a ?support documentation? updated edits to refl ect current revision. table a-2. edits to current revision (continued) section revision
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